JP4413798B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4413798B2 JP4413798B2 JP2005050795A JP2005050795A JP4413798B2 JP 4413798 B2 JP4413798 B2 JP 4413798B2 JP 2005050795 A JP2005050795 A JP 2005050795A JP 2005050795 A JP2005050795 A JP 2005050795A JP 4413798 B2 JP4413798 B2 JP 4413798B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
Description
図1は、本発明半導体装置の概略断面説明図で、まずこの図1を用いて本発明半導体装置について説明する。
図2(b):次いで、支持体21に、半導体構成体22に対応する部分に開口部を有す絶縁基材25を配置し、加熱加圧して積層する。ここに絶縁基材25としては、例えばガラス繊維にエポキシ樹脂を含浸させたプリプレグなどのシートが好適に使用される。
図3(f):次いで、第一再配線28を含む第一絶縁層26の上面に、第二絶縁層29を積層した後、該第二絶縁層29に非貫通孔27を形成する。
図4(g):次いで、非貫通孔27を含む第二絶縁層29に無電解・電解金属めっきを析出させた後、写真法にて第二接続パッド30aと第二再配線層30の回路形成を行う。
図4(h):次いで、はんだボールによる突起電極形成部以外にソルダーレジスト31を形成する。
図4(i):次いで、半導体構成体22間を絶縁基材25部でダイシング加工により切断個片化し、複数個の半導体装置32を得る。
図5は、図3(d)のA−Aで示す領域の概略平面説明図である。
該図5において、円形状の外部接続用電極bと菱形の外部接続用電極aが混在しているが、当該菱形の外部接続用電極aが、前述の上層の絶縁層26に非貫通孔27を形成する際のアライメントマークとして使用される電極である。
図6(b):次いで、支持体41に、半導体積層体42に対応する部分に開口部を有する絶縁基材45を配置し、加熱加圧して積層する。ここに絶縁基材45としては、前記と同様なものが用いられる。
図7(f):次いで、第一配線48を含む第一絶縁層46の上面に、第二絶縁層49を積層した後、該第二絶縁層49に非貫通孔47を形成する。
図8(g):次いで、非貫通孔47を含む第二絶縁層49に無電解・電解金属めっきを析出させた後、写真法にて第二接続パッド50aと第二再配線50の回路形成を行う。
図8(h):次いで、はんだボールによる突起電極形成部以外にソルダーレジスト51を形成する。
図8(i):次いで、半導体構成体42間を絶縁基材45部でダイシング加工により切断個片化し、複数個の半導体装置52を得る。
図9は、図7(d)のA−Aで示す領域の概略平面説明図である。
該図9において、円形状に形成された金属箔eの開口部dと三角形状に形成された金属箔eの開口部cが混在しているが、当該三角形状の開口部cが、前述の上層の絶縁層46に非貫通孔47を形成する際のアライメントマークとして使用される開口部である。アライメントマークとして使用する金属箔eの開口部cの形状とアライメントマークとして使用しない金属箔eの開口部dの形状を変えることによって、誤認識を防止することができ、より精度よく非貫通孔を形成することが可能となる。
2,22,42:半導体構成体
3,23,43:接着層
4,24,44:外部接続用電極
5,25,45:絶縁基材
6,26,46:第一絶縁層
7,27,47:非貫通孔
8,28,48:第一再配線
8a,28a,48a:第一接続パッド
9,29,49:第二絶縁層
10,30,50:第二再配線
10a,30a,50a:第二接続パッド
11,31,51:ソルダーレジスト
12:突起電極
32,52:半導体装置
46a:金属箔
a:アライメントマークとして使用する外部接続用電極
b:アライメントマークとして使用しない外部接続用電極
c:アライメントマークとして使用する金属箔の開口部
d:アライメントマークとして使用しない金属箔の開口部
e:金属箔
Claims (4)
- 支持体に、各々が半導体基板上に設けられた複数の外部接続用電極を有する複数の半導体構成体を相互に離間させて配置する工程と、前記各半導体構成体に対応する部分に開口部を有する少なくとも1枚の絶縁基材を支持体に配置する工程と、前記絶縁基材を加熱加圧し、積層する工程と、前記半導体構成体及び絶縁基材の上面に上層の再配線のための絶縁層を配置し、積層する工程と、半導体構成体の外部接続用電極の一部をアライメントマークとして、前記絶縁層に非貫通孔を形成する工程と、前記絶縁層に設けられた非貫通孔及び絶縁層の表面に金属めっきを施す工程と、前記絶縁層上に再配線を形成する工程と、前記半導体構成体間を前記絶縁基材部で切断して前記最上層の上層配線接続パッドが前記絶縁基材の上方に配置された半導体装置を複数個得る工程とを有することを特徴とする半導体装置の製造方法。
- アライメントマークとしての外部接続用電極をCCDカメラで認識し、前記外部接続用電極の中央部に対応する位置の絶縁層に非貫通孔を形成することを特徴とする請求項1記載の半導体装置の製造方法。
- 支持体に、各々が半導体基板上に設けられた複数の外部接続用電極を有する複数の半導体構成体を相互に離間させて配置する工程と、前記各半導体構成体に対応する部分に開口部を有する少なくとも1枚の絶縁基材を支持体に配置する工程と、前記絶縁基材を加熱加圧し、積層する工程と、前記半導体構成体及び絶縁基材の上面に上層の再配線のための絶縁層及び金属箔を配置し、積層する工程と、前記金属箔の外部接続用電極の真上部に対応する部位に予め開口部を設ける工程と、前記金属箔の開口部の一部をアライメントマークとして、前記絶縁層に非貫通孔を形成する工程と、前記絶縁層に設けられた非貫通孔及び絶縁層の表面に金属めっきを施す工程と、前記絶縁層上に再配線を形成する工程と、前記半導体構成体間を前記絶縁基材部で切断して前記最上層の上層配線接続パッドが前記絶縁基材の上方に配置された半導体装置を複数個得る工程とを有することを特徴とする半導体装置の製造方法。
- アライメントマークとしての金属箔の開口部をCCDカメラで認識し、前記外部接続用電極の中央部に対応する位置の絶縁層に非貫通孔を形成することを特徴とする請求項3記載の半導体装置の製造方法。
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JP2005050795A JP4413798B2 (ja) | 2005-02-25 | 2005-02-25 | 半導体装置の製造方法 |
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JP4413798B2 true JP4413798B2 (ja) | 2010-02-10 |
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Families Citing this family (5)
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KR100851072B1 (ko) * | 2007-03-02 | 2008-08-12 | 삼성전기주식회사 | 전자 패키지 및 그 제조방법 |
KR100982795B1 (ko) * | 2008-07-10 | 2010-09-16 | 삼성전기주식회사 | 전자소자 내장형 인쇄회로기판 제조방법 |
JP2011187473A (ja) * | 2010-03-04 | 2011-09-22 | Nec Corp | 半導体素子内蔵配線基板 |
JP2011253879A (ja) * | 2010-06-01 | 2011-12-15 | Nec Corp | 半導体素子及び半導体内蔵基板 |
JP5581830B2 (ja) * | 2010-06-11 | 2014-09-03 | 富士通株式会社 | 部品内蔵基板の製造方法及び部品内蔵基板 |
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