JP2010098098A - 電子装置の製造方法 - Google Patents
電子装置の製造方法 Download PDFInfo
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Abstract
【解決手段】ICチップ10の一面のうちはんだ接合される部位に、当該一面より突出しその先端面に鋭利形状をなす鋭利部12が設けられた導電性のポスト11を形成し、基板20の一面のうちはんだ接合される部位に、はんだ30を配置し、次に、ICチップ10と基板20とを互いの一面同士にて対向させ、ICチップ10を基板20側に押し付けてポスト11の鋭利部12ではんだ30の表面に位置する酸化膜を突き破り、この状態ではんだ30をリフローさせる。
【選択図】図2
Description
図1は、本発明の第1実施形態に係るICチップ10の概略断面構成を示す図である。また、図2において(a)は、基板20に搭載する前のICチップ10におけるポスト11部分の拡大断面図、(b)は、基板20に搭載した後のICチップ10におけるポスト11部分の拡大断面図である。
図5(a)、(b)は、本発明の第2実施形態に係る電子装置の製造方法の要部を示す工程図である。この図5では、本製造方法におけるポスト形成工程の要部を示しており、工程途中におけるワークの断面構成を示している。
図6(a)〜(d)は、本発明の第3実施形態に係る電子装置の製造方法の要部を示す工程図である。この図6では、本製造方法におけるポスト形成工程の要部を示しており、工程途中におけるワークの断面構成を示している。また、ここでも、図6(d)に示されるポスト11の最終形態は、本体部11aの表面に上記同様の金メッキ11bが施されたものであるが、図6(d)では、当該金メッキは省略してある。
図8(a)〜(e)は、本発明の第4実施形態に係る電子装置の製造方法の要部を示す工程図である。この図8では、本製造方法におけるポスト形成工程の要部を示しており、(a)、(b)は工程途中におけるワークの平面構成を示し、(c)〜(e)はワークの断面構成を示している。
図9(a)〜(e)は、本発明の第5実施形態に係る電子装置の製造方法の要部を示す工程図である。この図9では、本製造方法におけるポスト形成工程の要部を示しており、工程途中におけるワークの断面構成を示している。
図10(a)〜(c)は、本発明の第6実施形態に係る電子装置の製造方法の要部を示す工程図である。この図10では、本製造方法におけるポスト形成工程の要部を示しており、工程途中におけるワークの断面構成を示している。本実施形態は、ポスト11の先端面に鋭利部12を設ける方法が、上記各実施形態とは相違するものであり、ここでは、その相違点を中心に述べる。
図11(a)〜(c)は、本発明の第7実施形態に係る電子装置の製造方法の要部を示す工程図である。この図11では、本製造方法におけるポスト形成工程の要部を示しており、工程途中におけるワークの断面構成を示している。本実施形態も、ポスト11の先端面に鋭利部12を設ける方法が、上記第1実施形態とは相違するものであり、ここでは、第1実施形態との相違点を中心に述べる。
なお、上記各実施形態では、ポスト11は銅などのメッキで本体部11aを形成し、この本体部11aの先端面をエッチングして鋭利部12を形成し、その後、はんだ濡れ性の向上のために、好ましくは、その表面に金メッキ11bを施すというように、ポスト11をメッキで形成し、鋭利部12をエッチングにより形成した。
11 ポスト
11b 金メッキ
12 鋭利部12
17 凹凸としての凹み
18 針
20 基板
30 はんだ
31 酸化膜
Claims (8)
- ICチップ(10)の一面と基板(20)の一面との間を、はんだ(30)によってはんだ接合してなる電子装置の製造方法において、
前記ICチップ(10)の前記一面のうち前記はんだ接合される部位に、当該一面より突出しその先端面に鋭利形状をなす鋭利部(12)が設けられた導電性のポスト(11)を形成するポスト形成工程と、
前記基板(20)の前記一面のうち前記はんだ接合される部位に、前記はんだ(30)を配置するはんだ配置工程と、
次に、前記ICチップ(10)と前記基板(20)とを互いの前記一面同士にて対向させ、前記ICチップ(10)を前記基板(20)側に押し付けて前記ポスト(11)の前記鋭利部(12)で前記はんだ(30)の表面に位置する酸化膜(31)を突き破り、この状態で前記はんだ(30)をリフローさせるはんだ接合工程と、を備えることを特徴とする電子装置の製造方法。 - 前記ポスト形成工程では、前記ポスト(11)をメッキにより形成することを特徴とする請求項1に記載の電子装置の製造方法。
- 前記ポスト(11)の最表面を金メッキ(11b)により形成することを特徴とする請求項2に記載の電子装置の製造方法。
- 前記ポスト形成工程では、前記ポスト(11)の先端面をエッチングすることにより、前記鋭利部(12)を形成することを特徴とする請求項1ないし3のいずれか1つに記載の電子装置の製造方法。
- 前記ポスト形成工程では、前記ポスト(11)の先端面に粗化メッキを施すか、もしくは当該先端面をエッチングすることにより、当該先端面を、前記鋭利部(12)としての複数の針状突起を有する粗化された面とすることを特徴とする請求項1ないし3のいずれか1つに記載の電子装置の製造方法。
- 前記ポスト形成工程では、前記ICチップ(10)の前記一面のうち前記ポスト(11)が形成される部位に凹凸(17)を設け、その上にメッキを行うことによって、先端面が前記凹凸(17)を継承した形状の凹凸面となっているとともに当該凹凸面の凸部が前記鋭利部(12)として構成されている前記ポスト(11)を形成することを特徴とする請求項1ないし3のいずれか1つに記載の電子装置の製造方法。
- 前記凹凸面の凸部をエッチングして、さらに鋭利な形状に加工することを特徴とする請求項6に記載の電子装置の製造方法。
- 前記ポスト形成工程では、前記ICチップ(10)の前記一面のうち前記ポスト(11)が形成される部位に針(18)を立て、その後、前記針(18)の根元部分にメッキを行い、先端面から突出する前記針(18)の先端が前記鋭利部(12)として構成されている前記ポスト(11)を形成することを特徴とする請求項1ないし3のいずれか1つに記載の電子装置の製造方法。
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Cited By (43)
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JP2012069761A (ja) * | 2010-09-24 | 2012-04-05 | Shinko Electric Ind Co Ltd | 半導体素子、半導体素子実装体及び半導体素子の製造方法 |
US8254155B1 (en) | 2011-10-03 | 2012-08-28 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with orthogonal windows |
US8304881B1 (en) | 2011-04-21 | 2012-11-06 | Tessera, Inc. | Flip-chip, face-up and face-down wirebond combination package |
US8338963B2 (en) | 2011-04-21 | 2012-12-25 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
US8345441B1 (en) | 2011-10-03 | 2013-01-01 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8405207B1 (en) | 2011-10-03 | 2013-03-26 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
US8436477B2 (en) | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate |
US8441111B2 (en) | 2011-10-03 | 2013-05-14 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8502390B2 (en) | 2011-07-12 | 2013-08-06 | Tessera, Inc. | De-skewed multi-die packages |
US8513817B2 (en) | 2011-07-12 | 2013-08-20 | Invensas Corporation | Memory module in a package |
US8513813B2 (en) | 2011-10-03 | 2013-08-20 | Invensas Corporation | Stub minimization using duplicate sets of terminals for wirebond assemblies without windows |
US8525327B2 (en) | 2011-10-03 | 2013-09-03 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
JP2013541858A (ja) * | 2010-11-02 | 2013-11-14 | テッセラ,インコーポレイテッド | ノーフローアンダーフィル |
JP2013239543A (ja) * | 2012-05-15 | 2013-11-28 | Panasonic Corp | 電子部品の実装構造体およびその製造方法 |
US8633576B2 (en) | 2011-04-21 | 2014-01-21 | Tessera, Inc. | Stacked chip-on-board module with edge connector |
US8670261B2 (en) | 2011-10-03 | 2014-03-11 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals |
US8787034B2 (en) | 2012-08-27 | 2014-07-22 | Invensas Corporation | Co-support system and microelectronic assembly |
US8823165B2 (en) | 2011-07-12 | 2014-09-02 | Invensas Corporation | Memory module in a package |
US8848392B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support module and microelectronic assembly |
US8848391B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support component and microelectronic assembly |
US8917532B2 (en) | 2011-10-03 | 2014-12-23 | Invensas Corporation | Stub minimization with terminal grids offset from center of package |
US8928153B2 (en) | 2011-04-21 | 2015-01-06 | Tessera, Inc. | Flip-chip, face-up and face-down centerbond memory wirebond assemblies |
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