CN105826289A - 一种半导体封装结构 - Google Patents

一种半导体封装结构 Download PDF

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CN105826289A
CN105826289A CN201610301968.7A CN201610301968A CN105826289A CN 105826289 A CN105826289 A CN 105826289A CN 201610301968 A CN201610301968 A CN 201610301968A CN 105826289 A CN105826289 A CN 105826289A
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Prior art keywords
solder
semiconductor package
wiring layer
terminal
metal coupling
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施建根
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Nantong Fujitsu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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Priority to CN201610301968.7A priority Critical patent/CN105826289A/zh
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Abstract

本发明公开了一种半导体封装结构。该封装结构包括芯片和载体，该芯片包括芯片主体、设置在芯片主体上的电极以及固定在电极上的金属凸块。该载体包括介电层、形成于介电层上的再布线层以及形成于再布线层上的第一端子，其中第一端子包括焊料。金属凸块由焊料固定于再布线层上。在本发明中，利用金属凸块取代现有技术中的形成于电极上的球状焊料，并利用形成于再布线层上的第一端子中的焊料将金属凸块固定于再布线层上，可有效避免电极间的桥接以及焊料中的α射线对芯片性能的影响。进一步，所形成的半导体封装结构中端子的节距减小，使在小尺寸芯片上实现多端子成为可能。

Description

一种半导体封装结构
技术领域
本发明涉及半导体技术领域，特别是涉及一种半导体封装结构。
背景技术
近年来，半导体器件在成本降低和前道晶圆制造工艺的提升的共同促进下，实现了同样功能的半导体器件的单体芯片尺寸越来越小的目标，这样会导致半导体器件上用于外接的电极之间的节距越来越小，原来的用于倒装焊的半导体器件结构容易引起电极之间的桥接从而导致半导体器件失效。
目前，用于倒装焊的半导体器件结构中，半导体芯片与再布线基板间的连接一般是通过在电极上进行金属焊料回流后形成球状凸点，然后倒装在再布线基板而形成。如图1所示，是现有技术提供的半导体封装结构的结构示意图。半导体芯片101上设置有电极102，在半导体芯片101和电极102上可选择性地覆盖有氧化硅或氮化硅等材料形成的钝化层103，在钝化层103上再可选择性地形成一层由聚酰亚胺PI、PBO等形成的保护层104。然后，通过溅射加电镀的工艺在电极102表面形成UBM金属层105和电镀金属焊料106，典型的UBM金属层105由溅射的钛层和铜层组成的金属层107以及电镀镍层108组成。金属焊料106回流后形成球状凸点(如图1所示)，最后倒装在再布线层200上，形成图1所示的现有倒装芯片封装结构。
在这种倒装芯片封装结构中，虽然在结构上满足了倒装芯片封装结构的要求，但是由于金属焊料106直接形成于电极上，容易引起电极之间的桥接。此外，金属焊料106靠近半导体芯片设置，导致金属焊料106中的α射线对芯片性能造成影响。另一方面，现有技术再布线层200采用复杂的刻蚀工艺形成，生产成本高且层厚难以随半导体器件对电流大小的设计需求进行调整。
发明内容
本发明主要解决的技术问题是提供一种半导体封装结构，用以有效避免电极间的桥接以及金属焊料中的α射线对芯片性能造成的影响。
为解决上述技术问题，本发明采用的一个技术方案是提供一种半导体封装结构，所述封装结构包括：芯片，包括芯片主体、设置在所述芯片主体上的电极以及固定在所述电极上的金属凸块；
载体，包括介电层、形成于所述介电层上的再布线层以及形成于所述再布线层上的第一端子，其中所述第一端子包括焊料，所述金属凸块由所述焊料固定于所述再布线层上。
其中，所述金属凸块由所述焊料以回流焊方式固定于所述再布线层上。
其中，所述金属凸块以超声波焊接方式固定于所述电极上。
其中，所述金属凸块的横向尺寸小于所述电极的横向尺寸。
其中，所述焊料的横向尺寸大于所述金属凸块的横向尺寸，以使得所述金属凸块插置于所述焊料中。
其中，所述金属凸块插置于所述焊料中的端部呈尖端状设置。
其中，所述第一端子进一步包括金属柱，所述金属柱形成于所述再布线层上，所述焊料形成于所述金属柱的朝向所述芯片主体的端部上。
其中，所述芯片进一步包括覆盖于所述芯片主体和所述电极上的钝化层，所述钝化层上设置有开口，所述电极经所述开口至少部分外露，所述金属凸块固定于所述电极的外露部分上且突出于所述钝化层。
其中，所述介电层上设置有开口，所述载体进一步包括形成于所述开口内且与所述再布线层电性接触的第二端子。
其中，所述第二端子和所述再布线层由电镀工艺一体成型。
本发明的有益效果是：本发明利用金属凸块取代现有技术中的形成于电极上的球状焊料，并利用形成于再布线层上的第一端子中的焊料将金属凸块固定于再布线层上，可有效避免电极间的桥接以及焊料中的α射线对芯片性能的影响。进一步，所形成的半导体封装结构中端子的节距减小，使在小尺寸芯片上实现多端子成为可能。
附图说明
图1是现有技术提供的半导体封装结构的结构示意图；
图2是本发明提供的半导体封装结构实施方式一的结构示意图；
图3是本发明提供的半导体封装结构实施方式二的结构示意图；
图4是图2所示的半导体封装结构的制造方法的流程示意图；
图5a-图5j为图4所示的制造方法中各步骤中半导体封装结构的断面图；
图6是图4所示的制造方法的步骤S4的备选实施方式的断面图。
具体实施方式
下面结合附图和实施方式对本发明进行详细说明，附图中各部分的尺寸仅为示意，并不代表实际器件的尺寸。
请参阅图2，图2是本发明提供的半导体封装结构实施方式一的结构示意图。如图2所示，该半导体封装结构包括芯片300和载体400。进一步，芯片300包括芯片主体301、设置在芯片主体301上的电极302以及固定在电极302上的金属凸块303。在优选实施例中，金属凸块303以超声波焊接方式(例如，热压超声波焊接)固定于电极302上，且金属凸块303的横向尺寸D1小于电极32的横向尺寸D2。
在本实施例中，芯片300进一步包括覆盖于芯片主体301和电极302上的钝化层304，钝化层304上设置有开口304a，电极302经开口304a至少部分外露，金属凸块303固定于电极302的外露部分上且突出于钝化层304。钝化层304可以包括氮化硅、氧化硅、其它绝缘体或者他们的组合或多层结构。
载体400包括介电层401、形成于介电层401上的再布线层402以及形成于再布线层402上的第一端子403。介电层401的材料可以为聚酰亚胺、PBO等。在本实施例中，第一端子403包括焊料404和金属柱405。其中，金属柱405形成于再布线层402上，焊料404形成于金属柱405的朝向芯片主体301的端部上。金属凸块303由焊料404固定于再布线层402上。在优选实施例中，金属凸块303由焊料404以回流焊方式固定于再布线层402上。具体来说，将金属凸块303倒扣在焊料404上，焊料404回流使金属凸块303置于焊料404中并固定。金属凸块303的形状不限，材料可以包括铜、金、锡中的至少一种，优选的，金属凸块303的材料进一步包括钛。金属凸块的形状优选为柱状。金属柱405的材料优选为铜。
在优选实施例中，焊料404的横向尺寸D3大于金属凸块303的横向尺寸D1，以使得金属凸块303插置于焊料404中。进一步优选的，金属凸块303插置于焊料404中的端部呈尖端状设置。
在本实施例中，介电层401上设置有开口401a，载体400进一步包括形成于开口401a内且与再布线层402电性接触的第二端子406。本实施例中载体400只包括一层再布线层402和第二端子406，在其他实施例中也可以包括至少两层再布线层和/或第二端子。在优选实施例中，第二端子406和再布线层402的材料相同，例如铜，且由电镀工艺一体成型。当然，第二端子406和再布线层402的材料可以不同，也可以通过不同的工艺形成，例如先采用电镀工艺形成材料为铜的再布线层402，然后采用网版印刷形成材料为锡的第二端子406。
可以根据半导体器件对电流大小的设计需求调控第二端子406和再布线层402的厚度，通过简单的工艺操作，使其应用于不同规格的半导体器件。
进一步，芯片300和载体400之间的间隙由填充材料500进行填充且在第二端子406的端部可通过微腐蚀及植球回流焊接形成球状焊料块406a。
通过上述方式，利用金属凸块取代现有技术中的形成于电极上的球状焊料，并利用形成于再布线层上的第一端子中的焊料将金属凸块固定于再布线层上，可有效避免电极间的桥接。同时，由于焊料相较于现有技术远离芯片主体，进而避免焊料中的α射线对芯片性能的影响。进一步，上述半导体封装结构中端子的节距减小，使在小尺寸芯片上实现多端子成为可能。此外，使用再布线层取代传统基板，没有传统基板上的保护层，降低寄生电阻。金属柱的存在可以增加芯片与再布线层之间的间距，进行填充时有利于填充材料的扩散。
请参阅图3，其中图3是本发明提供的半导体封装结构实施方式二的结构示意图。
如图3所示，该半导体封装结构包括芯片600和载体700。图3所示的实施例与图2所示的实施例的区别之处在于，芯片600上的金属凸块603由直接形成于再布线层702上的焊料704进行固定。
请参阅图4以及图5a-图5j，图4是图2所示的半导体封装结构的制造方法的的流程示意图；图5a-图5j为本发明各步骤中半导体封装结构的断面图。如图4所示，该半导体封装结构的制造方法具体包括如下步骤：
S1：提供一基材S。
在本步骤中，基材S可以是硅材、不锈钢、铜板、杂质铁等，优选为杂质铁，成本低且后道工艺中易去除。
S2：在基材S上形成介电层401。
在本步骤中，优选在介电层401形成多个开口401a，如图5a所示。介电层401的材料可以为聚酰亚胺、PBO等。
S3：在介电层401上形成再布线层402。
在本步骤中，首先在介电层401上形成第一掩膜层407，并对第一掩膜层407进行曝光及显影处理，以在第一掩膜层407上形成至少暴露第一开口401a的第二开口407a，如图5b所示。
进一步，以第一掩膜层407为掩膜在第一开口401a内形成第二端子406且在第二开口407a内形成再布线层402，并剥离第一掩膜层407，如图5c所示。在优选实施例中，第二端子406和再布线层402的材料相同，例如铜，且通过电镀工艺一体形成。当然，第二端子406和再布线层402的材料可以不同，也可以通过不同的工艺形成，例如先采用电镀工艺形成材料为铜的再布线层402，然后采用网版印刷形成材料为锡的第二端子406。
可根据电流大小的设计需求调控第二端子406和再布线层402的厚度，通过简单的工艺操作，使其应用于不同规格的半导体器件。进一步的，可以重复执行本步骤以根据需要形成至少两层再布线层和/或第二端子。
S4：在再布线层402上形成第一端子403。
在本步骤中，在再布线层402上形成第二掩膜层408，并对第二掩膜层408进行曝光及显影处理，以在第二掩膜层408上形成部分暴露再布线层402的第三开口408a，如图5d所示。
进一步，在第三开口408a内形成金属柱405，并在金属柱405的远离再布线层402的端部上形成焊料404，如图5e所示。剥离第二掩膜层408，露出金属柱405和焊料404，如图5f所示。金属柱405的材料优选为铜。在优选实施例中，通过电镀或其他适当工艺在第三开口408a内依次形成金属柱405和焊料404，此时焊料404为厚度一致的层状结构。在备选实施方式中，可仅在第三开口408a内形成金属柱405，并对金属柱405的端部进行微腐蚀并通过植球回流焊工艺在金属柱405端部上形成焊料404。此外，还可以通过印刷工艺形成焊料404，此时焊料404的厚度不一定一致。
S5：提供一芯片300，包括芯片主体301、设置在芯片主体301上的电极302以及固定在电极302上的金属凸块303，如图5g所示。
金属凸块303的形状不限，材料可以包括铜、金、锡中的至少一种，优选的，金属凸块303的材料进一步包括钛。金属凸块的形状优选为柱状。在本步骤中，优选通过超声波焊接工艺(例如，热压超声波焊接)将金属凸块303固定于电极302上。
S6：利用焊料404将金属凸块303固定于再布线层402上。
在本步骤中，优选通过回流焊工艺将金属凸块303固定于再布线层402上。此时，焊料404回流后部分隆起，进而将金属凸块303的端部包裹，如图5h所示。
S7：利用填充材料500对芯片300、再布线层402和第一端子403进行填充，如图5i所示；
S8：从介电层401去除基材S，如图5j所示。
可以通过撕除、研磨、腐蚀等方式去除基材S。
进一步，还可以在在第二端子406的端部可通过微腐蚀及植球回流焊接形成球状焊料406a。
参照图6，图6为图4所示的步骤S4的备选实施方式的截面示意图。
在本实施例中，介电层801、再布线层802以及第二端子801以与图4相同的方式形成于基材S上，其与图4所示的实施例的不同之处在于，在再布线层802上以电镀或印刷方式直接形成焊料804。例如，在对再布线层802上的第二掩膜层进行曝光及显影处理，进而形成第三开口(与图4所示实施例相同)，通过电镀或印刷工艺在第三开口内形成焊料804，以使得焊料804直接接触再布线层802。焊料804优选为厚度一致的层状结构，并在回流过程中部分隆起。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明专利保护范围内。

Claims (10)

1.一种半导体封装结构，其特征在于，所述封装结构包括：
芯片，包括芯片主体、设置在所述芯片主体上的电极以及固定在所述电极上的金属凸块；
载体，包括介电层、形成于所述介电层上的再布线层以及形成于所述再布线层上的第一端子，其中所述第一端子包括焊料，所述金属凸块由所述焊料固定于所述再布线层上。
2.根据权利要求1所述的半导体封装结构，其特征在于，所述金属凸块由所述焊料以回流焊方式固定于所述再布线层上。
3.根据权利要求1所述的半导体封装结构，其特征在于，所述金属凸块以超声波焊接方式固定于所述电极上。
4.根据权利要求1所述的半导体封装结构，其特征在于，所述金属凸块的横向尺寸小于所述电极的横向尺寸。
5.根据权利要求1所述的半导体封装结构，其特征在于，所述焊料的横向尺寸大于所述金属凸块的横向尺寸，以使得所述金属凸块插置于所述焊料中。
6.根据权利要求5所述的半导体封装结构，其特征在于，所述金属凸块插置于所述焊料中的端部呈尖端状设置。
7.根据权利要求1所述的半导体封装结构，其特征在于，所述第一端子进一步包括金属柱，所述金属柱形成于所述再布线层上，所述焊料形成于所述金属柱的朝向所述芯片主体的端部上。
8.根据权利要求1所述的半导体封装结构，其特征在于，所述芯片进一步包括覆盖于所述芯片主体和所述电极上的钝化层，所述钝化层上设置有开口，所述电极经所述开口至少部分外露，所述金属凸块固定于所述电极的外露部分上且突出于所述钝化层。
9.根据权利要求1所述的半导体封装结构，其特征在于，所述介电层上设置有开口，所述载体进一步包括形成于所述开口内且与所述再布线层电性接触的第二端子。
10.根据权利要求9所述的半导体封装结构，其特征在于，所述第二端子和所述再布线层由电镀工艺一体成型。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009147220A (ja) * 2007-12-17 2009-07-02 Toshiba Corp 半導体装置の製造方法及び半導体装置
US7569935B1 (en) * 2008-11-12 2009-08-04 Powertech Technology Inc. Pillar-to-pillar flip-chip assembly
CN101604638A (zh) * 2009-06-26 2009-12-16 江阴长电先进封装有限公司 圆片级扇出芯片封装方法
JP5056718B2 (ja) * 2008-10-16 2012-10-24 株式会社デンソー 電子装置の製造方法
CN103972111A (zh) * 2014-05-22 2014-08-06 南通富士通微电子股份有限公司 引线框架结构的形成方法
CN104282648A (zh) * 2013-07-10 2015-01-14 矽品精密工业股份有限公司 半导体装置及其制法
CN104409434A (zh) * 2014-08-28 2015-03-11 南通富士通微电子股份有限公司 半导体器件封装结构

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009147220A (ja) * 2007-12-17 2009-07-02 Toshiba Corp 半導体装置の製造方法及び半導体装置
JP5056718B2 (ja) * 2008-10-16 2012-10-24 株式会社デンソー 電子装置の製造方法
US7569935B1 (en) * 2008-11-12 2009-08-04 Powertech Technology Inc. Pillar-to-pillar flip-chip assembly
CN101604638A (zh) * 2009-06-26 2009-12-16 江阴长电先进封装有限公司 圆片级扇出芯片封装方法
CN104282648A (zh) * 2013-07-10 2015-01-14 矽品精密工业股份有限公司 半导体装置及其制法
CN103972111A (zh) * 2014-05-22 2014-08-06 南通富士通微电子股份有限公司 引线框架结构的形成方法
CN104409434A (zh) * 2014-08-28 2015-03-11 南通富士通微电子股份有限公司 半导体器件封装结构

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
刘汉诚、李世玮著，贾松良、王水弟、蔡坚译: "《芯片尺寸封装：设计、材料、工艺、可靠性及应用》", 31 October 2003, 清华大学出版社 *
田民波: "《电子封装工程》", 30 September 2003, 清华大学出版社 *

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