CN105593986B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN105593986B
CN105593986B CN201380079870.6A CN201380079870A CN105593986B CN 105593986 B CN105593986 B CN 105593986B CN 201380079870 A CN201380079870 A CN 201380079870A CN 105593986 B CN105593986 B CN 105593986B
Authority
CN
China
Prior art keywords
insulating layer
expansion coefficient
linear expansion
wiring
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201380079870.6A
Other languages
English (en)
Other versions
CN105593986A (zh
Inventor
下手义和
马场伸治
岩崎俊宽
中川和之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of CN105593986A publication Critical patent/CN105593986A/zh
Application granted granted Critical
Publication of CN105593986B publication Critical patent/CN105593986B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16052—Shape in top view
    • H01L2224/16055—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16105—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1712—Layout
    • H01L2224/1713—Square or rectangular array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053—Oxides composed of metals from groups of the periodic table
    • H01L2924/0544—14th Group
    • H01L2924/05442—SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/186—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/2064—Length ranges larger or equal to 1 micron less than 100 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09427—Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10704—Pin grid array [PGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0465—Shape of solder, e.g. differing from spherical shape, different shapes due to different solder pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种实施方式的半导体装置(SP1)，在配线基板2的基材层(2CR)与半导体芯片(3)之间层叠有与基材层紧贴的阻焊膜(第1绝缘层、SR1)以及与阻焊膜和半导体芯片紧贴的树脂体(第2绝缘层、4)。另外，阻焊膜的线膨胀系数在基材层的线膨胀系数以上，阻焊膜的线膨胀系数在树脂体的线膨胀系数以下，并且基材层的线膨胀系数小于树脂体的线膨胀系数。通过上述结构，能够抑制由温度循环负荷引起的半导体装置的损伤，提高可靠性。

Description

半导体装置及其制造方法
技术领域
本发明例如涉及在配线基板的阻焊膜上隔着树脂体而搭载了半导体芯片的半导体装置及其制造方法。
背景技术
在日本特开2013-12648号公报(专利文献1)中，记载了在配线基板的阻焊膜上隔着底部填充树脂而搭载有半导体芯片的半导体装置及其制造方法。在专利文献1中，记载了在从阻焊膜露出的焊接引线的狭窄部上配置突起电极并经由焊接材料连接。
另外，在日本特开2000-77471号公报(专利文献2)中，记载了在从阻焊膜露出的焊接引线(导体图案)的宽度大的部分配置突起电极(凸块)并经由焊接材料连接。
另外，在日本特开2007-266136号公报(专利文献3)中，记载了分别在形成于配线基板的上表面以及下表面的阻焊层中包含玻璃纤维布，从而强化配线基板的力学强度。
现有技术文献
专利文献
专利文献1：日本特开2013-12648号公报
专利文献2：日本特开2000-77471号公报
专利文献3：日本特开2007-266136号公报
发明内容
发明所要解决的课题
例如如上述专利文献1的图2所示，BGA(Ball Grid Array，球栅阵列)型的半导体装置由配线基板、在该配线基板上搭载的半导体芯片以及保护(或者固定)该半导体芯片的树脂体等构成。另外，搭载半导体芯片的配线基板具备基材层、形成于该基材层的正反面的配线层以及覆盖该配线层的阻焊膜。
这样，1个半导体装置由多种材料构成。另外，各材料的热膨胀率也多种多样。换言之，各材料的热膨胀率不限于彼此相同。
因此，如果对这样的半导体装置施加反复进行温度上升、温度降低的温度循环负荷，则在构成半导体装置的各材料的连接界面等处产生应力，判明是成为半导体装置的可靠性降低的原因。
其他课题与新的特征将根据本说明书的叙述以及附图变得明确。
用于解决课题的技术方案
一种实施方式的半导体装置，在配线基板的基材层与半导体芯片之间，层叠有与所述基材层紧贴的第1绝缘层以及与所述第1绝缘层和所述半导体芯片紧贴的第2绝缘层。另外，所述第1绝缘层的线膨胀系数在所述基材层的线膨胀系数以上，所述第1绝缘层的线膨胀系数在所述第2绝缘层的线膨胀系数以下，并且所述基材层的线膨胀系数小于所述第2绝缘层的线膨胀系数。
发明效果
根据上述一种实施方式，能够提高半导体装置的可靠性。
附图说明
图1是示出作为一种实施方式的半导体装置的芯片搭载面侧的整体构造的俯视图。
图2是示出图1所示的半导体装置的安装面(相反面)侧的俯视图。
图3是示出沿着图1的A-A线的剖视图。
图4是去除图1所示的半导体芯片以及树脂体而示出配线基板的芯片搭载面侧的俯视图。
图5是示出图1所示的半导体芯片的正面(与配线基板的对置面)侧的俯视图。
图6是示出将图3所示的半导体芯片与配线基板电连接的部分的放大剖视图。
图7是示出与图6所示的剖面对应的放大俯视图。
图8是示出使用图1～图7说明的半导体装置的制造工序的概要的说明图。
图9是示出在图8所示的基板准备工序中准备的配线基板的整体构造的俯视图。
图10是示出沿着图9的A-A线的放大剖视图。
图11是示出在图8所示的晶圆准备工序中准备的半导体晶圆的俯视图。
图12是示出形成于图11所示的半导体晶圆的一个芯片区域的焊盘的周边的放大剖视图。
图13是示出在图12所示的多个焊盘上形成有基底金属膜以及突起电极的状态的放大剖视图。
图14是示出在图13所示的突起电极的前端面上安装有焊接材料的状态的放大剖视图。
图15是示出去除了图14所示的掩模的状态的放大剖视图。
图16是示出对图15所示的焊接材料进行加热而使其变形为圆顶形状的状态的放大剖视图。
图17是示出在图12所示的配线基板上搭载有半导体芯片的状态的放大剖视图。
图18是示出在配线基板上配置有半导体芯片时的突起电极与端子的平面位置关系的放大俯视图。
图19是示出沿着图18的A-A线的放大剖视图。
图20是示出图19所示的焊接材料一体化后的状态的放大剖视图。
图21是示出向图17所示的半导体芯片与配线基板之间供给了底部填充树脂的状态的放大剖视图。
图22是示出在图21所示的配线基板的多个焊接区(land)上接合有焊锡球的状态的放大剖视图。
图23是示出在图8所示的单片化工序中对多片的配线基板实施单片化的情况的剖视图。
图24是示出针对图6所示的半导体装置的变形例的放大剖视图。
图25是示出针对图6所示的半导体装置的其他变形例的放大剖视图。
图26是示出针对图7所示的半导体装置的变形例的放大俯视图。
图27是示出针对图3所示的半导体装置的变形例的放大俯视图。
图28是示出将图27所示的半导体芯片与配线基板电连接的部分的放大剖视图。
图29是示出针对图7所示的半导体装置的其他变形例的放大剖视图。
图30是示出针对图7所示的半导体装置的其他变形例的放大剖视图。
图31是示出针对图6所示的半导体装置的其他变形例的放大剖视图。
图32是示出针对图6所示的半导体装置的其他变形例的放大剖视图。
图33是示出针对图3所示的半导体装置的其他变形例的放大剖视图。
图34是示出作为针对图6的比较例的半导体装置的放大剖视图。
具体实施方式
(本申请中的记载形式/基本的用语/用法的说明)
在本申请中，实施方式的记载根据需要，为了方便说明而分成多个部分等来记载，但除了在特别明示的情况下，它们并非相互独立，不论记载的前后，单一例子的各部分，一方是另一方的部分详情或者部分或者全部的变形例等。另外，原则上，省略对相同的部分重复说明。另外，实施方式中的各结构要素除了在特别明示并非如此的情况、理论上限定于该数的情况以及根据上下文明显并非如此的情况下之外，并不是必需的。
同样地在实施方式等的记载中，关于材料、组成等，即使说“由A构成的X”等，除了在特别明示并非如此的情况以及根据上下文明显并非如此的情况下之外，也并非排除包含A以外的要素的情况。例如，如果提及分量，则表示“作为主要成分而包含A的X”等的意义。例如，即使说“硅部件”等，也不限定于纯的硅，还包含硅/锗(SiGe)合金、其他以硅为主要成分的多元合金、包含其他添加物等的部件，这自不待言。另外，即使说镀金、Cu层、镀镍等，除了在特别明示并非如此的情况下，也不仅仅是纯的，分别包含以金、Cu、镍等为主要成分的部件。
进一步地，在提及确定的数值、数量时，除了在特别明示并非如此的情况、理论上限定于该数的情况以及根据上下文明显并非如此的情况下以外，既可以是超过该确定的数值的数值，也可以是低于该确定的数值的数值。
另外，在实施方式的各图中，用同一或者类似的记号或者参照标号表示同一或者同样的部分，原则上不重复说明。
另外，在本申请中，有时使用上表面或者下表面这样的用语，但由于在半导体封装的安装方式中存在各种方式，因此在安装半导体封装之后，也有时例如将上表面配置在下表面的下方。在本申请中，将半导体芯片的元件形成面侧的平面记载为正面，将正面的相反侧的面记载为背面。另外，将配线基板的芯片搭载面侧的平面记载为上表面或者正面，将位于上表面的相反侧的面记载为下表面。
另外，在附图中，在反而变得繁琐的情况或者与空隙的区别明确的情况下，即使是剖面，有时也省略阴影线等。与此相关联地，在根据说明等明确的情况下等，即使是平面性地闭合的孔，有时也省略背景的轮廓线。进而，即使不是剖面，为了明示不是空隙或者为了明示区域的边界，有时也附加阴影线、点状图。
<半导体装置>
首先，使用图1～图5说明本实施方式的半导体装置SP1的概要结构。图1是示出本实施方式的半导体装置的芯片搭载面侧的整体构造的俯视图。另外，图2是示出图1所示的半导体装置的安装面(相反面)侧的俯视图。另外，图3是沿着图1的A-A线的剖视图。另外，图4是去除图1所示的半导体芯片以及树脂体而示出配线基板的芯片搭载面侧的俯视图。另外，图5是示出图1所示的半导体芯片的正面(与配线基板的对置面)侧的俯视图。
此外，在图2～图5中，为了容易观察，减少端子数，比以下说明的数值例更大地图示。端子(焊盘3PD、焊接指状部2BF或者焊锡球SB等)的数量不限定于图2～图5所示的方式。例如，能够应用于焊盘3PD、焊接指状部2BF、焊锡球SB等端子的数量分别为100个～10000个左右的半导体装置。另外，在图5中，为了示出焊盘3PD以及突起电极3BP的俯视时的构造，还一并示出了将多个焊盘3PD中的2个放大的局部放大俯视图。
本实施方式的半导体装置SP1具有配线基板2、搭载于配线基板2上的半导体芯片3(参照图1、图3)以及形成于配线基板2与半导体芯片3之间的树脂体(绝缘层、底部填充材料、密封材料、粘接材料、芯片焊接材料)4。
如图3所示，配线基板2具有搭载了半导体芯片3的上表面(面、主面、芯片搭载面)2a、与上表面2a相反侧的下表面(面、主面、安装面)2b、以及配置于上表面2a与下表面2b之间的侧面2s(参照图1～图3)，如图2以及图3所示，在俯视时形成为四边形的外形形状。在图1以及图2所示的例子中，配线基板2的平面尺寸(俯视时的尺寸、上表面2a以及下表面2b的尺寸、外形尺寸)形成为例如一边的长度为12mm～60mm左右的四边形。另外，配线基板2的厚度(高度)、即图4所示的从上表面2a到下表面2b的距离例如为0.3mm～1.3mm左右。
配线基板2是用于将在上表面2a侧搭载的半导体芯片3与未图示的安装基板电连接的中介层，具有将作为芯片搭载面的上表面2a侧与作为安装面的下表面2b侧电连接的多个配线层(在图2所示的例子中为两层)。配线基板2具有上表面(面、第1面、主面、焊接指状部形成面)2CRa以及位于上表面2CRa的相反侧的下表面(面、第2面、主面、焊接区形成面)2CRb，具备例如由使树脂浸渍到玻璃纤维(纤维材料)而得到的预浸材料构成的基材层(核心层、绝缘层)2CR。在基材层2CR的上表面2CRa以及下表面2CRb，分别形成配线层。
在形成于基材层2CR的上表面2CRa的配线层中，形成了多个导体图案，在该导体图案中，如图3所示包含作为用于将半导体芯片3与配线基板2电连接的端子的多个焊接指状部(端子、电极、内部接口端子)2BF。焊接指状部2BF的详细构造在后面叙述。另外，在形成于基材层2CR的下表面2CRb的配线层中，形成有多个导体图案，在该导体图案中，如图3所示包含作为连接半导体装置SP1的外部端子即多个焊锡球SB的端子的多个焊接区(端子、电极、外部接口端子、外部端子)2LD。
焊接指状部2BF、焊接区2LD等导体图案是例如通过镀敷法形成的金属膜，由例如以铜(Cu)为主体的金属构成。另外，焊接指状部2BF、焊接区2LD等导体图案的厚度(膜厚)例如是5μm～30μm左右。
此外，在图2中，以容易判明本申请的技术思想的方式进行说明，因此使配线层构造简化，列举两层构造的配线基板2来进行说明，但配线层的数量不限定于两层，例如，也可以是3层以上。关于具有3层以上的配线层的配线基板的变形例，在后面叙述。
另外，在基材层2CR的上表面2CRa，形成作为包含树脂的绝缘层的阻焊膜(绝缘层)SR1，上表面2CRa的大部分被阻焊膜SR1覆盖。另外，如图4所示，在阻焊膜SR1形成开口部Sk1，在开口部Sk1，多个焊接指状部2BF各自的一部分从阻焊膜SR1露出。在图4所示的例子中，开口部Sk1跨过多个焊接指状部2BF地形成。换言之，多个焊接指状部2BF各自的一部分在一个开口部Sk1中一并从阻焊膜SR1露出。
另外，在基材层2CR的下表面2CRb，形成作为包含树脂的绝缘层的阻焊膜(绝缘层)SR2，下表面2CRb的大部分被阻焊膜SR2覆盖。另外，如图3所示，在阻焊膜SR2形成多个开口部Sk2，在开口部Sk2，多个焊接区2LD各自的一部分从阻焊膜SR2露出。在图3所示的例子中，开口部Sk2与多个焊接区2LD分别对应地形成。换言之，在多个焊接指状部2BF分别单独地形成开口部Sk2，在多个开口部Sk2中，多个焊接指状部2BF分别从阻焊膜SR2露出。
阻焊膜SR1以及阻焊膜SR2的详细的构造在后面叙述，但在本实施方式中，阻焊膜SR1以及阻焊膜SR2分别通过使多个填料粒子以及树脂浸渍到玻璃纤维而形成。另外，关于阻焊膜SR1以及阻焊膜SR2的厚度(膜厚)中的覆盖导体图案的部分的厚度为5μm～35μm左右。
另外，基材层2CR的上表面2CRa侧的配线层与下表面2CRb侧的配线层经由多个通孔配线2TW相互电连接，所述多个通孔配线2TW在被设置成从上表面2CRa与下表面2CRb中的一方贯通到另一方的多个贯通孔(通孔)内分别形成。通孔配线2TW例如通过镀敷法形成，与焊接指状部2BF、焊接区2LD等导体图案同样地，由例如以铜(Cu)为主体的金属构成。
另外，在图3所示的例子中，对多个焊接区2LD分别连接了焊锡球(焊接材料、外部端子、电极、外部电极)SB。焊锡球SB是在将半导体装置SP1安装到未图示的安装基板时将安装基板侧的多个端子(省略图示)与多个焊接区2LD电连接的导电性部件。换言之，焊锡球SB是半导体装置SP1的外部端子。
焊锡球SB是例如掺有铅(Pb)的Sn-Pb焊接材料、由实质上不包含Pb的所谓无铅焊料构成的焊接材料。作为无铅焊料的例子，可列举例如纯锡(Sn)、锡-铋(Sn-Bi)、或者锡-铜-银(Sn-Cu-Ag)、锡-铜(Sn-Cu)等。此处，无铅焊料意味着铅(Pb)的含量为0.1wt％以下，该含量被确定为RoHS(Restriction of Hazardous Substances，关于限制在电子电器设备中使用某些有害成分的指令)指令的基准。
另外，如图2所示，多个焊锡球SB配置成矩阵状(阵列状、方阵状)。换言之，多个焊锡球SB沿着配线基板2的下表面2b的边且在多列配置。另外，接合多个焊锡球SB的多个焊接区2LD也配置呈矩阵状(方阵状)。这样，将在配线基板2的安装面侧矩阵状地配置多个外部端子(焊锡球SB、焊接区2LD)的半导体装置称为面阵型的半导体装置。面阵型的半导体装置能够将配线基板2的安装面(下表面2b)侧作为外部端子的配置空间进行有效地利用，因此即使外部端子数量增大，也能够抑制半导体装置的安装面积的增大，在这一点上是优选的。即，能够以节省空间的方式安装伴随着高功能化、高集成化而外部端子数量增大的半导体装置。
另外，如图1以及图3所示，半导体装置SP1具有在配线基板2上搭载的半导体芯片3。半导体芯片3具备正面(主面、上表面)3a(参照图3)、与正面3a相反侧的背面(主面、下表面)3b以及位于正面3a与背面3b之间的侧面3s。另外，如图1所示，半导体芯片3以在俯视时平面面积比配线基板2小的四边形的外形形状形成。在图1所示的例子中，半导体芯片3以四个侧面3s分别沿着配线基板2的四个侧面2s的各侧面延伸的方式，搭载于配线基板2的上表面2a的中央部。
另外，如图5所示，半导体芯片3具备形成于正面3a侧的多个焊盘(焊接焊盘)3PD。在图5所示的例子中，多个焊盘3PD在正面3a的周缘部并且沿着正面3a的各边(沿着侧面3s)形成。另外，在图3所示的例子中，半导体芯片3在正面3a侧与配线基板2的上表面2a侧对置的状态下，隔着多个突起电极3BP而搭载于配线基板2上。这样的搭载方式被称为面朝下(Face-down)安装方式、或者倒装片连接方式。
半导体芯片3(详细而言，是作为半导体芯片3的基材的半导体基板)例如由硅(Si)构成。另外，在正面3a形成有覆盖半导体芯片3的基材以及配线的绝缘膜3F，在绝缘膜3F形成有多个开口部3Fk。多个焊盘3PD各自的正面在形成于该绝缘膜3F的开口部3Fk中从绝缘膜3F露出。另外，多个焊盘3PD分别由金属构成，在本实施方式中，例如由铝(Al)构成。
另外，如图3以及图5所示，对多个焊盘3PD分别连接突起电极(导电性部件)3BP。半导体芯片3的多个焊盘3PD与配线基板2的多个焊接指状部2BF经由多个突起电极3BP而分别相互电连接。突起电极3BP是以在半导体芯片3的正面3a上突出的方式形成的金属部件。换言之，突起电极3BP是用于将形成于半导体芯片3的电路与配线基板的焊接指状部2BF电连接的导电性部件。
作为突起电极3BP，能够例示如下的结构。例如能够将在由铜(Cu)、镍(Ni)构成的导体柱的前端面形成有焊料膜的柱凸块(pillar bump)(柱状电极)用作突起电极3BP。另外，例如能够将利用球形焊接技术而将熔融的金属与焊盘3PD接合而得到的螺栓形凸块(stud bump)用作突起电极3BP。另外，例如，能够将以焊接材料自身用作突起电极3BP的焊料凸块用作突起电极3BP。在本实施方式中，作为代表例，举出突起电极3BP是柱凸块的情况来进行说明。
另外，如图3所示，在半导体芯片3与配线基板2之间配置树脂体4。树脂体4被配置成堵塞半导体芯片3的正面3a与配线基板2的上表面2a之间的空间。换言之，树脂体4紧贴于配线基板2的阻焊膜SR1以及半导体芯片3的正面3a双方。
另外，树脂体4由绝缘性(非导电性)的材料构成，被配置成对将半导体芯片3与配线基板2电连接的部分(多个突起电极3BP的接合部)进行密封。这样，通过以密封多个突起电极3BP的接合部的方式配置树脂体4，能够保护半导体芯片3与配线基板2的电连接部分。另外，通过使树脂体4紧贴于配线基板2以及半导体芯片3，能够使在突起电极3BP的连接部分产生的应力分散。树脂体4例如通过在环氧系的树脂中混合二氧化硅(SiO2)等填料粒子并进行热固化而形成。
<半导体芯片与配线基板之间的构造的详细情况>
接下来，说明图3所示的半导体芯片3与配线基板2之间的构造的详细情况。图6是将图3所示的半导体芯片与配线基板电连接的部分的放大剖视图。另外，图34是作为针对图6的比较例的半导体装置的放大剖视图。另外，图7是与图6所示的剖面对应的放大俯视图。此外，在图7中，为了容易判定图6所示的突起电极3BP与焊接指状部2BF的俯视时的位置关系，省略图6所示的半导体芯片3以及树脂体4的图示。另外，在图7中，附加双点划线来示出突起电极3BP以及焊接材料SD1。
如图6所示，作为配线基板2的端子的焊接指状部2BF形成于基材层2CR的上表面2CRa。另外，在基材层2CR的上表面2CRa上形成阻焊膜SR1，焊接指状部2BF的一部分(形成于开口部Sk1的外部的部分)被阻焊膜SR1覆盖。另外，焊接指状部2BF中的形成于阻焊膜SR1的开口部Sk1内的部分从阻焊膜SR1露出。
换言之，如图7所示，多个焊接指状部2BF分别具有连接突起电极3BP的部分即结合部BF1。结合部BF1形成于开口部Sk1内，从阻焊膜SR1露出。另外，多个焊接指状部2BF分别具有与结合部BF1连接的配线部BF2。配线部BF2从与结合部BF1的连接部分朝向阻焊膜SR1延伸。另外，配线部BF2的一部分形成于开口部Sk1的外侧，被阻焊膜SR1覆盖。
另外，在本实施方式中，配线部BF2与结合部BF1的一个侧面连结，在其相反侧的侧面未连接配线部BF2。即，结合部BF1的连结有配线部BF2的侧面的相反侧具有焊接指状部2BF的前端面(前端边)BFt。
另外，在图7所示的例子中，结合部BF1的平面形状是四边形，特别详细而言是长方形。与结合部BF1的宽度W1相当的短边方向的长度例如是10μm～40μm左右。另外，结合部BF1的长边方向的长度例如是50μm～70μm左右。另外，在图7所示的例子中，配线部BF2的宽度W2小于结合部BF1的宽度W1，例如是5μm～40μm左右。但是，作为针对图7的变形例，有时也将结合部BF1的宽度W1与配线部BF2的宽度W2设为相同值。进而，有时也将配线部BF2的宽度W2设为大于结合部BF1的宽度W1的值。
另外，作为半导体芯片3的电极的焊盘3PD形成于半导体芯片3的正面3a侧。详细而言，半导体芯片3具有在正面3a侧层叠的多个配线层，在多个配线层中的最上层(在图6所示的例子中是面朝下安装方式，因此在图6的情况下，是最下侧的配线层)形成焊盘3PD。半导体芯片3的正面3a被绝缘膜3F覆盖，焊盘3PD在形成于绝缘膜3F的开口部3Fk中，从绝缘膜3F露出。在图6所示的例子中，绝缘膜3F是层叠绝缘膜3F1与绝缘膜3F2而得到的层叠膜。绝缘膜3F1是例如氧化硅(SiO2)、氮化硅(SiN)等无机绝缘膜(钝化膜)。另外，绝缘膜3F2是例如聚酰亚胺树脂等树脂绝缘膜。此外，在绝缘膜3F中有各种变形例，例如有时也不形成绝缘膜3F2。
另外，半导体芯片3的焊盘3PD经由导电性部件而与配线基板2的焊接指状部2BF电连接。在图6所示的例子中，在上述导电性部件中包含突起电极3BP。本实施方式的突起电极3BP例如由铜(Cu)构成，是形成棱柱的柱状电极。详细来说，突起电极3BP如图5所示，被形成为在俯视时形成对角部进行了倒角加工而得到的四边形。此外，柱状电极的形状不限定于棱柱型，例如也能够形成为圆柱形。
图5以及图7所示的柱状的突起电极3BP的俯视时的一边的长度是25μm～35μm左右。另外，图6所示的突起电极3BP的高度(从与基底金属膜3UB的接合界面到前端面BPt的距离)是27μm～40μm左右。
柱状的突起电极3BP在焊盘3PD上隔着基底金属膜(凸块下金属)3UB而形成。基底金属膜3UB是用于提高例如由铝构成的焊盘3PD与由铜构成的突起电极3BP的连接性(例如电特性、连接强度)的金属膜，例如由镍(Ni)等金属材料构成。
另外，突起电极3BP与焊接指状部2BF经由作为导电性部件的焊接材料SD1而电连接。焊接材料SD1例如与使用图3说明的焊锡球SB同样地，能够使用无铅焊料。作为将突起电极3BP与焊接指状部2BF电连接的导电性部件而使用焊接材料SD1，这在以下方面是优选的。即，将焊接材料以及非连接部加热到比焊接材料SD1具有的焊料成分的融点更高的温度，此后如果进行冷却，则在与被连接对象物的接合界面形成合金层。在加热到比焊料成分的融点更高的温度之后进行冷却的处理被称为回流处理，在存在大量的端子的情况下，也能够一并处理大量的端子。另外，在针对大量的端子进行一并处理的情况下，也在焊接材料SD1与被连接对象物的连接界面形成合金层，因此容易确保所需的连接强度。
另外，将半导体芯片3与配线基板2电连接的部分的周边、即在图6所示的例子中焊盘3PD、基底金属膜3UB、突起电极3BP、焊接材料SD1、以及焊接指状部2BF的从阻焊膜SR1露出的露出部分的周边被树脂体4密封。
此处，为了使树脂体4作为密封体而发挥功能，需要抑制与半导体芯片3的密合界面以及与配线基板2的密合界面的剥离。但是，构成树脂体4的树脂材料(例如以环氧树脂为主体的树脂)与半导体芯片3(特别是构成半导体基板的硅)的热膨胀率的差异大。因此，如果对热膨胀率之差大的密合界面施加反复进行温度上升、温度降低的温度循环负荷，则在密合界面产生应力，成为产生剥离等的原因。详细而言，在热膨胀率中存在作为直线方向的膨胀率的指标的线膨胀系数和作为3维空间中的膨胀率的指标的体积膨胀系数，但作为由温度循环负荷引起的应力的产生原因，线膨胀系数的差异的影响较大。
因此，在树脂体4中，如上所述地混合例如二氧化硅等线膨胀系数的值与硅接近的填料粒子。例如，填料粒子的混合比例优选为50wt％(重量比例)以上，按50wt％～80wt％的程度混合填料粒子。半导体芯片3的线膨胀系数为约4ppm(parts per million)左右。与此相对地，在本实施方式中，通过在树脂体4中混合50wt％以上的填料粒子，树脂体4的线膨胀系数例如为25ppm～30ppm左右。这样，通过使树脂体4的线膨胀系数接近于半导体芯片3的线膨胀系数，能够抑制半导体芯片3与树脂体4的密合界面的剥离。
但是，根据本申请发明人的研究，在仅降低树脂体4的线膨胀系数的情况下，判明存在如下的课题。本申请发明人在针对完成的半导体封装(检査体)反复进行加热处理与冷却处理的温度循环试验中，发现下述的课题。但是，关于产生下述课题，认为不限于实施温度循环试验的情况，在安装半导体封装之后，也由于实际使用环境中的温度循环负荷而产生。以下，详细说明通过本申请发明人的研究而发现的课题。
在本实施方式中，如上所述，配线基板2的上表面2a的大部分被阻焊膜SR1覆盖。因此，如果阻焊膜SR1的线膨胀系数大，则由于温度循环负荷，有可能在树脂体4与阻焊膜SR1的密合界面发生剥离。
例如，在图34所示的半导体装置H1的情况下，在阻焊膜SRh中混合的填料粒子的比例为例如30wt％以下左右。另外，玻璃纤维未被混合。在这种情况下，阻焊膜SRh的线膨胀系数为500ppm～1000ppm左右(即，0.05％～0.1％左右)，相对于树脂体4的线膨胀系数，成为10倍以上的值。
另外，如图34所示，当在阻焊膜SRh中形成开口部Sk1的情况下，由于温度循环负荷而应力集中于开口部Sk1的端部，如图34示意地示出的那样，有时在树脂体4中产生裂纹CLK1。根据本申请发明人的研究，以阻焊膜SR1的开口部Sk1的开口端部(边沿部)为起点而产生裂纹CLK1的情况较多。
另外，如果产生该裂纹CLK1，则该裂纹CLK1在其产生部位的附近发展，例如在图34所示的例子中，存在作为发展终点的导体图案的焊接指状部2BF的一部分或者在半导体芯片3的正面3a侧层叠的配线层的一部分受到损伤的情况。
另外，在不产生裂纹CLK1的情况下，也判明产生如下的课题。即，在阻焊膜SRh的线膨胀系数大的情况下，通过阻焊膜SRh将焊接指状部2BF向阻焊膜SRh的方向拉伸。在图34中，对将焊接指状部2BF向阻焊膜SR1拉伸的方向附加箭头ST1而示意地示出。如果在图34所示的箭头ST1的方向上产生拉伸力，则在焊接材料SD1与焊接指状部2BF的接合部处，力作用于使接合界面剥离的方向。并且，判明如果这样的力反复进行作用，则在将半导体芯片3与配线基板2电连接的部分中的一部分的连接界面处发生剥离。详细而言，判明在焊接材料SD1与焊接指状部2BF的连接界面、焊接材料SD1与突起电极3BP的连接界面、突起电极3BP与基底金属膜3UB的连接界面、或者基底金属膜3UB与焊盘3PD、绝缘膜3F的连接界面中的某一处或者多处发生连接界面的剥离。
另外，为了提高半导体封装整体针对温度循环负荷的耐久性，判明不仅减小阻焊膜SRh的线膨胀系数，还需要考虑被层叠的各部件的线膨胀系数的平衡。例如，在阻焊膜SRh的线膨胀系数小于基材层2CR的线膨胀系数的情况下，在阻焊膜SRh与基材层2CR的连接界面，有时发生由温度循环负荷引起的剥离。另外，如果为了减小阻焊膜SRh的线膨胀系数而过量地混合玻璃纤维(纤维材料)GC(参照图6)，则阻焊膜SRh的加工性降低。因此，例如难以高精度地形成开口部Sk1。
因此，本申请发明人进一步地进行研究，发现了本实施方式的结构。即，在本实施方式中，在阻焊膜SR1包含有多个填料粒子。另外，在阻焊膜SR1中，如图6示意地示出的那样，包含了玻璃纤维GC。通过在阻焊膜SR1中混合玻璃纤维GC，能够减小阻焊膜SR1的线膨胀系数。
在本实施方式中，通过在阻焊膜SR1中混合多个填料粒子以及玻璃纤维，调整阻焊膜SR1的线膨胀系数的值。即，理想地说，优选按树脂体4、阻焊膜SR1、基材层2CR的顺序，线膨胀系数的值依次变小。进而，更优选按树脂体4、阻焊膜SR1、焊接指状部2BF、基材层2CR的顺序，线膨胀系数的值依次变小。
另外，阻焊膜SR1的线膨胀系数与树脂体4的线膨胀系数也可以相同。但是，在这种情况下，阻焊膜SR1的线膨胀系数需要大于基材层2CR的线膨胀系数。
另外，阻焊膜SR1的线膨胀系数与基材层2CR的线膨胀系数也可以相同。但是，在这种情况下，阻焊膜SR1的线膨胀系数需要小于树脂体4的线膨胀系数。
如果总结上述的线膨胀系数的关系，则如下所述。即，阻焊膜SR1的线膨胀系数为基材层2CR的线膨胀系数以上，并且阻焊膜SR1的线膨胀系数为树脂体4的线膨胀系数以下，并且基材层2CR的线膨胀系数小于树脂体4的线膨胀系数。
换言之，如果将基材层2CR的线膨胀系数设为α1、将阻焊膜SR1的线膨胀系数设为α2、将树脂体4的线膨胀系数设为α3，则满足下述(式1)或者下述(式2)的关系：
α1≤α2＜α3···(式1)
α1＜α2≤α3···(式2)。
在图6所示的例子中，半导体芯片3(详细而言，半导体芯片3具备的半导体基板)的线膨胀系数约为4ppm左右。另外，紧贴于半导体芯片3以及阻焊膜SR1的树脂体4的线膨胀系数为25ppm～30ppm。另外，阻焊膜SR1的线膨胀系数在15ppm～30ppm的范围内并且在树脂体4的线膨胀系数的值以下。另外，基材层2CR的线膨胀系数为10～15ppm并且在阻焊膜SR1的线膨胀系数的值以下。
通过上述结构，在对层叠了线膨胀系数不同的多个部件的半导体装置SP1施加温度循环负荷的情况下，也能够抑制各绝缘层的连接界面的剥离。因此，能够提高半导体装置的可靠性。
另外，焊接指状部2BF的线膨胀系数在15ppm～17ppm的范围内并且在阻焊膜SR1的线膨胀系数的值以下。如果焊接指状部2BF的线膨胀系数与阻焊膜SR1的线膨胀系数满足上述的关系，则能够抑制紧贴于焊接指状部2BF的绝缘层的密合界面的剥离，因此是更加优选的。
在本实施方式中，在阻焊膜SR1中混合玻璃纤维GC是为了使阻焊膜SR1的线膨胀系数高效地降低。如果通过使填料粒子混入到阻焊膜SR1就能够满足上述(式1)或者上述(式2)的关系，则也考虑不混合纤维材料的变形例。但是，不混合玻璃纤维GC而满足上述(式1)或者上述(式2)的关系是困难的。另一方面，如果在阻焊膜SR1中包括玻璃纤维GC，则能够较容易地满足上述(式1)或者上述(式2)的关系。
此外，通过采用满足上述(式1)或者上述(式2)的关系的阻焊膜SR1，也能够抑制在使用图34说明的课题中的、在将半导体芯片3与配线基板2电连接的部分中的一部分的连接界面产生的剥离，但作为更可靠地解决该课题的手段，在本实施方式的半导体装置SP1中还具备以下的结构。
即，如图6所示，在本实施方式中，突起电极3BP连接到在厚度方向上与焊接指状部2BF的延伸方向的前端重叠的位置。详细而言，如图7所示，多个焊接指状部2BF分别具有作为经由焊接材料SD1而连接突起电极3BP的部分的结合部BF1。结合部BF1配置于阻焊膜SR1的开口部Sk1内，具有位于俯视时的焊接指状部2BF的延伸方向(在图7所示的例子中为X方向)的前端的前端面(前端边)BFt。此外，如图6所示，前端面BFt是位于焊接指状部2BF的延伸方向(在图6中为X方向)的前端的侧面，但在图7所示的俯视图时，能够作为边来考虑。因此，在本实施方式的说明中，有时一并记为前端面(前端边)BFt而示出。
另外，多个焊接指状部2BF分别从结合部BF1朝向与前端面(前端边)BFt相反的方向延伸，一部分具有被阻焊膜SR1覆盖的配线部BF2。并且，在俯视时，多个突起电极3BP与多个焊接指状部2BF具有的结合部BF1的前端面(前端边)BFt分别重叠。
如本实施方式那样，突起电极3BP与焊接指状部2BF的前端面(前端边)BFt配置成在厚度方向上重叠，换言之，以突起电极3BP的一部分从焊接指状部2BF的前端面(前端边)BFt向前突出的方式配置(搭载)半导体芯片3，从而配置于突起电极3BP的正下方的焊接材料SD1的量增加。详细而言，能够增大焊接材料SD1中的、覆盖焊接指状部2BF的前端面BFt的部分的厚度(焊接指状部2BF的延伸方向(在图6中为X方向)的厚度)。焊接材料SD1是弹性比构成焊接指状部2BF、突起电极3BP的主要金属材料(例如铜)更低的材料。如在图6中附加箭头ST2而示意地示出的那样，在由于温度循环负荷而产生将焊接指状部2BF向阻焊膜SR1的方向拉伸的拉伸力时，即使在本实施方式的情况下，在突起电极3BP的连接部分的周边也产生应力。
但是，在本实施方式的情况下，配置于突起电极3BP的下方的焊接材料SD1中的、图6所示的覆盖前端面BFt的部分的量增加。并且，由于包括了覆盖前端面BFt的部分的焊接材料SD1发生弹性变形，能够缓和应力。换言之，使容易因温度循环负荷而发生应力集中的前端面(前端边)BFt的附近的焊接材料SD1的配置量增加，从而利用焊接材料SD1的弹性变形功能，能够抑制应力集中。
另外，在本实施方式的情况下，如上所述，阻焊膜SR1的线膨胀系数在基材层2CR的线膨胀系数以上，并且阻焊膜SR1的线膨胀系数在树脂体4的线膨胀系数以下，并且基材层2CR的线膨胀系数小于树脂体4的线膨胀系数。因此，在对半导体装置SP1施加温度循环负荷的情况下产生的拉伸力(图6的箭头ST2所示的力)小于在对图34所示的半导体装置H1施加温度循环负荷的情况下产生的拉伸力(图34的箭头ST1所示的力)。因此，半导体装置SP1与半导体装置H1相比，能够抑制在将半导体芯片3与配线基板2电连接的部分中的一部分的连接界面发生剥离的现象。
另外，如图7所示，在本实施方式中，结合部BF1的宽度(与焊接指状部2BF的延伸方向正交的方向的长度)W1大于配线部BF2的宽度(与焊接指状部2BF的延伸方向正交的方向的长度)W2。通过这样使结合部BF1的宽度W1大于配线部BF2的宽度W2，能够增大结合部BF1与焊接材料SD1的接合面积。因此，焊接材料SD1与焊接指状部2BF的接合强度提高。但是，虽然省略图示，但作为针对本实施方式的变形例，也能够使结合部BF1的宽度W1与配线部BF2的宽度W2相同。进而，也能够将配线部BF2的宽度W2设为比结合部BF1的宽度W1更大的值。
另外，在图4所示的例子中，焊接指状部2BF的配线部BF2从形成于开口部Sk1内的结合部BF1朝向配线基板2的周缘部(换言之，朝向侧面2s)延伸。但是，作为变形例，也能够从形成于开口部Sk1内的结合部BF1朝向配线基板2的上表面2a的中心地使配线部BF2向内侧延伸。另外，作为针对本实施方式的另一个变形例，也能够在一个开口部Sk1中，以多列来排列多个结合部BF1。关于该变形例，在后面叙述。
另外，在本实施方式中，关于芯片搭载面侧的阻焊膜SR1，说明包括玻璃纤维GC的实施方式。另一方面，图3所示的安装面侧的阻焊膜SR2与将半导体芯片3与配线基板2电连接的部分没有直接的关系，因此也能够不包括玻璃纤维GC(参照图6)地形成。但是，从抑制配线基板2的翘曲变形的观点出发，优选使阻焊膜SR1与阻焊膜SR2的线膨胀系数一致。因此，优选在阻焊膜SR2中与阻焊膜SR1同样地包括玻璃纤维GC。另外，阻焊膜SR2的线膨胀系数优选在基材层2CR的线膨胀系数以上，与阻焊膜SR1的线膨胀系数程度相同。在本实施方式中，图3所示的阻焊膜SR2的线膨胀系数在10ppm～30ppm的范围内，并且为基材层2CR的线膨胀系数以上的值。
<半导体装置的制造方法>
接下来，说明使用图1～图7说明的半导体装置PK1的制造工序。半导体装置SP1按照图8所示的流程来制造。图8是示出使用图1～图7说明的半导体装置的制造工序的概要的说明图。
<基板准备工序>
首先，在图8所示的基板准备工序中，准备图9以及图10所示的配线基板20。图9是示出在图8所示的基板准备工序中准备的配线基板的整体构造的俯视图，图10是沿着图9的A-A线的放大剖视图。此外，在图10中，为了示出形成于焊接指状部2BF的露出面的焊接材料SD2，也示出了焊接指状部2BF的周边的放大图。另外，在图10中，为了明示安装面侧的阻焊膜SR2包括玻璃纤维GC，因此也示出了阻焊膜SR2与基材层2CR的粘接界面的一部分的放大图。
如图9所示，在本工序中准备的配线基板20在框部(框体)20b的内侧具备多个产品形成区域20a。详细而言，多个(在图9中为27个)产品形成区域20a配置成矩阵状。配线基板20是相当于图3所示的配线基板2的具有多个产品形成区域20a以及在各产品形成区域20a之间的切割线(dicing line)(切割区域)20c的所谓多片基板。这样，通过使用具备多个产品形成区域20a的多片基板，能够提高制造效率。
此外，在本实施方式中，说明使用多片基板的半导体装置的制造方法，但作为变形例，也能够对以单片形成的配线基板2(参照图3)搭载半导体芯片3。在这种情况下，能够省略图8所示的单片化工序。
如图10所示，在各产品形成区域20a中，分别形成有使用图1～图7说明的配线基板2的结构部件。详细而言，配线基板20具备具有上表面2CRa以及上表面2CRa的相反侧的下表面2CRb的基材层2CR。基材层2CR通过在使混合了填料粒子的树脂浸渍到玻璃纤维GC之后进行加热而使热固化性树脂成分固化而得到。
另外，配线基板20的各产品形成区域20a具备形成于基材层2CR的上表面2CRa上的多个焊接指状部2BF、配置于下表面2CRb的多个焊接区2LD以及将多个焊接指状部2BF与焊接区2LD电连接的多个通孔配线2TW。
另外，在基材层2CR的上表面2CRa，形成使用图6说明的包含玻璃纤维GC、多个填料粒子以及树脂的绝缘层即阻焊膜(绝缘层)SR1。基材层2CR的上表面2CRa的大部分被阻焊膜SR1覆盖。阻焊膜SR1通过在使混合了填料粒子的树脂浸渍到玻璃纤维GC之后进行固化而得到。在浸渍于玻璃纤维GC的树脂包括例如环氧等热固化性树脂成分的情况下，在形成阻焊膜SR1之后进行加热，从而能够进行固化。
另外，如图4所示，在阻焊膜SR1形成开口部Sk1，在开口部Sk1中，多个焊接指状部2BF各自的一部分从阻焊膜SR1露出。在图4所示的例子中，开口部Sk1跨过多个焊接指状部2BF地形成。换言之，多个焊接指状部2BF各自的一部分在一个开口部Sk1中一并从阻焊膜SR1露出。开口部Sk1的形成方法例如能够通过使用了光刻技术的蚀刻处理来形成。但是，在本实施方式中，在阻焊膜SR1中包含了玻璃纤维GC(参照图10)。因此，从去除玻璃纤维GC的一部分而高精度地形成开口部Sk1的观点出发，优选通过照射激光来形成开口部Sk1。
另外，在基材层2CR的下表面2CRb，形成作为包含树脂的绝缘层的阻焊膜(绝缘层)SR2，下表面2CRb的大部分被阻焊膜SR2覆盖。另外，如图3所示，在阻焊膜SR2中形成多个开口部Sk2，在开口部Sk2中，多个焊接区2LD各自的一部分从阻焊膜SR2露出。在图3所示的例子中，开口部Sk2与多个焊接区2LD分别对应地形成。换言之，在多个焊接指状部2BF处，分别单独地形成开口部Sk2，在多个开口部Sk2中，多个焊接指状部2BF分别从阻焊膜SR2露出。
如上所述，在本实施方式中，在阻焊膜SR2中也包含了玻璃纤维GC。阻焊膜SR2能够与阻焊膜SR1同样地形成。另外，开口部Sk2与开口部Sk1同样地，也能够通过蚀刻处理来形成，但从高精度地形成开口部Sk2的观点出发，优选通过照射激光来去除阻焊膜SR2的一部分的方法。
另外，配线基板20具备的导体图案(焊接指状部2BF、焊接区2LD以及通孔配线2TW)分别由以铜(Cu)为主分量的金属材料形成。在本实施方式中，作为形成这些导体图案的方法，例如使用减成法、半加成法等方法来形成。根据这样的方法，如图7例示出的那样，能够形成结合部BF1以及配线部BF2。此外，各导体图案的形成顺序是首先形成通孔配线2TW，之后形成与通孔配线2TW连接的焊接指状部2BF以及焊接区2LD。焊接指状部2BF与焊接区2LD的形成顺序的先后没有限定。
另外，在形成上述导体图案之后形成阻焊膜SR1以及阻焊膜SR2。此后，形成开口部Sk1，使多个焊接指状部2BF在开口部Sk1内露出。另外，形成多个开口部Sk2，使多个焊接区2LD分别在开口部Sk2中露出。
另外，在多个焊接指状部2BF的从阻焊膜SR1露出的露出部分，预先涂敷有多个焊接材料SD2。该焊接材料SD2是图6所示的焊接材料SD1的原料。在图8所示的半导体芯片搭载工序之前，在焊接指状部2BF的结合部BF1的露出面预先形成焊接材料SD2，从而在半导体芯片搭载工序中，能够提高形成于突起电极3BP(参照图6)侧的焊接材料(详细情况在后面叙述)的湿润性。焊接材料SD2能够通过各种形成方法来形成，例如能够通过镀敷法形成。另外，形成焊接材料SD2的时机优选为在阻焊膜SR1中形成开口部Sk1之后。在这种情况下，在被阻焊膜SR1覆盖的部分不形成焊接材料SD2。
<半导体芯片准备工序>
在图8所示的半导体芯片准备工序中，准备图5所示的半导体芯片3。图11是示出在图8所示的晶圆准备工序中准备的半导体晶圆的俯视图，图12是示出形成于图11所示的半导体晶圆的一个芯片区域的焊盘的周边的放大剖视图。另外，图13是示出在图12所示的多个焊盘上形成有基底金属膜以及突起电极的状态的放大剖视图，图14是示出在图13所示的突起电极的前端面上安装有焊接材料的状态的放大剖视图。另外，图15是示出去除了图14所示的掩模的状态的放大剖视图，图16是示出对图15所示的焊接材料进行加热而使其变形为圆顶形状的状态的放大剖视图。
图5所示的半导体芯片3例如以如下方式制造。首先，在图8所示的晶圆准备工序中，准备图11所示的晶圆(半导体晶圆)WH。如图11所示，在本工序中准备的晶圆WH具备具有大致圆形的平面形状的正面3a以及位于正面3a的相反侧的背面3b。另外，晶圆WH具有多个芯片区域(设备区域)WHa，各芯片区域WHa分别相当于图5所示的半导体芯片3。另外，在相邻的芯片区域WHa之间，形成划片槽(scribe line)(划片区域)WHb。划片槽WHb形成为格子状，将晶圆WH的正面3a划分成多个芯片区域WHa。另外，在划片槽WHb上，形成多个用于确认是否正确地形成了在芯片区域WHa内形成的半导体元件等的TEG(Test Element Group，测试元件组)、对准标记等导体图案。
在本工序中准备的晶圆WH处，在例如由硅(Si)构成的半导体基板的主面(元件形成面)形成了例如晶体管等多个半导体元件(省略图示)。另外，在半导体基板的半导体元件形成面上层叠多个配线层(省略图示)，在最上层形成有与上述多个配线层电连接的多个焊盘3PD。多个焊盘3PD经由形成于配线层的多个配线而分别与多个半导体元件电连接。即，在本工序中准备的晶圆WH处，预先在半导体基板的半导体元件形成面上形成集成电路。另外，半导体芯片3的正面3a例如被氧化硅(SiO2)、聚酰亚胺树脂等绝缘膜3F覆盖，但在多个焊盘3PD上，以覆盖正面3a的方式形成开口部3Fk。然后，在开口部3Fk中，焊盘3PD从绝缘膜3F露出。
接下来，在图8所示的突起电极形成工序中，如图13所示，在多个焊盘3PD上分别堆积金属膜而形成突起电极3BP。在本实施方式中，如图13所示，在晶圆WH的正面3a上配置(固定)掩模MS。然后，在形成突起电极3BP的位置形成贯通孔(开口部)MSh。贯通孔MSh例如能够采用光刻技术、蚀刻技术来形成。
接下来，在贯通孔MSh内堆积金属膜而形成突起电极3BP。在本实施方式中，在堆积例如镍膜等基底金属膜3UB之后，堆积铜膜，形成突起电极3BP。堆积金属膜的方法没有特别限定，例如能够通过镀敷法来堆积。这样，在通过堆积金属膜来形成基底金属膜3UB与突起电极3BP的情况下，在接合突起电极3BP与焊盘3PD时，能够降低对焊盘3PD施加的压力。
特别是，如果与球形焊接方式等使突起电极压接于焊盘(包含热压接)的方式相比，则通过镀敷法来形成的本实施方式的方法更能够降低压力。因此，能够抑制由突起电极形成时的芯片区域WHa的破损引起的可靠性降低。另外，通过当在掩模MS中形成了多个贯通孔MSh的状态下堆积金属膜，能够一并形成多个(大量)突起电极3BP。因此，能够高效地形成突起电极3BP。另外，在切割晶圆WH之前形成突起电极3BP，因此能够在多个芯片区域WHa一并形成突起电极3BP。因此，能够高效地形成突起电极3BP。这样在掩模MS的贯通孔MSh内堆积金属膜而形成的突起电极成为具备柱型的立体形状的柱状电极。另外，突起电极3BP的平面形状根据贯通孔MSh的开口形状而形成。例如，在本实施方式中，形成为对四个角部进行倒角而成为曲线的四边形(四边形)的开口形状。但是，在柱状电极的形状中，存在各种变形例，例如能够设为圆柱形。
接下来，在图8所示的焊接材料形成工序中，如图14所示，在突起电极3BP的前端面BPt上分别堆积焊料膜而形成(安装)焊接材料SD3。在本实施方式中，在上述突起电极形成工序中将金属膜堆积到贯通孔MSh(参照图13)的中途，此后继续(不去除掩模MS)堆积焊料膜。因此，例如在堆积铜膜之后，如果继续堆积焊料膜，则能够抑制在形成焊料膜之前在铜膜处形成氧化膜。因此，能够提高焊接材料SD3与突起电极3BP的接合界面的接合强度。另外，在本工序中通过用焊接材料SD3覆盖突起电极3BP的前端面BPt，能够防止前端面BPt曝露于大气，因此能够维持在前端面BPt难以形成氧化膜的状态。因此，能够提高焊接材料SD3与突起电极3BP的接合界面的接合强度。其结果是，能够提高焊接材料SD3与前端面BPt的接合界面的接合强度。此外，为了更可靠地抑制突起电极3BP的氧化，也可以在突起电极3BP的前端面BPt形成镍(Ni)膜。但是，在形成镍膜的情况下，用于形成镀镍膜的镀敷的工序数(工序时间)增加，因此优选如本实施方式那样，在突起电极3BP的前端面BPt直接形成焊接材料SD3。
接下来，如果去除掩模MS(参照图14)并进行清洗，则如图15所示，突起电极3BP的侧面露出。在该状态下，焊接材料SD3与突起电极3BP同样地是四棱柱的形状，但如果实施热处理(加热处理)，使焊接材料SD3的至少一部分熔融，则如图16所示，焊接材料SD3的形状由于熔融焊料的表面张力的影响而变形，成为圆顶形状。如果这样实施热处理，则能够使突起电极3BP的前端面BPt与焊接材料SD3牢固地接合。另外，如图16所示，在设为圆顶形状的情况下，焊接材料SD3更稳定，因此能够抑制从突起电极的脱落、损伤。
通过以上的各工序，得到在多个焊盘3PD的正面(上表面)形成(接合)多个突起电极3BP、并且在多个突起电极3BP的前端面BPt形成有多个焊接材料SD3的晶圆WH。
接下来，在形成了多个突起电极3BP的晶圆WH的正面粘贴背面研磨用的胶带，对晶圆WH的背面进行研磨(研削)，从而取得所期望的厚度的晶圆WH。此外，在准备的晶圆WH的厚度在晶圆的准备阶段已经较薄的情况下，或者在不需要削薄的情况下，能够删除该研削工序。
接下来，在图8所示的切割工序中，将图16所示的晶圆WH按芯片区域WHa进行切割(单片化)，取得多个如图5所示的半导体芯片3。在本工序中，沿着图12所示的划片槽WHb切断并切割晶圆WH。切断方法没有特别限定，能够采用使用划片刀(旋转刀)的切断方法、照射激光的切断方法。
<半导体芯片搭载工序>
在图8所示的半导体芯片搭载工序中，如图17所示，在配线基板20上搭载半导体芯片3。在本实施方式中，以半导体芯片3的正面3a与配线基板20的上表面2a对置的方式配置在配线基板20上，将多个焊接指状部2BF与多个焊盘3PD电连接。图17是示出在图12所示的配线基板上搭载有半导体芯片的状态的放大剖视图。另外，图18是示出在配线基板上配置有半导体芯片时的突起电极与端子的平面位置关系的放大俯视图。另外，图19是沿着图18的A-A线的放大剖视图。另外，图20是示出图19所示的焊接材料一体化后的状态的放大剖视图。
在本工序中，首先如图17所示，以半导体芯片3的正面3a与配线基板20的上表面2a对置的方式配置在配线基板20上(半导体芯片配置工序)。此时，如图18所示，以多个突起电极3BP与多个焊接指状部2BF的前端面(前端边)BFt分别重叠的方式调整半导体芯片3与配线基板20的平面位置关系。换言之，如图19所示，以安装于突起电极3BP的前端面BPt的焊接材料SD3在厚度方向上与焊接指状部2BF的前端面(前端边)BFt重叠的方式使半导体芯片3对位地配置在配线基板20上。
如上所述，在本实施方式中，通过增加配置于突起电极3BP的下方的焊接材料SD1中的、覆盖焊接指状部2BF的前端面BFt的部分的量，缓和由于温度循环负荷而在突起电极3BP的周边产生的应力。在本工序中，如果能够以多个突起电极3BP与多个焊接指状部2BF的前端面(前端边)BFt在厚度方向上重叠的方式进行对位，则能够增加配置于突起电极3BP的下方的焊接材料SD1中的、覆盖焊接指状部2BF的前端面BFt的部分的量。
换言之，能够增大焊接材料SD1中的、覆盖焊接指状部2BF的前端面BFt的部分的厚度(焊接指状部2BF的延伸方向(在图18以及图19中，X方向)的厚度)。进一步地，换言之，能够增加配置于突起电极3BP的正下方的焊接材料SD1的量。
接下来，使图19所示的半导体芯片3与配线基板2的距离接近，并使焊接材料SD2与焊接材料SD3接触(抵接)。此时，焊接材料SD3以在厚度方向上与焊接材料SD2中的、覆盖焊接指状部2BF的前端面BFt的部分重叠的方式进行接触。另外，在多个焊接指状部2BF分别中，为了使焊接材料SD2与焊接材料SD3接触，优选进行预先加热直到焊接材料SD2或者焊接材料SD3中的至少一方变成在接触后变形的程度的硬度为止。
接下来，进一步进行加热直到焊接材料SD2以及焊接材料SD3达到融点以上为止(加热工序(热处理工序、回流工序)。加热温度根据焊接材料SD2以及焊接材料SD3的融点而变化，但在采用锡-银(Sn-Ag)系的无铅焊料的情况下，在230℃～300℃下进行加热。在本工序中，在使焊接材料SD2与焊接材料SD3接触的状态下进行加热，因此例如如果对半导体芯片3进行加热，则能够通过来自焊接材料SD3的热传递，对焊接材料SD2进行加热。并且，如果焊接材料SD2以及焊接材料SD3分别熔融，则焊接材料SD2与焊接材料SD3一体化。即，焊接材料SD2以及焊接材料SD3成为所谓“湿润的”状态。然后，在一体化之后，通过冷却熔融焊料，形成图20所示的焊接材料SD1。
另外，如果图19所示的焊接材料SD2与焊接材料SD3一体化，则通过一体化后的熔融焊料的表面张力，变形成物理上稳定的形状。即，成为与球形类似的形状。即，在本工序中，在俯视时多个突起电极3BP与多个焊接指状部2BF的前端面(前端边)BFt分别重叠的状态下固定半导体芯片3。
如本实施方式那样，在突起电极3BP的一部分存在于在厚度方向上与焊接指状部2BF不重叠的位置的情况下，在该部分的正下方(突起电极3BP与基材层2CR的上表面2CRa之间的空间)，如图19所示，焊接材料SD1形成得较厚。即，能够增加突起电极3BP的正下方的、与焊接指状部2BF不重叠的部分的焊接材料SD1的量。其结果是，能够缓和由于温度循环负荷而在突起电极3BP的周边产生的应力。
<密封工序>
接下来，在图8所示的密封工序中，如图21所示，向半导体芯片3的正面3a与配线基板20的上表面2a之间供给树脂体4，对将焊盘3PD与焊接指状部2BF电连接的部分进行密封。图21是示出向图17所示的半导体芯片与配线基板之间供给了底部填充树脂的状态的放大剖视图。
在本工序中，例如在半导体芯片3的侧面3s的外侧配置供给树脂用的喷嘴NZ1，将液状或者膏状的树脂4p供给到半导体芯片3的正面3a与配线基板20的上表面2a之间。在树脂4p中，含有热固化性树脂成分以及多个填料粒子。
向半导体芯片3的正面3a与配线基板20的上表面2a之间供给的树脂4p通过毛细现象，向半导体芯片3的正面3a与配线基板20的上表面2a的空间扩展。然后，如果对树脂4p进行加热而使树脂4p中包含的热固化性树脂成分固化，则图20所示的焊盘3PD、基底金属膜3UB、突起电极3BP、焊接材料SD1以及焊接指状部2BF的各接合部通过树脂体4而一并被密封。
这样，通过树脂体4对焊盘3PD与焊接指状部2BF的连接部进行密封，能够使对连接部施加的应力分散到树脂体4，因此从提高焊盘3PD与焊接指状部2BF的连接可靠性的观点出发是优选的。
另外，从提高树脂体4与半导体芯片3的粘接强度的观点出发，优选在半导体芯片3的周围也形成树脂体4，树脂体4的一部分形成覆盖半导体芯片3的侧面3s的至少一部分的凸缘。如果在树脂体4的周缘部形成凸缘，则树脂体4分别粘接于半导体芯片3的正面3a以及多个侧面3s，因此粘接强度提高。
另外，如上所述，当在半导体芯片3的周围也形成树脂体4的情况下，阻焊膜SR1的开口部Sk1被树脂体4堵塞。因此，例如如图6所示，成为开口部Sk1的开口端部被树脂体4密封的构造。
另外，在本实施方式中，由于在树脂体4中含有多个填料粒子，从而树脂体4的线膨胀系数例如为25ppm～30ppm左右，降低与半导体芯片3的线膨胀系数(例如4ppm)之差。因此，能够抑制在树脂体4与半导体芯片3的密合界面发生由温度循环负荷引起的剥离。
另外，如上所述，固化后的树脂体4的线膨胀系数在紧贴于树脂体4的阻焊膜SR1的线膨胀系数以上，并且大于基材层2CR的线膨胀系数。因此，通过在树脂体4中混合填料粒子，在降低树脂体4的线膨胀系数的情况下，也能够抑制在阻焊膜SR1与树脂体4的密合界面发生由温度循环负荷引起的剥离。
此外，在本实施方式中说明的技术不限于应用于在半导体芯片搭载工序之后形成树脂体4的制造方法，能够应用各种变形例。例如，作为针对本实施方式的变形例，存在在半导体芯片搭载工序之前在搭载半导体芯片的预定区域(芯片搭载区域)预先形成膏状或者膜状的树脂的方法。在这种情况下，在半导体芯片搭载工序中，贯通预先形成的树脂地将突起电极3BP与焊接指状部2BF电连接，此后，使树脂固化而形成树脂体4。即，在密封工序中，不供给树脂而进行加热固化处理。
<球装配工序>
接下来，在图8所示的球装配工序中，如图22所示，对形成于配线基板20的下表面2b的多个焊接区2LD接合多个焊锡球SB。图22是示出在图21所示的配线基板的多个焊接区上接合了焊锡球的状态的放大剖视图。在本工序中，如图22所示，在配线基板20的下表面2b露出的多个焊接区2LD中的各接合区上配置焊锡球SB之后，通过进行加热来使多个焊锡球SB与焊接区2LD接合。通过本工序，多个焊锡球SB经由配线基板20而与半导体芯片3电连接。但是，在本实施方式中说明的技术不限于应用于接合了焊锡球SB的所谓BGA(Ball GridArray，球栅阵列)型的半导体装置。例如，作为针对本实施方式的变形例，能够应用于不形成焊锡球SB而以使焊接区2LD露出的状态、或者在焊接区2LD比焊锡球SB更薄地涂敷了焊料膏的状态发货的所谓LGA(Land Grid Array，栅格阵列)型的半导体装置。
<单片化工序>
接下来，在图8所示的单片化工序中，将配线基板20按产品形成区域20a(参照图9)进行切割。图23是示出在图8所示的单片化工序中对多片的配线基板实施单片化的情况的剖视图。
在本工序中，沿着图9所示的切割线(切割区域)20c将配线基板20切断，按产品形成区域20a切割成单片，取得多个图1所示的半导体装置。在图23所示的例子中，在固定到固定配线基板20的夹具DCd的状态下，通过使用划片刀(旋转刀)DCb切削配线基板20的切割线20c来进行切断。
通过以上各工序，得到使用图1～图7说明的半导体装置SP1。此后，进行外观检査、电气试验等必要的检査、试验，并发货或者安装到未图示的安装基板。
以上，根据实施方式具体说明了通过本申请发明人进行的发明，但本发明不限定于上述实施方式，除上述例示地示出的变形例之外，在不脱离其主旨的范围内，还能够进行各种变更，这自不待言。以下，例示地说明针对上述实施方式的变形例。
<变形例1>
首先，在上述实施方式中，作为抑制由于温度循环负荷而产生的应力的影响所导致的半导体装置的可靠性降低的方法，说明使阻焊膜SR1中含有玻璃纤维GC并调整阻焊膜SR1的线膨胀系数的技术(以下记载为线膨胀系数调整技术)。
另外，在上述实施方式中，说明了由于在图6中附加箭头ST2而示出的拉伸力而在将图6所示的焊盘3PD与焊接指状部2BF电连接的导电性部件的接合界面发生剥离、损伤的现象及其解决办法。即，说明了在焊接指状部2BF的前端面(前端边)BFt在厚度方向上与突起电极3BP重叠的状态下，将突起电极3BP与焊接指状部2BF经由焊接材料SD1而电连接的技术(以下，记载为突起电极布局技术)。
在上述实施方式中，说明了将线膨胀系数调整技术与突起电极布局技术组合地应用的实施方式，但作为变形例，也能够单独地分别应用线膨胀系数调整技术与突起电极布局技术。
例如，图24所示的半导体装置SP2在突起电极3BP在厚度方向上与焊接指状部2BF的前端面(前端边)BFt不重叠这一点上，与图6所示的半导体装置SP1不同。即，半导体装置SP2是独立地应用上述线膨胀系数调整技术而未应用上述突起电极布局技术的实施方式。
在半导体装置SP2的情况下，在阻焊膜SR1中包含玻璃纤维GC。另外，阻焊膜SR1的线膨胀系数在基材层2CR的线膨胀系数以上，并且阻焊膜SR1的线膨胀系数在树脂体4的线膨胀系数以下，并且基材层2CR的线膨胀系数小于树脂体4的线膨胀系数。
因此，在由于温度循环负荷而产生在图24中附加箭头ST2而示出的拉伸力的情况下，图24所示的拉伸力的大小也小于在图34中附加箭头ST1而示出的拉伸力。因此，半导体装置SP2与半导体装置H1相比，能够抑制在将半导体芯片3与配线基板2电连接的部分中的一部分的连接界面发生剥离的现象。
另外，图25所示的半导体装置SP3在形成于芯片搭载面侧的阻焊膜SR3中未包含图6所示的玻璃纤维GC等纤维材料这一点上，与图6所示的半导体装置SP1不同。即，半导体装置SP3是独立地应用上述突起电极布局技术而未应用上述线膨胀系数调整技术的实施方式。
在半导体装置SP3的情况下，在阻焊膜SR1中不包含纤维材料，因此阻焊膜SR3的线膨胀系数大于图6所示的阻焊膜SR1的线膨胀系数。例如阻焊膜SR3的线膨胀系数为500ppm～1000ppm。因此，阻焊膜SR3的线膨胀系数是分别大于树脂体4的线膨胀系数以及基材层2CR的线膨胀系数的值。
因此，在对半导体装置SP3施加了温度循环负荷时产生的拉伸力如在图25中附加箭头ST2而示出的那样变大。但是，在半导体装置SP3中，突起电极3BP在厚度方向上与焊接指状部2BF的前端面(前端边)BFt重叠。因此，配置于突起电极3BP的下方的焊接材料SD1中的覆盖前端面BFt的部分的量与图34所示的半导体装置H1相比能够增加。因此，通过包括了覆盖前端面BFt的部分的焊接材料SD1发生弹性变形，能够缓和应力。
即，图25所示的半导体装置SP3与图34所示的半导体装置H1相比，在施加了温度循环负荷时，能够抑制在将焊盘3PD与焊接指状部2BF电连接的导电性部件的接合界面发生剥离、损伤。
图24所示的半导体装置SP2以及图25所示的半导体装置SP3除了上述的不同点之外，与在上述实施方式中说明的半导体装置SP1相同，因此省略重复的说明。
<变形例2>
另外，也存在通过与在上述实施方式中说明的突起电极布局技术不同的方法来抑制将焊盘3PD与焊接指状部2BF电连接的导电性部件的接合界面的剥离、损伤的方法。图26所示的半导体装置SP4在阻焊膜SR1的开口部Sk1内从阻焊膜SR1露出的焊接指状部2BF的配线部BF3的形状与图7所示的半导体装置SP1不同。另外，图26所示的半导体装置SP4在突起电极3BP在厚度方向上与焊接指状部2BF的前端面(前端边)BFt不重叠这一点上，与图6所示的半导体装置SP1不同。
如图26所示，半导体装置SP4的多个焊接指状部2BF分别具有配置于开口部Sk1内的结合部BF1以及从结合部BF1朝向阻焊膜SR1延伸并且一部分被阻焊膜SR1覆盖的配线部BF3。
此处，多个配线部BF3分别在结合部BF1与被阻焊膜SR1覆盖的配线部BF3的一部分之间具有延伸方向变化的拐点FP。拐点FP是为了使配线部BF3的延伸方向变化而弯曲的部分，例如如图26所示，除了配线部BF3的中途折弯的弯曲构造之外，也可以是曲线地弯曲的构造。
在对半导体装置SP4施加了温度循环负荷的情况下，通过向阻焊膜SR1拉伸焊接指状部2BF而产生的拉伸力如在图26中附加箭头ST2而示出的那样，沿着配线部BF3的延伸方向产生。另一方面，在焊接指状部2BF的结合部BF1的附近，容易发生由拉伸力导致的应力集中的部分是前端面(前端边)BFt的周边部分。另外，拉伸力中的成为突起电极3BP以及焊接指状部2BF等导电性部件的接合界面的剥离的原因的分量是与前端面(前端边)BFt的延伸方向正交的方向(在图26中为X方向)的拉伸力分量。
因此，如果如图26所示的半导体装置SP4那样，在结合部BF1与被阻焊膜SR1覆盖的配线部BF3的一部分之间形成延伸方向变化的拐点FP，则作为箭头ST2而示出的拉伸力在结合部BF1的前端面(前端边)的附近被分解成箭头ST3所示的拉伸力分量以及箭头ST4所示的拉伸力分量。即，能够降低拉伸力中的成为突起电极3BP以及焊接指状部2BF等导电性部件的接合界面的剥离的原因的分量(箭头ST3所示的分量)。
这样在图26所示的变形例中，能够降低成为突起电极3BP以及焊接指状部2BF等导电性部件的接合界面的剥离的原因的拉伸力分量，因此能够抑制该接合界面的剥离、损伤。
另外，在配线部BF3在结合部BF1与被阻焊膜SR1覆盖的配线部BF3的一部分之间具有延伸方向变化的拐点FP的情况下，在产生图26中通过箭头ST2表示的拉伸力时，配线部BF3例如如弹簧那样容易发生弹性变形。并且，如果配线部BF3发生弹性变形，则能够进一步地降低传递到结合部的拉伸力。
另外，从使配线部BF3如弹簧那样发生弹性变形的观点出发，优选与配线部BF3的延伸方向正交的方向的宽度较窄。这是由于细长的金属图案更容易发生弹性变形。因此，如图26所示，配线部BF3的宽度(与配线部BF3的延伸方向正交的方向的长度)W2小于结合部BF1的宽度(沿着前端面(前端边)BFt的方向的长度)W1的情况从配线部BF3容易发生弹性变形的观点出发是优选的。
图26所示的半导体装置SP4除了上述的不同点之外，与在上述实施方式中说明的半导体装置SP1相同，因此省略重复的说明。
另外，在图26中，说明了使用含有玻璃纤维GC(参照图6)的阻焊膜SR1的实施方式。即，说明了组合了线膨胀系数调整技术以及在结合部BF1与被阻焊膜SR1覆盖的配线部BF3的一部分之间设置延伸方向变化的拐点FP的技术(以下，记载为配线部弯曲技术)的实施方式。但是，上述配线部弯曲技术能够不与线膨胀系数调整技术、突起电极布局技术组合而独立地应用。在这种情况下，将图26所示的阻焊膜SR1置换成图25所示的阻焊膜SR3。
另外，在图26中，说明了突起电极3BP在厚度方向上与焊接指状部2BF的结合部BF1的前端面(前端边)BFt不重叠的实施方式。但是，上述配线部弯曲技术能够与突起电极布局技术组合地使用。在这种情况下，抑制突起电极3BP以及焊接指状部2BF等导电性部件的接合界面的剥离的效果进一步提高。
另外，在组合了上述配线部弯曲技术、线膨胀系数调整技术以及突起电极布局技术的全部的情况下，抑制突起电极3BP以及焊接指状部2BF等导电性部件的接合界面的剥离的效果进一步提高。
<变形例3>
另外，在上述实施方式中，为了容易理解技术思想，举出在基材层2CR的上表面2CRa与下表面2CRb分别形成有配线层的两层配线层构造的配线基板2的例子来进行说明。但是，配线层的数量不限定于两层，也能够应用于3层以上的多层构造的配线基板。
例如，在图27所示的半导体装置SP5中，在基材层2CR的上表面2CRa层叠有例如通过叠压(build-up)方法形成的绝缘层、即叠压层(基材层)2BU1。另外，在基材层2CR的下表面2CRb，层叠了例如通过叠压方法形成的绝缘层、即叠压层(基材层)2BU2。然后，在基材层2CR的上表面2CRa、下表面2CRb、叠压层2BU1的上表面2BU1a、叠压层2BU2的下表面2BU2b分别形成有配线层。即，半导体装置SP5具有的配线基板2A是层叠了4层的配线层的多层配线基板。
在配线基板2A的情况下，作为端子的焊接指状部2BF形成于叠压层2BU1的上表面2BU1a。另外，在叠压层2BU1的上表面2BU1a上形成阻焊膜SR1，焊接指状部2BF的一部分(形成于开口部Sk1的外部的部分)被阻焊膜SR1覆盖。另外，焊接指状部2BF中的、形成于阻焊膜SR1的开口部Sk1内的部分从阻焊膜SR1露出。
另外，作为半导体装置SP5的外部端子的接合多个焊锡球SB的多个焊接区2LD形成于叠压层2BU2的下表面2BU2b。另外，在叠压层2BU2的下表面2BU2b上形成阻焊膜SR2，多个焊接区2LD分别在形成于阻焊膜SR2的多个开口部Sk2中从阻焊膜SR2露出。
另外，多个焊接指状部2BF与多个焊接区2LD经由使叠压层2BU1、叠压层2BU2在厚度方向上导通的多个导通配线2VA以及使基材层2CR在厚度方向上导通的多个通孔配线2TW而分别电连接。
此外，在本变形例中，将配置于厚度方向的中央的核心绝缘层记载为基材层2CR，将紧贴于基材层2CR的绝缘层记载为叠压层2BU1或者叠压层2BU2，但叠压层2BU1以及叠压层2BU2分别也包含在配线基板的基材层中。
在上述实施方式中说明的线膨胀系数调整技术中，树脂体4的线膨胀系数、紧贴于树脂体4的阻焊膜SR1的线膨胀系数和与紧贴于阻焊膜SR1的树脂体4相反侧的绝缘层(基底绝缘层)的线膨胀系数的关系是重要的。因此，在如半导体装置SP5那样使用多层配线基板的配线基板2A的情况下，树脂体4的线膨胀系数、阻焊膜SR1的线膨胀系数与芯片搭载面侧的叠压层2BU1的线膨胀系数的关系是重要的。
即，如图28所示，半导体装置SP5的配线基板2A具备的叠压层2BU1以及阻焊膜SR1分别包括玻璃纤维GC。并且，阻焊膜SR1的线膨胀系数在叠压层2BU1的线膨胀系数以上，阻焊膜SR1的线膨胀系数在树脂体4的线膨胀系数以下，并且叠压层2BU1的线膨胀系数小于树脂体4的线膨胀系数。
换言之，如果将叠压层2BU1的线膨胀系数设为α1、将阻焊膜SR1的线膨胀系数设为α2、将树脂体4的线膨胀系数设为α3，则满足(式1)或者(式2)的关系，即：
α1≤α2＜α3···(式1)
α1＜α2≤α3···(式2)。
通过上述结构，在对层叠了线膨胀系数不同的多个部件的半导体装置SP5施加温度循环负荷的情况下，也能够抑制各绝缘层的连接界面的剥离。因此，能够提高半导体装置的可靠性。
另外，作为图27以及图28所示的半导体装置SP5的另一个变形例，能够分别独立地应用上述突起电极布局技术、配线部弯曲技术，或者将上述突起电极布局技术、配线部弯曲技术分别组合来应用。
图27以及图28所示的半导体装置SP5除了上述的不同点之外，与上述实施方式中说明的半导体装置SP1相同，因此省略重复的说明。
<变形例4>
另外，在上述实施方式中，为了容易理解技术思想，说明了如图7所示地在开口部Sk1内以多个焊接指状部2BF进行配置的例子。但是，焊接指状部2BF的排列除图7所示的方式以外，还存在各种变形例。
例如，存在如图29所示的半导体装置SP6那样，在开口部Sk1内在多列的范围内配置多个焊接指状部2BF的变形例。在这种情况下，多个焊接指状部2BF中的、配置于配线基板2的外周侧的焊接指状部2BF的配线部BF2朝向配线基板2的上表面2a的周缘部延伸，配置于内周侧的焊接指状部2BF的配线部BF2朝向配线基板2的上表面2a的中央部延伸。
另外，在如半导体装置SP6那样以多列形成焊接指状部2BF的情况下，从提高端子的配置密度而降低配线基板2的平面面积的观点出发，优选将焊接指状部2BF排列成所谓的锯齿状。锯齿配置是指配置成在俯视时第1列(例如图29的纸面右侧的列)的多个焊接指状部2BF的位置与第2列(例如图29的纸面左侧的列)的位置交替地错位的排列方法。详细而言，锯齿配置是指以第1列的结合部BF1的前端面(前端边)BFt与第2列的多个焊接指状部2BF中的、相邻的焊接指状部2BF之间的间隙对置的方式交替地错开第1列以及第2列的多个焊接指状部2BF而配置的排列方法。
另外，例如，还存在如图30所示的半导体装置SP7那样焊接指状部2BF不具有图6所示的前端面(前端边)BFt而在结合部BF1的延伸方向的两端连接配线部BF2的变形例。如果如半导体装置SP7那样，在焊接指状部2BF的结合部BF1的两端连接配线部BF2，则能够使引出配线延伸到配线基板2的上表面2a的周缘部或者中央部的任一方。因此，配线设计的自由度提高。
另外，作为图29所示的半导体装置SP6、图30所示的半导体装置SP7的另一个变形例，能够分别独立地应用上述突起电极布局技术、配线部弯曲技术，或者将上述突起电极布局技术、配线部弯曲技术分别组合地应用。但是，在图30所示的半导体装置SP8的情况下，在结合部BF1的两端连接配线部BF2，因此即使在俯视时使突起电极3BP与结合部BF1的位置关系错开，也难以使覆盖结合部BF1的侧面的焊接材料SD1量充分地增加。因此，在半导体装置SP7的情况下，优选不应用上述的突起电极布局技术，而按照突起电极3BP与焊接指状部2BF的结合部BF1的中央部对置那样的位置关系来连接突起电极3BP与焊接指状部2BF的结合部BF1。
图29所示的半导体装置SP6以及图30所示的半导体装置SP7除了上述的不同点之外，与上述实施方式中说明的半导体装置SP1相同，因此省略重复的说明。
<变形例5>
另外，在上述实施方式中，作为将半导体芯片3与配线基板2电连接的导电性部件，说明了在焊盘3PD上隔着基底金属膜3UB而形成柱状的突起电极3BP，并经由焊接材料SD1将突起电极3BP与焊接指状部2BF电连接的实施方式。但是，将半导体芯片3与配线基板2电连接的导电性部件存在各种变形例。
例如虽然省略图示，存在不形成图6所示的基底金属膜3UB的变形例。
另外，例如存在如图31所示的半导体装置SP8那样使用应用导线焊接技术而形成的螺栓形凸块3BPs来作为突起电极3BP的变形例。图31中记载的螺栓形凸块3BPs通过球形焊接技术、即在使导线的前端熔融而形成球部之后将球部压接到被接合部而接合的接合方法来形成。例如，若由金形成螺栓形凸块3BPs，则在焊接材料SD1与突起电极3BP的接合部，形成金与焊料的合金层，能够提高接合强度。
形成该螺栓形凸块3BPs的工序能够在图8所示的突起电极形成工序中在切割半导体晶圆之前进行。另外，在由金形成螺栓形凸块3BPs的情况下，能够省略在半导体芯片准备工序中包含的焊接材料形成工序。
另外，如半导体装置SP8那样，在使突起电极3BP为螺栓形凸块3BPs的情况下，也能够独立地应用上述线膨胀系数调整技术、突起电极布局技术以及配线部弯曲技术中的某一个。另外，能够组合线膨胀系数调整技术、突起电极布局技术以及配线部弯曲技术中的两个以上地应用。
此外，螺栓形凸块3BPs利用在进行球形焊接时使用的夹具即腔室(省略图示)来成型，并通过切断多余的导线而形成。因此，不明确地形成图6所示的柱状的突起电极3BP那样的前端面BPt的情况较多。在半导体装置SP8的构造中，在应用上述突起电极布局技术的情况下，如果图31所示的螺栓形凸块3BPs的至少一部分在厚度方向上与焊接指状部2BF的前端面BFt重叠，则能够增加覆盖前端面BFt的焊接材料SD1的量。
另外，例如，存在如图32所示的半导体装置SP9那样，利用焊接材料SD1来作为突起电极3BP的变形例。半导体装置SP9是能够在半导体芯片3的正面3a上层叠再配线层、并且在与焊盘3PD在厚度方向上不重叠的位置配置作为突起电极3BP的焊接材料SD1的半导体封装。
半导体装置SP9中，在半导体芯片的焊盘3PD连接再配线3RD，并经由基底金属膜3UB而将焊接材料SD1连接到再配线3RD。再配线3RD是用于将俯视时的焊接材料SD1变换到与焊盘3PD不同的位置的配线。通过使再配线3RD介于突起电极3BP与焊盘3PD之间，也能够将作为半导体芯片3的接口端子的突起电极3BP的位置配置成例如矩阵状。
半导体装置SP9具有的再配线层是在对半导体晶圆实施单片化而取得半导体芯片3之前，利用在半导体晶圆形成集成电路的工序而形成的。因此，半导体装置SP9那样的半导体封装被称为WPP(Wafer Process Package，晶圆工艺封装)。
另一方面，搭载WPP类型的半导体封装的配线基板2也可以是与上述实施方式相同的构造，针对每个焊接材料SD1的连接部分形成开口部Sk1的情况较多。另外，如图32所示，作为配线基板2侧的端子的焊接指状部(焊接焊盘)2BF的结合部的前端面BFt被阻焊膜SR1覆盖。通过阻焊膜SR1覆盖端子的周缘部而得的构造被称为SMD(Solder Mask Defined，阻焊层限定)构造。
在半导体装置SP9的情况下，成为SMD构造，因此难以应用上述突起电极布局技术以及配线弯曲技术。但是，能够应用线膨胀系数调整技术。即，阻焊膜SR1的线膨胀系数在基材层2CR的线膨胀系数以上，阻焊膜SR1的线膨胀系数在树脂体4的线膨胀系数以下，并且基材层2CR的线膨胀系数小于树脂体4的线膨胀系数。因此，能够抑制在树脂体4中产生图34所示的裂纹CLK1。另外，能够抑制由于裂纹CLK1发展而导致焊接指状部2BF受到损伤。
在半导体装置SP9的制造方法中，在图8所示的突起电极形成工序之前进行再配线层形成工序。在再配线工序中，形成包含图32所示的再配线3RD的再配线层。另外，在图8所示的突起电极形成工序中，形成由焊接材料SD1构成的突起电极3BP，省略在半导体芯片准备工序中包含的焊接材料形成工序。
图31所示的半导体装置SP8以及图32所示的半导体装置SP9除了上述不同点之外，与上述实施方式中说明的半导体装置SP1相同，因此省略重复的说明。
另外，例如，存在如图33所示的半导体装置SP10那样，以半导体芯片3的背面3b与配线基板2的上表面2a对置的方式在配线基板2上搭载半导体芯片3的所谓面朝上安装方式的变形例。
在半导体装置SP10那样通过面朝上安装方式搭载半导体芯片3的情况下，半导体芯片3的焊盘3PD与配线基板2的焊接指状部2BF经由作为导电性部件的导线BW电连接。另外，在半导体装置SP10的情况下，树脂体4不具有密封将半导体芯片3与配线基板2电连接的部分(即导线BW)的功能。对于树脂体4，要求作为将半导体芯片3粘接固定于配线基板2的粘接材料的功能。另外，在通过导线BW连接焊盘3PD与焊接指状部2BF的情况下，需要形成导线环形状，因此焊接指状部2BF的结合部配置成相比搭载了半导体芯片3的区域更靠周缘部侧，在半导体芯片3之间需要一定程度的距离。因此，如图33所示，在面朝上安装方式的半导体装置SP10的情况下，树脂体4部埋入到开口部Sk1内的情况较多。
因此，不易产生在上述实施方式中说明的课题中的、产生图34所示的裂纹CLK1的课题。另外，产生使用图34说明的、由于将焊接指状部2BF向阻焊膜SR1的方向拉伸而在接合部产生应力的现象。但是，导线BW与在上述实施方式中说明的突起电极3BP相比延伸距离更长，因此通过导线BW自身发生变形，能够缓和一定程度的应力。因此，上述突起电极布局技术以及配线部弯曲技术是在通过倒装片连接方式将半导体芯片3搭载于配线基板2的情况下能够得到特别大的效果的技术。
但是，关于由于温度循环负荷而有可能在树脂体4与阻焊膜SR1的密合界面发生剥离这样的课题，在半导体装置SP10的情况下也有可能产生。另外，树脂体4是粘接固定半导体芯片3的部件，因此如果从配线基板2剥离，则成为半导体装置SP10的可靠性降低的原因。因此，优选应用上述线膨胀系数调整技术。
另外，图33所示的半导体装置SP10需要密封多个导线BW来进行保护，因此形成密封半导体芯片3以及多个导线BW的密封体(树脂体)5。阻焊膜SR1的开口部Sk1内通过该密封体5来堵塞。
另外，图33所示的半导体装置SP10制造方法与图8所示的工序在以下方面不同。即，在半导体准备工序中，省略突起电极形成工序以及焊接材料形成工序。另外，在半导体芯片工序中，隔着作为粘接材料的树脂体4，在配线基板2的上表面2a上以面朝上安装方式搭载半导体芯片3。另外，在半导体芯片搭载工序与密封工序之间，追加将半导体芯片3与配线基板2电连接的导线焊接工序。另外，在密封工序中，以覆盖半导体芯片3以及多个导线BW的方式供给树脂，形成密封体5。
图33所示的半导体装置SP10除了上述的不同点之外，与上述实施方式中说明的半导体装置SP1相同，因此省略重复的说明。
<变形例6>
另外，在不脱离在上述实施方式中说明的技术思想的主旨的范围内，能够将变形例彼此组合来应用。
另外，如果对在实施方式、其变形例中说明的半导体装置以及半导体装置的制造方法提取技术思想，则能够如下所述地表现。
〔附记1〕
一种半导体装置，
包括：配线基板，具备基材层、形成于所述基材层的第1面的多个第1端子以及覆盖所述基材层的所述第1面的第1绝缘层；
半导体芯片，具备正面、所述正面的相反侧的背面、形成于所述正面的多个焊接焊盘以及在所述多个焊接焊盘上分别形成的多个突起电极，在所述正面与所述配线基板的所述第1面对置的状态下，隔着所述多个突起电极而搭载于所述配线基板；
多个焊接材料，分别连接所述多个突起电极与所述多个第1端子；以及
第2绝缘层，配置于所述配线基板与所述半导体芯片之间，对所述多个突起电极与所述多个第1端子的连接部分以及形成于所述第1绝缘层的第1开口部内进行密封，
所述多个第1端子分别从所述第1绝缘层的所述第1开口部露出，
所述多个第1端子分别具有：
结合部，形成于所述第1开口部内；以及
配线部，从所述结合部朝向所述第1绝缘层延伸，并且一部分被所述第1绝缘层覆盖，
所述配线部在所述结合部与被所述第1绝缘层覆盖的部分之间具有延伸方向变化的拐点。
〔附记2〕
一种半导体装置的制造方法，具有以下工序：
(a)工序，准备配线基板，该配线基板具备基材层、形成于所述基材层的第1面的多个第1端子以及覆盖所述基材层的所述第1面的第1绝缘层；
(b)工序，准备半导体芯片，该半导体芯片具备正面、所述正面的相反侧的背面、形成于所述正面的多个焊接焊盘以及形成于所述正面侧并且与所述多个焊接焊盘分别电连接的多个突起电极；以及
(c)工序，在所述(a)工序以及所述(b)工序之后，隔着第2绝缘层而将所述半导体芯片搭载于所述配线基板的所述第1面侧，
其中，所述多个第1端子分别从形成于所述第1绝缘层的第1开口部露出，
所述配线基板的所述基材层以及所述第1绝缘层分别由多个填料粒子和含有玻璃纤维的树脂构成，
所述第1绝缘层的线膨胀系数在所述基材层的线膨胀系数以上，并且所述第1绝缘层的线膨胀系数在所述第2绝缘层的线膨胀系数以下，并且所述基材层的线膨胀系数小于所述第2绝缘层的线膨胀系数。
标号说明
2、2A 配线基板
2a 上表面(面、主面、芯片搭载面)
2A 配线基板
2b 下表面(面、主面、安装面)
2BF 焊接指状部(端子、电极、内部接口端子、焊接焊盘)
2BU1、2BU2 叠压层(基材层)
2BU1a 上表面
2BU2b 下表面
2CR 基材层(核心层、绝缘层)
2CRa 第1面、主面、焊接指状部形成面)
2CRb 第2面、主面、焊接区形成面)
2LD 多个焊接区(端子、电极、外部接口端子、外部端子)
2s 侧面
2TW 通孔配线
2VA 导通配线
3 半导体芯片
3a 正面(主面、上表面)
3b 背面(主面、下表面)
3BP 突起电极(导电性部件、柱凸块、螺栓形凸块、焊料凸块)
3BPs 螺栓形凸块
3F、3F1、3F2 绝缘膜
3Fk 开口部
3PD 焊盘(焊接焊盘、电极、电极焊盘)
3RD 再配线
3s 侧面
3UB 基底金属膜(凸块下金属)
4 树脂体(绝缘层、底部填充材料、密封材料、粘接材料、芯片焊接材料)
4p 树脂
5 密封体(树脂体)
20 配线基板(多片基板)
20a 产品形成区域
20b 框部(框体)
20c 切割线(切割区域)
BF1 结合部(焊接部)
BF2、BF3 配线部
BFt 前端面(前端边)
BPt 前端面
BW 导线(导电性部件、金属线)
CLK1 裂纹
DCb 划片刀(旋转刀)
DCd 夹具
FP 拐点
GC 玻璃纤维(纤维材料)
H1 半导体装置
MS 掩模
MSh 贯通孔(开口部)
NZ1 向外侧供给树脂用的喷嘴
PK1 半导体装置
SB 焊锡球(焊接材料、外部端子、电极、外部电极)
SD1、SD2、SD3 焊接材料
Sk1、Sk2 开口部
SP1、SP2、SP3、SP4、SP5、SP6、SP7、SP8、SP9、SP10、H1 半导体装置(半导体封装)
SR1、SR2、SRh 阻焊膜(绝缘层)
ST1、ST2、ST3、ST4 箭头(拉伸力)
W1、W2 宽度(长度)
WH 晶圆(半导体晶圆)
WHa 芯片区域(设备区域)
WHb 划片槽(划片区域)。

Claims (12)

1.一种半导体装置，其特征在于，
包括：配线基板，具备基材层、形成于所述基材层的第1面的多个第1端子以及覆盖所述基材层的所述第1面的第1绝缘层；
半导体芯片，具有正面、所述正面的相反侧的背面以及形成于所述正面的多个焊接焊盘，并且搭载于所述第1绝缘层上；以及
第2绝缘层，配置于所述配线基板与所述半导体芯片之间，分别紧贴于所述第1绝缘层以及所述半导体芯片，
所述多个第1端子分别从形成于所述第1绝缘层的第1开口部露出，
所述配线基板的所述基材层以及所述第1绝缘层分别由多个填料粒子和含有玻璃纤维的树脂构成，
所述第1绝缘层的线膨胀系数在所述基材层的线膨胀系数以上，并且所述第1绝缘层的线膨胀系数在所述第2绝缘层的线膨胀系数以下，并且所述基材层的线膨胀系数小于所述第2绝缘层的线膨胀系数。
2.根据权利要求1所述的半导体装置，其特征在于，
所述半导体芯片在所述正面侧与所述配线基板的所述第1面侧对置的状态下，隔着与所述多个焊接焊盘电连接的多个突起电极而搭载于所述配线基板，
所述多个突起电极与所述多个第1端子的连接部分以及所述第1绝缘层的所述第1开口部内通过所述第2绝缘层来密封。
3.根据权利要求2所述的半导体装置，其特征在于，
所述多个突起电极形成于所述多个焊接焊盘上，经由多个焊接材料而与所述多个第1端子电连接，
所述多个突起电极由与所述多个焊接材料不同的材料形成。
4.根据权利要求3所述的半导体装置，其特征在于，
所述多个第1端子分别具备形成于所述第1开口部内的、具有前端边的结合部，
在俯视时，所述多个突起电极与所述多个第1端子所具有的结合部的前端边分别重叠。
5.根据权利要求2所述的半导体装置，其特征在于，
所述多个第1端子分别具有：
结合部，形成于所述第1开口部内；以及
配线部，从所述结合部朝向所述第1绝缘层延伸，并且一部分被所述第1绝缘层覆盖，
所述配线部在所述结合部与被所述第1绝缘层覆盖的所述配线部的一部分之间具有延伸方向变化的拐点。
6.根据权利要求5所述的半导体装置，其特征在于，
与所述配线部的延伸方向正交的方向的宽度比所述结合部的宽度小。
7.根据权利要求3所述的半导体装置，其特征在于，
所述多个突起电极经由形成于所述多个焊接焊盘上的多个基底导电膜而与所述多个焊接焊盘连接，
所述多个突起电极隔着所述多个基底导电膜而形成于所述多个焊接焊盘上。
8.根据权利要求1所述的半导体装置，其特征在于，
所述配线基板具备：所述多个第1端子；多个第2端子，形成于与所述第1面相反侧的所述基材层的第2面，并且与所述多个第1端子分别电连接；第3绝缘层，覆盖所述基材层的所述第2面；以及第2开口部，形成于所述第3绝缘层，并且使所述多个第2端子分别露出，
所述第3绝缘层由多个填料粒子以及含有玻璃纤维的树脂形成，
所述第3绝缘层的线膨胀系数在所述基材层的线膨胀系数以上。
9.一种半导体装置的制造方法，其特征在于，
具有以下工序：
(a)工序，准备配线基板，该配线基板具备基材层、形成于所述基材层的第1面的多个第1端子以及覆盖所述基材层的所述第1面的第1绝缘层；
(b)工序，准备半导体芯片，该半导体芯片具备正面、所述正面的相反侧的背面、形成于所述正面的多个焊接焊盘以及形成于所述正面侧并且与所述多个焊接焊盘分别电连接的多个突起电极；
(c)工序，在所述(a)工序以及所述(b)工序之后，以所述半导体芯片的所述正面与所述配线基板的所述第1面对置的方式，将所述半导体芯片搭载于所述配线基板，并将所述多个突起电极与所述多个第1端子电连接；以及
(d)工序，在所述(c)工序之后，向所述配线基板与所述半导体芯片之间供给树脂，形成分别紧贴于所述第1绝缘层以及所述半导体芯片的第2绝缘层，
其中，所述多个第1端子分别从形成于所述第1绝缘层的第1开口部露出，
所述配线基板的所述基材层以及所述第1绝缘层分别由多个填料粒子和含有玻璃纤维的树脂构成，
所述第1绝缘层的线膨胀系数在所述基材层的线膨胀系数以上，并且所述第1绝缘层的线膨胀系数在所述第2绝缘层的线膨胀系数以下，并且所述基材层的线膨胀系数小于所述第2绝缘层的线膨胀系数。
10.根据权利要求9所述的半导体装置的制造方法，其特征在于，
在通过所述(a)工序准备的配线基板的所述多个第1端子的露出面，分别形成有多个第1焊接材料，
在通过所述(b)工序准备的所述半导体芯片的所述多个突起电极的前端面，分别形成有多个第2焊接材料，
在所述(c)工序中，对所述多个第1焊接材料与所述多个第2焊接材料进行加热而一体化，从而将所述多个突起电极与所述多个第1端子电连接。
11.根据权利要求10所述的半导体装置的制造方法，其特征在于，
通过所述(a)工序准备的所述配线基板的所述多个第1端子分别具有：
结合部，形成于所述第1开口部内，并具有前端边；以及
配线部，从所述结合部朝向与所述前端边相反的方向延伸，并且一部分被所述第1绝缘层覆盖，
在所述(c)工序中，以在俯视时所述多个突起电极与所述多个第1端子的前端边分别重叠的状态固定所述半导体芯片。
12.根据权利要求10所述的半导体装置的制造方法，其特征在于，
通过所述(a)工序准备的所述配线基板的所述多个第1端子分别具有：
结合部，形成于所述第1开口部内；以及
配线部，从所述结合部朝向所述第1绝缘层延伸，并且一部分被所述第1绝缘层覆盖，
所述配线部在所述结合部与被所述第1绝缘层覆盖的部分之间具有延伸方向变化的拐点。
CN201380079870.6A 2013-09-27 2013-09-27 半导体装置及其制造方法 Active CN105593986B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2013/076227 WO2015045089A1 (ja) 2013-09-27 2013-09-27 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
CN105593986A CN105593986A (zh) 2016-05-18
CN105593986B true CN105593986B (zh) 2018-10-19

Family

ID=52742293

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380079870.6A Active CN105593986B (zh) 2013-09-27 2013-09-27 半导体装置及其制造方法

Country Status (8)

Country Link
US (2) US9837369B2 (zh)
EP (1) EP3051583B1 (zh)
JP (1) JP6169713B2 (zh)
KR (1) KR102110332B1 (zh)
CN (1) CN105593986B (zh)
HK (1) HK1219347A1 (zh)
TW (1) TWI619214B (zh)
WO (1) WO2015045089A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6362066B2 (ja) * 2013-12-17 2018-07-25 キヤノン株式会社 プリント回路板の製造方法及びプリント回路板
JP6792322B2 (ja) * 2015-05-12 2020-11-25 昭和電工マテリアルズ株式会社 半導体装置及び半導体装置の製造方法
JP6846117B2 (ja) * 2016-04-12 2021-03-24 ローム株式会社 半導体装置および半導体装置の製造方法
JP6702019B2 (ja) * 2016-06-22 2020-05-27 株式会社ジェイテクト 半導体装置
JP2018046092A (ja) * 2016-09-13 2018-03-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US10276465B2 (en) * 2016-09-29 2019-04-30 Mediatek Inc. Semiconductor package assembly
KR102009905B1 (ko) * 2017-02-21 2019-08-12 삼성전자주식회사 팬-아웃 반도체 패키지
JP2018206797A (ja) * 2017-05-30 2018-12-27 アオイ電子株式会社 半導体装置および半導体装置の製造方法
JP6515243B2 (ja) * 2018-11-14 2019-05-15 アオイ電子株式会社 半導体装置の製造方法
TWI693644B (zh) * 2019-01-28 2020-05-11 鼎元光電科技股份有限公司 封裝結構及其製造方法
KR20210101574A (ko) * 2020-02-10 2021-08-19 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
KR102587161B1 (ko) * 2022-06-15 2023-10-11 엘지이노텍 주식회사 반도체 패키지

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1674219A (zh) * 2004-03-22 2005-09-28 日立化成工业株式会社 半导体器件和用于半导体器件的多层基板
CN1864254A (zh) * 2003-10-06 2006-11-15 日本电气株式会社 电子器件及其制造方法
CN101047154A (zh) * 2006-03-29 2007-10-03 台湾积体电路制造股份有限公司 半导体装置及其形成方法
CN101103450A (zh) * 2005-03-14 2008-01-09 住友电木株式会社 半导体装置
CN102856220A (zh) * 2011-06-30 2013-01-02 瑞萨电子株式会社 半导体器件的制造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3420076B2 (ja) 1998-08-31 2003-06-23 新光電気工業株式会社 フリップチップ実装基板の製造方法及びフリップチップ実装基板及びフリップチップ実装構造
JP3639736B2 (ja) * 1999-01-20 2005-04-20 新光電気工業株式会社 半導体装置用パッケージ
JP2001053448A (ja) * 1999-08-12 2001-02-23 Ibiden Co Ltd プリント配線板、ソルダーレジスト樹脂組成物およびプリント配線板の製造方法
JP3888302B2 (ja) * 2002-12-24 2007-02-28 カシオ計算機株式会社 半導体装置
US8574959B2 (en) * 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
JP4740765B2 (ja) * 2006-02-24 2011-08-03 エルピーダメモリ株式会社 半導体装置及びその製造方法
JP4929784B2 (ja) * 2006-03-27 2012-05-09 富士通株式会社 多層配線基板、半導体装置およびソルダレジスト
MY148173A (en) * 2006-04-28 2013-03-15 Sumitomo Bakelite Co Solder resist material, wiring board using the solder resist material, and semiconductor package
US8258620B2 (en) * 2007-08-10 2012-09-04 Sanyo Electric Co., Ltd. Circuit device, method of manufacturing the circuit device, device mounting board and semiconductor module
JP2009064812A (ja) * 2007-09-04 2009-03-26 Panasonic Corp 半導体装置の電極構造およびその関連技術
JP2012049219A (ja) * 2010-08-25 2012-03-08 Fujitsu Ltd 電子装置
US8435834B2 (en) * 2010-09-13 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP
JP5587123B2 (ja) * 2010-09-30 2014-09-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR20140023980A (ko) * 2011-04-14 2014-02-27 스미토모 베이클리트 컴퍼니 리미티드 적층판, 회로 기판 및 반도체 패키지
US20130070437A1 (en) * 2011-09-20 2013-03-21 Invensas Corp. Hybrid interposer
US9679863B2 (en) * 2011-09-23 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interconnect substrate for FO-WLCSP
JP2013122957A (ja) * 2011-12-09 2013-06-20 Dexerials Corp 接続方法、接続構造体、絶縁性接着部材、及び、接着部材付電子部品及びその製造方法
US20140183744A1 (en) * 2012-12-28 2014-07-03 Texas Instruments Incorporated Package substrate with bondable traces having different lead finishes
JP6230794B2 (ja) * 2013-01-31 2017-11-15 新光電気工業株式会社 電子部品内蔵基板及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1864254A (zh) * 2003-10-06 2006-11-15 日本电气株式会社 电子器件及其制造方法
CN1674219A (zh) * 2004-03-22 2005-09-28 日立化成工业株式会社 半导体器件和用于半导体器件的多层基板
CN101103450A (zh) * 2005-03-14 2008-01-09 住友电木株式会社 半导体装置
CN101047154A (zh) * 2006-03-29 2007-10-03 台湾积体电路制造股份有限公司 半导体装置及其形成方法
CN102856220A (zh) * 2011-06-30 2013-01-02 瑞萨电子株式会社 半导体器件的制造方法

Also Published As

Publication number Publication date
EP3051583A1 (en) 2016-08-03
US9837369B2 (en) 2017-12-05
EP3051583A4 (en) 2017-05-17
US20160233189A1 (en) 2016-08-11
JPWO2015045089A1 (ja) 2017-03-02
KR20160061342A (ko) 2016-05-31
US20180047695A1 (en) 2018-02-15
WO2015045089A1 (ja) 2015-04-02
JP6169713B2 (ja) 2017-07-26
CN105593986A (zh) 2016-05-18
HK1219347A1 (zh) 2017-03-31
TW201519392A (zh) 2015-05-16
TWI619214B (zh) 2018-03-21
EP3051583B1 (en) 2018-09-19
KR102110332B1 (ko) 2020-05-14

Similar Documents

Publication Publication Date Title
CN105593986B (zh) 半导体装置及其制造方法
US6462412B2 (en) Foldable, flexible laminate type semiconductor apparatus with reinforcing and heat-radiating plates
US10879203B2 (en) Stud bump structure for semiconductor package assemblies
US8389339B2 (en) Method of manufacturing semiconductor device
US9177936B2 (en) Method of manufacturing semiconductor device
JP5789431B2 (ja) 半導体装置の製造方法
US9455240B2 (en) Method of manufacturing semiconductor device and semiconductor device
US20100261311A1 (en) Method of manufacturing a semiconductor device
KR20080083533A (ko) 플립-칩 방식의 적층형 파워 모듈 및 그 파워 모듈의제조방법
US9443823B2 (en) Semiconductor device including filling material provided in space defined by three semiconductor chips
US9023717B2 (en) Method for manufacturing semiconductor device
TW201505145A (zh) 半導體裝置及其製造方法
KR20140124725A (ko) 반도체 장치 및 그 제조 방법
KR20140097535A (ko) 반도체 장치 및 반도체 장치의 제조 방법
US8796132B2 (en) System and method for forming uniform rigid interconnect structures
WO2012053129A1 (ja) 半導体装置及びその製造方法
JP2015015362A (ja) 半導体装置の製造方法
CN114256173A (zh) 散热封装系统及其制作方法
JP2004047563A (ja) 半導体装置
JP2022081872A (ja) 半導体装置およびその製造方法
JP2012174900A (ja) 半導体装置の製造方法
US20090189272A1 (en) Wafer Level Chip Scale Packages Including Redistribution Substrates and Methods of Fabricating the Same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1219347

Country of ref document: HK

GR01 Patent grant
GR01 Patent grant