CN101047154A - 半导体装置及其形成方法 - Google Patents
半导体装置及其形成方法 Download PDFInfo
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- CN101047154A CN101047154A CNA2007100869873A CN200710086987A CN101047154A CN 101047154 A CN101047154 A CN 101047154A CN A2007100869873 A CNA2007100869873 A CN A2007100869873A CN 200710086987 A CN200710086987 A CN 200710086987A CN 101047154 A CN101047154 A CN 101047154A
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Abstract
本发明是提供一种半导体装置及其形成方法。上述半导体装置的形成方法包含:通过介于一集成电路芯片与一封装基板或印刷电路板之间的多个软焊料凸块,将上述集成电路芯片与上述封装基板或印刷电路板结合,上述集成电路芯片具有至少一介电层,上述介电层的介电常数较好为不大于3.0,上述软焊料的铅浓度较好为不大于5wt%;以及形成一多层式的底胶层于上述集成电路芯片与上述封装基板或印刷电路板之间。本发明所述的半导体装置及其形成方法,可提升半导体装置的可靠度。
Description
技术领域
本发明是有关于半导体技术,特别是关于集成电路封装体及其形成方法。
背景技术
将一集成电路芯片与一封装基板连接或直接连接至一印刷电路板所使用的覆晶技术中,是在上述集成电路芯片的主动面上,形成多个导电性接点(连接垫);上述封装基板或印刷电路板亦具有多个连接垫,分别对应于上述集成电路芯片上的导电性接点。多个软焊料凸块(solder bump)是形成于上述集成电路芯片的导电性接点上或是上述封装基板或印刷电路板中对应于上述集成电路芯片的平面上的连接垫上。将上述软焊料凸块加热后,可使其回焊于上述集成电路芯片与上述封装基板或印刷电路板之间,形成导电性与机械性的连接。“覆晶”的意思是使上述集成电路芯片以主动面朝下的方式面对上述封装基板或印刷电路板,再对上述软焊料凸块加热、熔化,而使其回焊于上述集成电路芯片的主动面与上述封装基板或印刷电路板之间,形成导电性与机械性的连接。一底胶(underfill)材料可填入上述集成电路芯片与上述封装基板或印刷电路板之间的空间,以强化二者之间的结合强度、调和及重新分布二者之间热膨胀系数值、并保护上述软焊料凸块。
上述集成电路芯片与上述封装基板或印刷电路板的热膨胀系数通常有很大的差异。例如硅的热膨胀系数为2ppm/℃~5ppm/℃、有机的封装基板的热膨胀系数约为16ppm/℃、软焊料的热膨胀系数为20ppm/℃~30ppm/℃。如果未使用底胶材料,上述软焊料凸块便成为上述集成电路芯片与上述封装基板或印刷电路板之间仅有的接合剂,而完全曝露于热应力的作用之下,反复性的热循环会使上述软焊料凸块发生破坏、失效(疲劳性破坏),而降低界面处的接合力或是在上述软焊料凸块中形成应力引发的裂痕,而通过此应力/应变的表现,会降低上述软焊料凸块对于热循环的可靠度。降低作用于上述软焊料凸块的应力/应变,可提升其可靠度及疲劳寿命。因此,通常会将上述底胶材料填入上述集成电路芯片与上述封装基板或印刷电路板之间。
上述底胶材料的热膨胀系数通常为30ppm/℃~50ppm/℃,而足以吸收残余的热应力以降低上述软焊料凸块内、以及上述软焊料凸块与上述集成电路芯片之间的界面上的热应力。
在半导体业界中,以铜金属与低介电常数材料取代铝与二氧化硅的情形已逐步增加,使用铜可降低金属内连线的电阻(并可增加其可靠度);而低介电常数材料(介电常数小于3.9,3.9为二氧化硅的介电常数)的使用则可降低金属导线之间的寄生电容。预计到了65纳米的时代,低介电常数材料的使用会有显著性的增加;而到了45纳米的时代,极低介电常数(extreme low-k;ELK)材料(介电常数为2~2.5)的使用会有显著性的增加。
然而将低介电常数材料用于内连线层时,则会增加覆晶封装体内热膨胀系数不匹配的问题。低介电常数材料的热膨胀系数约为8ppm/℃,具底胶材料的覆晶封装体会在低介电常数材料介电层上产生高应力,而会对具有低/极低介电常数材料介电层的覆晶封装体的可靠度产生冲击。
在无铅封装体中,上述热膨胀系数不匹配的问题会更加严重,无铅的软焊料凸块中的软焊料与介金属化合物(合金)的性质较脆,而会造成软焊料凸块的崩裂。
现有可适用于共晶/高铅软焊料的低应力及低玻璃转换温度的底胶材料,并无法对无铅软焊料凸块提供足够的保护;现有的无铅软焊料凸块与底胶材料的组合,无法适用于具有低介电常数材料的覆晶封装体。在使用传统的无铅软焊料与低介电常数材料的封装体中,在热循环的过程中可观察到软焊料凸块的崩裂及基板中的线路的断线的情况,亦可在植球后与可靠度试验之前处理之后,观察到底胶材料发生剥离的情形。
因此,业界需要一种改良型的半导体装置及其形成方法。
发明内容
有鉴于此,本发明的一目的是提供一种半导体装置及其形成方法,以提升半导体装置的可靠度。
为达成本发明的上述目的,本发明提供一种半导体装置,包含:一集成电路芯片,其具有至少一介电层,上述集成电路芯片是通过介于上述集成电路芯片与一封装基板或印刷电路板之间的多个软焊料凸块,与上述封装基板或印刷电路板结合;一底胶层位于上述集成电路芯片与上述封装基板或印刷电路板之间;以及一缓冲层,位于上述底胶层与上述集成电路芯片之间。
本发明所述的半导体装置,该缓冲层的热膨胀系数小于该底胶层的热膨胀系数。
本发明所述的半导体装置,该缓冲层的热膨胀系数小于10ppm/℃、该底胶层的热膨胀系数大于10ppm/℃。
本发明所述的半导体装置,该缓冲层将该集成电路芯片封于其中。
本发明所述的半导体装置,该缓冲层包含一封胶材料,该封胶材料包含一模封材料(molding compound)。
本发明又提供一种半导体装置,包含:一集成电路芯片,其具有至少一介电层;一封装基板或印刷电路板;多个软焊料凸块,介于上述集成电路芯片与该封装基板或印刷电路板之间;以及一多层式的底胶层位于上述集成电路芯片与上述封装基板或印刷电路板之间。
本发明所述的半导体装置,该多层式的底胶层包含一第一层与一第二层,该第一层与该第二层具有实质上不同的热膨胀系数。
本发明所述的半导体装置,该第一层是相邻于该集成电路芯片,其热膨胀系数小于10ppm/℃;该第二层是相邻于该封装基板或印刷电路板,其热膨胀系数大于10ppm/℃。
本发明所述的半导体装置,该多层式的底胶层具有一底胶材料与一渐变的填充物材料结构。
本发明所述的半导体装置,该渐变的填充物材料结构中,相邻于该集成电路芯片的填充物的尺寸小于相邻于该封装基板或印刷电路板的填充物的尺寸。
本发明所述的半导体装置,该渐变的填充物材料结构具有一填充物浓度梯度,且相邻于该集成电路芯片的填充物浓度与相邻于该封装基板或印刷电路板的填充物浓度之间,具有一浓度差距(gap)。
本发明所述的半导体装置,该多层式的底胶层包含一第一层与一第二层,该第一层是相邻于该集成电路芯片、该第二层是相邻于该封装基板或印刷电路板,该第一层的填充物浓度大于该第二层的填充物浓度。
本发明所述的半导体装置,该多层式的底胶层包含:一第一层,其为一底胶材料并接触该封装基板或印刷电路板,该第一层的厚度小于该集成电路芯片与该封装基板或印刷电路板之间的一第一间隔;以及一第二层,接触该集成电路芯片、并填入该集成电路芯片与该第一层之间的一第二间隔,该第二层是由一模封材料(molding compound)所形成,将该集成电路芯片封入其中。
本发明又提供一种半导体装置的形成方法,包含:通过介于一集成电路芯片与一封装基板或印刷电路板之间的多个软焊料凸块,将上述集成电路芯片与上述封装基板或印刷电路板结合,上述集成电路芯片具有至少一介电层;以及形成一多层式的底胶层于上述集成电路芯片与上述封装基板或印刷电路板之间。
本发明所述的半导体装置的形成方法,该多层式的底胶层具有一底胶材料与一填充物材料,该填充物材料包含一第一填充物粒子与一第二填充物粒子,该第一填充物粒子的尺寸大于该第二填充物粒子的尺寸,而形成该多层式的底胶层的方法包含:将该底胶材料、该第一填充物粒子与该第二填充物粒子混合,而形成一混合物;以及将该混合物加入该集成电路芯片与该封装基板或印刷电路板之间。
本发明所述的半导体装置的形成方法,更包含:形成一第一层,其为一底胶材料并使其接触该封装基板或印刷电路板,该第一层的厚度小于该集成电路芯片与该封装基板或印刷电路板之间的一第一间隔;以及加入一模封材料(molding compound)而形成一第二层,是使该第二层填入该集成电路芯片与该第一层之间的一第二间隔,将该集成电路芯片封入其中。
本发明是又提供一种半导体装置的形成方法,包含:通过介于一集成电路芯片与一封装基板或印刷电路板之间的多个软焊料凸块,将上述集成电路芯片与上述封装基板或印刷电路板结合;将一填充物材料混入一底胶材料,而形成一混合物;加入上述混合物,使其实质上填入上述集成电路芯片与上述封装基板或印刷电路板之间的间隔;在加入上述混合物之后,使上述填充物材料至少部分沉淀;以及在上述填充物材料至少部分沉淀之后,固化(cure)上述底胶材料。
本发明所述的半导体装置的形成方法,该填充物材料包含一第一填充物粒子与一第二填充物粒子,该第一填充物粒子的尺寸大于该第二填充物粒子的尺寸。
本发明所述的半导体装置及其形成方法,可提升半导体装置的可靠度。
附图说明
图1为一剖面图,是显示本发明第一实施例的半导体装置,其具有多层式的底胶。
图2为一剖面图,是显示本发明第二实施例的半导体装置,其具有多层式的底胶。
图3为一剖面图,是显示本发明第三实施例的半导体装置,其具有多层式的底胶。
图4为一剖面图,是显示本发明第四实施例的半导体装置,其具有多层式的底胶。
图5为一剖面图,是显示本发明第五实施例的半导体装置,其具有多层式的底胶。
具体实施方式
为让本发明的上述和其他目的、特征和优点能更明显易懂,下文特举出较佳实施例,并配合所附图式,作详细说明如下。
图1为一剖面图,是显示本发明第一实施例的半导体装置100的右侧。半导体装置100可以是半导体集成电路封装体或是以覆晶的方法将集成电路芯片102直接设置在印刷电路板上的结构。半导体装置100的左侧是与其右侧大体上成镜向对称,其所包含的元件可参考已绘示于图中的部分,而未绘示于图1中。
半导体装置100具有一多层式的底胶层125,其各层之间的性质的关系,是择自下列族群之一:具有各种不同的热膨胀系数、具有各种不同的填充物浓度、具有填充物浓度梯度(渐变的填充物浓度)与具有各种不同的填充物尺寸,关于各种的多层式的底胶层的实例将于后文依次说明。
半导体装置100具有一集成电路芯片102,其包含至少一介电层102d。虽然为了方便显示,图1仅绘示单一的介电层102d,本发明本领域技术人员应当了解,集成电路芯片102通常是具有多个内连线层,包含交错的金属层与层间介电层。介电层102d可以是低介电常数介电层,其介电常数在3.9以下,而较好为3.0以下;而在某些实施例中,其介电常数可约为2.75。在某些实施例中,介电层102d为一极低介电常数介电层,其介电常数为2.0~2.5。另外,集成电路芯片102的热膨胀系数约为3ppm/℃。
集成电路芯片102具有多个具导电性的第一接触垫106,其材质可以是铝或其他适合的金属或合金。一图形化的保护层108覆于集成电路芯片102上,而曝露出第一接触垫106。保护层108的材质可以是任何适合的保护材料例如但不限于氧化硅、氮化硅、氮氧化硅或其他适合的保护材料,其形成可使用化学气相沉积法、物理气相沉积法、旋涂法或其他适用于形成薄膜的方法。一第一凸块下金属(under-bump metallization;UBM)层112是覆于每个第一接触垫106上。在某些实施例中,第一凸块下金属层112包含不同金属的多层结构,例如包含一粘着层、一扩散阻障层、一可焊(solderable)层与一氧化阻障层。第一凸块下金属层112可为镍/金是材质或是其他适合的金属、合金、一系列的金属或一系列的合金,例如但不限于铬/铬-铜/铜、钛/镍-钒、钛/铜或钛/钨/金。连续性的凸块下金属复合层可在真空下以蒸镀法或溅镀法形成或是以晶圆级(wafer level)的化学镀所形成。
集成电路芯片102是以覆晶的技术粘着于基板104上。在某些实施例中,基板104为一封装基板,其热膨胀系数约为16ppm/℃;在其他实施例中,基板104为由有机材料、陶瓷或硅基板所形成的印刷电路板,其上表面具有多个第二接触垫116与一防焊层118,防焊层118是位于第二接触垫116上并曝露第二接触垫116。多个软焊料凸块110形成集成电路芯片102上的第一接触垫106与基板104上对应的第二接触垫116之间的内连线。在某些实施例中,软焊料凸块110是通过适当的已知方法或未来可能发展出的方法,先形成于集成电路芯片102上。首先,以例如光刻的步骤,将第一接触垫106曝露出来;然后如前述的方法形成第一凸块下金属层112后,再形成软焊料凸块110。有许多种方法可将软焊料凸块110形成于第一凸块下金属层112上,例如蒸镀、电镀、印刷法、喷射法(jetting)、焊线法、焊球残留凸块形成技术(stud bumping;其步骤与传统焊线法相似,但在接触垫上形成焊球后即将焊线截断,而以该焊球作为凸块)或直接注入法(direct displacement)。在某些实施例中是使用共晶材质的焊料,而亦可以使用高铅或无铅材质的焊料;在某些实施例中,焊料的铅浓度不大于5wt%,焊料可以是但不局限于金属和合金,例如但不限于锡、铟、镍、锡-铅、锡-铟、锡-银、锡-铋、锡-铋-锌、锡-银-铟、锡-银-铜、锡-铋-铟、锡-铋-锑、锡-银-铋-铟、锡-银-铜-锑、锡-银-铋-铜-锑或锡-银-铋-铟-锑。在另外的实施例中,软焊料凸块110是通过适当的已知方法或未来可能发展出的方法,先形成于集成电路芯片102上。首先,以例如光刻的步骤,将第二接触垫116曝露出来;然后如前述形成第一凸块下金属层112的方法与类似材质,在每个第二接触垫116上各形成一第二凸块下金属层122之后,再以上述相同的方法与材质,在第二凸块下金属层122上形成软焊料凸块110。
半导体装置100具有一多层式的底胶层125,其位于集成电路芯片102与基板104(封装基板或印刷电路板)之间,多层式的底胶层125具有至少二层或二区,各层或各区具有不同的热膨胀系数。在本实施例中,多层式的底胶层125具有一第一层140与一第二层130。在某些实施例中,多层式的底胶层125中的第一层140与第二层130均为均质的材质,且第一层140与第二层130的热膨胀系数分别大体上为常数;在其他实施例中,第一层140与第二层130中,至少其中之一可再分为具有不同热膨胀系数的次层(sub-layer)结构;在另外的其他实施例中,第一层140与第二层130中,至少其中之一的热膨胀系数是随着其厚度方向而变化。例如在某些实施例中,多层式的底胶层125中,与基板104接触的那一侧的热膨胀系数为最大值,与集成电路芯片102接触的那一侧的热膨胀系数为最小值,其热膨胀系数大体上呈现线性函数或多项式函数的变化;而在其他实施例中,多层式的底胶层125的热膨胀系数是呈现阶梯函数(step function)的变化,在其厚度方向,愈接近基板104,其热膨胀系数呈现非连续性的增加。
第二层130是覆于基板104上,其所包含的底胶材质可以是聚合物,包含例如环氧树脂、氰酸酯(cyanate ester)、以芳香族-环氧乙烷(aromatic oxirane)为封端(end-capped)的官能团连接Si-O2官能团的Siloxirane、马来酰亚胺(maleimide)、聚苯并噁嗪(polybenzoxazine)或聚酰亚胺(polyimide),其中上述环氧树脂例如为双酚A(bisphenol A)树脂、双酚F(bisphenol F)树脂或环脂族环氧树脂(cycloaliphatic epoxy resins)。
第二层130的材质可包含固化剂(或交联剂)、催化剂、增韧剂(toughening agent)与助焊剂。第二层130的热膨胀系数与基板104的热膨胀系数近似,较好为大于10ppm/℃,更好约为10ppm/℃~16ppm/℃。第二层130可包含一填充物,其材质可根据第二层130所包含的底胶材质作选择,可将第二层130的热膨胀系数最佳化至预设值。上述填充物可为粒状的无机材料例如二氧化硅(silica)、氧化铝(alumina)、碳、氮化铝或上述的组合。
将第二层130覆于基板104的方法包含但不限于印刷法、旋涂法或点胶法(dispensing);第二层130的厚度小于将集成电路芯片102与基板104结合后二者之间的间隙,例如为集成电路芯片102与基板104之间的间隙的0.2~0.8倍。在某些实施例中,第二层130的厚度为集成电路芯片102与基板104之间的间隙的0.4~0.6倍;在某些实施例中,第二层130的厚度约为集成电路芯片102与基板104之间的间隙的0.5倍。
第一层140的形成是在结合集成电路芯片102与基板104之后,是以点胶的方式使其散布于集成电路芯片102与第二层130之间的间隙,而完全填满该空隙。在某些实施例中,第一层140是使用真空点胶法(vacuum dispensing),以使第一层140均匀地散布于集成电路芯片102与第二层130之间的间隙,并避免气泡、空孔的产生。第一层140的热膨胀系数小于10ppm/℃;在某些实施例中,第一层140的热膨胀系数为7ppm/℃~9ppm/℃。适于作为第一层140的材料例如为聚酰亚胺的模封材料(moldingcompound)或预置型底胶(no flow underfill),较好为热固性材料。第一层140亦可包含一填充物以将其热膨胀系数降至近似于集成电路芯片102的热膨胀系数(集成电路芯片102的热膨胀系数为3ppm/℃~5ppm/℃)。
在图1所示的实施例中,软焊料凸块110的形成可使用晶圆上凸块生长制程(bump-on-wafer process)或基板上凸块生长制程(bump-on-substrate process)。在某些实施例中软焊料凸块110是形成于用以形成集成电路芯片102的晶圆上,其中是使用光刻制程来曝露第一接触垫106,而将第一凸块下金属层112形成于第一接触垫106上,然后将软焊料凸块110与晶圆上的集成电路芯片102结合。在其他实施例中,是于形成第二层130之前或之后,将软焊料凸块110形成于基板104。
图1所示的半导体装置100未包含基板104的软焊料凸块。当基板104为覆晶封装体的封装基板时,会如图2~图5所示,将多个软焊料凸块粘着于基板的底部;当基板104为一印刷电路板时,集成电路芯片102是直接固定于其上,其外观便如图1所示,基板104的底部不含任何软焊料凸块;同样地,当半导体装置100为一接点栅阵列(land grid array;LGA)的芯片尺寸封装(chipscale package;CSP)的封装体时,其基板104的下平面包含多个接触垫,其底部并不含软焊料凸块。虽然图1的半导体装置100是将集成电路芯片102直接固定在基板104,而在基板104的底部并不含软焊料凸块110;而图2~图5所示的半导体装置200、300、400与500则分别包含软焊料凸块224、324、424与524,但是图1~图5中所示的实施例皆可使用覆晶封装体的技术,或以覆晶的技术直接将芯片固定在印刷电路板的技术。
图2为一剖面图,是显示本发明第二实施例的半导体装置200的右侧。在图2中,基板204为一封装基板其内具有导电迹线(trace)与介层窗(via),并具有多个软焊料凸块224,用以连接一印刷电路板(未绘示)。
在图2中与图1对应的元件,除了另有标示的之外,其元件符号在数值上较图1所示多了100的,是分别代表与图1对应的等效元件,其相关叙述可参考图1所述而不重复叙述,如集成电路芯片202、介电层202d、基板204、第一接触垫206及第二接触垫216、保护层208、防焊层218、软焊料凸块210、第一凸块下金属层212及第二凸块下金属层222。
图2所示的半导体装置200与图1所示的半导体装置100的相异之处在于多层式的底胶层225的形成方法与多层式的底胶层125不同。多层式的底胶层225的形成是通过将第一层232形成于用以制造集成电路芯片202的晶圆上,将第一层232形成于上述晶圆上的方法包含印刷法、旋涂法或点胶法,其材质可以是任何适于图1所示的第一层140的材质,而不再重复叙述。例如,第一层232可包含预置型底胶、模封材料或聚酰亚胺,其热膨胀系数小于10ppm/℃,较好为5ppm/℃~9ppm/℃。第一层232是形成于集成电路芯片202上,因此在第一层232的形成之后再将软焊料凸块210形成于集成电路芯片202的第一凸块下金属层212上。
第二层242的形成是用以填入第一层232与基板204之间的空隙,其形成方法包含点胶法例如真空点胶法,其材质可包含任何适于形成图1所示的第二层130的材质,而不再重复叙述。第二层242的热膨胀系数较好为大于10ppm/℃,更好为10ppm/℃~16ppm/℃。
由于图2所示的实施例是将第一层232的材料以印刷法或旋涂法置于集成电路芯片202上,该制程可为晶圆级的制程,而不需逐一将第一层232形成于每个集成电路芯片202上。
图3为一剖面图,是显示本发明第三实施例的半导体装置300的右侧。在图3中,基板304为一封装基板其内具有导电迹线(trace)与介层窗(via),并具有多个软焊料凸块324,用以连接一印刷电路板(未绘示)。
在图3中与图1对应的元件,除了另有标示的之外,其元件符号在数值上较图1所示多了200的,是分别代表与图1对应的等效元件,其相关叙述可参考图1所述而不重复叙述,如集成电路芯片302、介电层302d、基板304、第一接触垫306及第二接触垫316、保护层308、防焊层318、软焊料凸块310、第一凸块下金属层312及第二凸块下金属层322。软焊料凸块324则与图2所示的软焊料凸块224相同。
半导体装置300的多层式的底胶层325包含一第一层333与第二层(或缓冲层)343。第一层333为邻接基板304的底胶层,其厚度小于集成电路芯片302与基板304之间的第一间隙的尺寸;第二层343则与集成电路芯片302接触,其填入集成电路芯片302与第一层333之间的第二间隙,其是由一模封材料或其他封胶材料所形成,将集成电路芯片302封入其中,其热膨胀系数小于第一层333的热膨胀系数。第二层343的热膨胀系数较好为小于10ppm/℃,而第一层333的热膨胀系数较好为大于10ppm/℃。
第一层333的材质可以是任何适于图1所示的第一层140的材质,而不再重复叙述。第一层333的形成可再将集成电路芯片302粘着于基板304之后,再将其置于基板304上。
第二层(或缓冲层)343包含一模封材料(moldingcompound)、聚酰亚胺或其他热膨胀系数低于10ppm/℃的封胶材料,较好为热膨胀系数5ppm/℃~9ppm/℃的模封材料,其形成可通过任何的封胶步骤,较好为包含一真空步骤,以将其驱入集成电路芯片302与第一层333之间的第二间隙内,并消除其内的气泡或空孔。因此,与图1所示的半导体装置100比较,半导体装置100尚需另一封胶的制程将集成电路芯片102封入其中;而用以形成图3所示的半导体装置300的方法则节省了此该步骤(图1并未绘示其封胶层)。
图4为一剖面图,是显示本发明第四实施例的半导体装置400的右侧。在图4中,多层式的底胶层425包含第一层444a与第二层444b,二者具有浓度相异的填充物粒子450。
在图4中与图1对应的元件,除了另有标示的之外,其元件符号在数值上较图1所示多了300的,是分别代表与图1对应的等效元件,其相关叙述可参考图1所述而不重复叙述,如集成电路芯片402、介电层402d、基板404、第一接触垫406及第二接触垫416、保护层408、防焊层418、软焊料凸块410、第一凸块下金属层412及第二凸块下金属层422。软焊料凸块424则与图2所示的软焊料凸块224相同。
半导体装置400的形成方法,包含通过位于集成电路芯片402与基板404之间的软焊料凸块410,将集成电路芯片402与基板404结合;一填充物粒子450是混入一封胶材料444中而形成一混合物,然后以点胶的方法使该混合物实质上填入集成电路芯片402与基板404之间的空隙,点胶之后至少使填充物粒子450部分沉淀;使填充物粒子450部分沉淀后,对封胶材料444进行固化处理。
通常填充物粒子450的热膨胀系数是小于封胶材料444的热膨胀系数,因此为了使靠近集成电路芯片402之处具有较小的热膨胀系数,填充物粒子450在上述空隙内的沉淀之处应靠近集成电路芯片402、而远离基板404,其达成可通过旋转集成电路芯片402与基板404,使基板404位于集成电路芯片402上方,因此通过重力而使填充物粒子450往集成电路芯片402的方向沉淀。其他使填充物粒子450沉淀至靠近集成电路芯片402之处的方法例如为离心法(centrifuging)。
填充物粒子450可具有大体相同的尺寸,如图4所示;亦可以具有二种或二种以上的尺寸,如图5所示。
请参考图4,根据封胶材料444的黏度、填充物粒子450在封胶材料444中的浮力及可使用的沉淀时间,可使填充物粒子450部分沉淀或完全沉淀。如图4所例示,是使填充物粒子450部分沉淀,因此填充物粒子450在封胶材料444中的分布密度会实质上连续性地由靠近基板404之处的零,上升至靠近集成电路芯片402之处的最大值。一虚拟的面(如图4中的虚线)将多层式的底胶层425分为二层,即为第一层444a与第二层444b,其中第一层444a是与集成电路芯片402邻接,其具有填充物粒子450的第一浓度值;第二层444b是与基板404邻接,具有填充物粒子450的第二浓度值,其异于上述第一浓度值。在某些实施例中,上述第二浓度值是实质上小于上述第一浓度值。
在一实施例中,集成电路芯片402与基板404之间的间隔内的填充物粒子450的分布,是具有一浓度梯度。在靠近集成电路芯片402之处具有较大的填充物粒子浓度,而在靠近基板404之处则具有较小的填充物粒子浓度。因此通过上述填充物粒子450在封胶材料444内的浓度梯度,在靠近集成电路芯片402之处的多层式的底胶层425具有较低的热膨胀系数;在靠近基板404之处的填充物粒子450具有较高的热膨胀系数。
在某些实施例中,上述第二浓度值是实质上为零。在图4所示的例子中,在虚线以下的填充物粒子450的浓度(第二浓度)趋近于零;而如果其虚线再稍向下移,则上述第二浓度则为零。
图4所示的实施例中,是得以通过单一的底胶点胶的步骤,来形成具有热膨胀系数相异的二层结构的多层式的底胶层425,而不需要以印刷法、旋涂法或点胶法等来形成第二底胶层。
图5为一剖面图,是显示本发明第五实施例的半导体装置500的右侧。在图5中,多层式的底胶层525是具有不同的填充物粒子。
在图5中与图1对应的元件,除了另有标示的之外,其元件符号在数值上较图1所示多了400的,是分别代表与图1对应的等效元件,其相关叙述可参考图1所述而不重复叙述,如集成电路芯片502、介电层502d、基板504、第一接触垫506及第二接触垫516、保护层508、防焊层518、软焊料凸块510、第一凸块下金属层512及第二凸块下金属层522。软焊料凸块524则与图2所示的软焊料凸块224相同。
在图5中,多层式的底胶层525中的填充物包含第一填充物粒子550与第二填充物粒子555,第一填充物粒子550的尺寸大于第二填充物粒子555的尺寸。在本实施例中,是使第一填充物粒子550与第二填充物粒子555沉淀而形成一第一层545a与一第二层545b,其中第一层545a中的第二填充物粒子555是位于第一填充物粒子550的间隙,而具有第二填充物粒子555的第一浓度;第二层545b中的第二填充物粒子555是位于第一填充物粒子550的间隙,而具有第二填充物粒子555的第二浓度。
上述第二浓度实质上小于上述第一浓度。在图5中,邻接基板504的第二层545b中的第二填充物粒子555(较小)的第二浓度实质上为零。在其他实施例中,邻接基板504的第二层545b中的第二填充物粒子555(较小)的第二浓度不为零,而是实质上小于第一层545a中的第二填充物粒子555的第一浓度。
在图5所示的实施例中,是使第一填充物粒子550与第二填充物粒子555完全沉淀。实质上所有的第二填充物粒子555是靠近集成电路芯片502,而使多层式的底胶层525的热膨胀系数的分布呈现阶梯函数的变化。在多层式的底胶层525中,第一层545a内的第一填充物粒子550与第二填充物粒子555的组合密度,实质上大于第二层545b内的第一填充物粒子550与第二填充物粒子555的组合密度。因此,具有较大的第一填充物粒子550与较小的第二填充物粒子555的第一层545a,具有较小的热膨胀系数;而仅具有较大的第一填充物粒子550的第二层545b,其热膨胀系数则相对较大。
虽然图5中是显示第一填充物粒子550的分布延伸至基板504;而在其他实施例中,最靠近基板504的第一填充物粒子550与基板504之间,可具有一实质的间隔,而将多层式的底胶层525分为三层,其中的第一层具有浓度相对上较高的较小的第二填充物粒子555,分布于较大的第一填充物粒子550的间隙;第二层则具有浓度相对上较低或实质上为零的较小的第二填充物粒子555,分布于较大的第一填充物粒子550的间隙;第三层中,则实质上不具第一填充物粒子550与第二填充物粒子555。
在一实施例中,分布于集成电路芯片502与基板504之间的第一填充物粒子550与第二填充物粒子555的组合浓度,是具有一浓度梯度。在靠近集成电路芯片502之处具有较高的填充物粒子浓度,在靠近基板504处具有较低的填充物粒子浓度。因此,上述浓度梯度是使靠近集成电路芯片502之处的多层式的底胶层525,具有较低的热膨胀系数;而靠近基板504之处的多层式的底胶层525,具有较高的热膨胀系数。
虽然图5中仅显示二种不同尺寸的填充物粒子,但是在其他实施例中,其可包含三种、四种或更多种的填充物粒子。
多层式的底胶层525的形成方法是类似于图4所示的多层式的底胶层425,其中将底胶材料545与第一填充物粒子550、第二填充物粒子555混合,而形成一混合物;再以点胶法将上述混合物分布于集成电路芯片502与基板504之间;然后再使第一填充物粒子550与第二填充物粒子555至少部分沉淀;在沉淀之后,对底胶材料545进行固化(curing)处理。较好为使第一填充物粒子550与第二填充物粒子555能够完全沉淀,而具有较宽的沉淀时间选择性,如此能够较准确地预测各层中第一填充物粒子550与第二填充物粒子555的浓度。亦即,一旦使第一填充物粒子550与第二填充物粒子555完全沉淀,第一层545a及第二层545b各层中的填充物粒子的浓度就不会有变化,因此就不需精确地控制沉淀时间来达成底胶材料内特定的填充物粒子浓度。如图5所示,通过将较小的第二填充物粒子555填于较大的第一填充物粒子550之间的间隙中,可达成底胶材料内不同的填充物粒子的组合密度,而能够形成具有不同的热膨胀系数的多层结构。
图5所示的实施例中,是得以通过单一的底胶点胶的步骤,来形成具有热膨胀系数相异的二或三层结构的多层式的底胶层525。
以上所述仅为本发明较佳实施例,然其并非用以限定本发明的范围,任何熟悉本项技术的人员,在不脱离本发明的精神和范围内,可在此基础上做进一步的改进和变化,因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
附图中符号的简单说明如下:
100、200、300、400、500:半导体装置
102、202、302、402、502:集成电路芯片
102d、202d、302d、402d、502d:介电层
104、204、304.404、504:基板
108、208、308、408、508:保护层
118、218、318、418、518:防焊层
110、210、310、224、324、410、424、510、524:软焊料凸块
106、206、306、406、506:第一接触垫
116、216、316、416、516:第二接触垫
112、212、312、412、512:第一凸块下金属层
122、222、322、422、522:第二凸块下金属层
125、225、325、425、525:多层式的底胶层
140、232、333、444a、545a:第一层
130、242、343、444b、545b:第二层
444、545:底胶材料
450:填充物粒子
550:第一填充物粒子
555:第二填充物粒子
Claims (18)
1.一种半导体装置,其特征在于,该半导体装置包含:
一集成电路芯片,其具有至少一介电层,该集成电路芯片是通过介于该集成电路芯片与一封装基板或印刷电路板之间的多个软焊料凸块,与该封装基板或印刷电路板结合;
一底胶层位于该集成电路芯片与该封装基板或印刷电路板之间;以及
一缓冲层,位于该底胶层与该集成电路芯片之间。
2.根据权利要求1所述的半导体装置,其特征在于,该缓冲层的热膨胀系数小于该底胶层的热膨胀系数。
3.根据权利要求1所述的半导体装置,其特征在于,该缓冲层的热膨胀系数小于10ppm/℃、该底胶层的热膨胀系数大于10ppm/℃。
4.根据权利要求1所述的半导体装置,其特征在于,该缓冲层将该集成电路芯片封于其中。
5.根据权利要求1所述的半导体装置,其特征在于,该缓冲层包含一封胶材料,该封胶材料包含一模封材料。
6.一种半导体装置,其特征在于,该半导体装置包含:
一集成电路芯片,其具有至少一介电层;
一封装基板或印刷电路板;
多个软焊料凸块,介于该集成电路芯片与该封装基板或印刷电路板之间;以及
一多层式的底胶层位于该集成电路芯片与该封装基板或印刷电路板之间。
7.根据权利要求6所述的半导体装置,其特征在于,该多层式的底胶层包含一第一层与一第二层,该第一层与该第二层具有实质上不同的热膨胀系数。
8.根据权利要求7所述的半导体装置,其特征在于,该第一层是相邻于该集成电路芯片,其热膨胀系数小于10ppm/℃;该第二层是相邻于该封装基板或印刷电路板,其热膨胀系数大于10ppm/℃。
9.根据权利要求6所述的半导体装置,其特征在于,该多层式的底胶层具有一底胶材料与一渐变的填充物材料结构。
10.根据权利要求9所述的半导体装置,其特征在于,该渐变的填充物材料结构中,相邻于该集成电路芯片的填充物的尺寸小于相邻于该封装基板或印刷电路板的填充物的尺寸。
11.根据权利要求9所述的半导体装置,其特征在于,该渐变的填充物材料结构具有一填充物浓度梯度,且相邻于该集成电路芯片的填充物浓度与相邻于该封装基板或印刷电路板的填充物浓度之间,具有一浓度差距。
12.根据权利要求6所述的半导体装置,其特征在于,该多层式的底胶层包含一第一层与一第二层,该第一层是相邻于该集成电路芯片、该第二层是相邻于该封装基板或印刷电路板,该第一层的填充物浓度大于该第二层的填充物浓度。
13.根据权利要求6所述的半导体装置,其特征在于,该多层式的底胶层包含:
一第一层,其为一底胶材料并接触该封装基板或印刷电路板,该第一层的厚度小于该集成电路芯片与该封装基板或印刷电路板之间的一第一间隔;以及
一第二层,接触该集成电路芯片、并填入该集成电路芯片与该第一层之间的一第二间隔,该第二层是由一模封材料所形成,将该集成电路芯片封入其中。
14.一种半导体装置的形成方法,其特征在于,该半导体装置的形成方法包含:
通过介于一集成电路芯片与一封装基板或印刷电路板之间的多个软焊料凸块,将该集成电路芯片与该封装基板或印刷电路板结合,该集成电路芯片具有至少一介电层;以及
形成一多层式的底胶层于该集成电路芯片与该封装基板或印刷电路板之间。
15.根据权利要求14所述的半导体装置的形成方法,其特征在于,该多层式的底胶层具有一底胶材料与一填充物材料,该填充物材料包含一第一填充物粒子与一第二填充物粒子,该第一填充物粒子的尺寸大于该第二填充物粒子的尺寸,而形成该多层式的底胶层的方法包含:
将该底胶材料、该第一填充物粒子与该第二填充物粒子混合,而形成一混合物;以及
将该混合物加入该集成电路芯片与该封装基板或印刷电路板之间。
16.根据权利要求14所述的半导体装置的形成方法,其特征在于,更包含:
形成一第一层,其为一底胶材料并使其接触该封装基板或印刷电路板,该第一层的厚度小于该集成电路芯片与该封装基板或印刷电路板之间的一第一间隔;以及
加入一模封材料而形成一第二层,是使该第二层填入该集成电路芯片与该第一层之间的一第二间隔,将该集成电路芯片封入其中。
17.一种半导体装置的形成方法,其特征在于,该半导体装置的形成方法包含:
通过介于一集成电路芯片与一封装基板或印刷电路板之间的多个软焊料凸块,将该集成电路芯片与该封装基板或印刷电路板结合;
将一填充物材料混入一底胶材料,而形成一混合物;
加入该混合物,使其实质上填入该集成电路芯片与该封装基板或印刷电路板之间的间隔;
在加入该混合物之后,使该填充物材料至少部分沉淀;以及
在该填充物材料至少部分沉淀之后,固化该底胶材料。
18.根据权利要求17所述的半导体装置的形成方法,其特征在于,该填充物材料包含一第一填充物粒子与一第二填充物粒子,该第一填充物粒子的尺寸大于该第二填充物粒子的尺寸。
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CN110854111A (zh) * | 2019-11-25 | 2020-02-28 | 维沃移动通信有限公司 | 封装组件、电子设备及封装方法 |
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US20100093135A1 (en) | 2010-04-15 |
US20070238220A1 (en) | 2007-10-11 |
US7656042B2 (en) | 2010-02-02 |
TWI323505B (en) | 2010-04-11 |
TW200737444A (en) | 2007-10-01 |
US7846769B2 (en) | 2010-12-07 |
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