CN102812542A - 用于改进结合强度的裸片的表面制备 - Google Patents
用于改进结合强度的裸片的表面制备 Download PDFInfo
- Publication number
- CN102812542A CN102812542A CN2011800124776A CN201180012477A CN102812542A CN 102812542 A CN102812542 A CN 102812542A CN 2011800124776 A CN2011800124776 A CN 2011800124776A CN 201180012477 A CN201180012477 A CN 201180012477A CN 102812542 A CN102812542 A CN 102812542A
- Authority
- CN
- China
- Prior art keywords
- passivation layer
- electronic packaging
- mating surface
- coating material
- package substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 238000002161 passivation Methods 0.000 claims abstract description 96
- 239000000463 material Substances 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000011248 coating agent Substances 0.000 claims abstract description 53
- 238000000576 coating method Methods 0.000 claims abstract description 53
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000007788 roughening Methods 0.000 claims abstract description 32
- 230000008569 process Effects 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 238000004100 electronic packaging Methods 0.000 claims description 45
- 230000013011 mating Effects 0.000 claims description 36
- 238000005516 engineering process Methods 0.000 claims description 22
- 230000002209 hydrophobic effect Effects 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 238000012856 packing Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 abstract description 5
- 239000000126 substance Substances 0.000 abstract description 4
- 238000001311 chemical methods and process Methods 0.000 abstract 1
- 238000010297 mechanical methods and process Methods 0.000 abstract 1
- 230000005226 mechanical processes and functions Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 62
- 229910052751 metal Inorganic materials 0.000 description 21
- 239000002184 metal Substances 0.000 description 21
- 230000008878 coupling Effects 0.000 description 10
- 238000010168 coupling process Methods 0.000 description 10
- 238000005859 coupling reaction Methods 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 238000004891 communication Methods 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 239000002202 Polyethylene glycol Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920001223 polyethylene glycol Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005352 clarification Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05666—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
本发明提供一种用于改进电子封装系统中的粘合度的表面制备方法。改进所述电子封装系统中的粘合度的所述方法包含在结合表面上沉积钝化层,以及使所述钝化层的至少一部分粗糙化。将涂覆材料沉积在所述钝化层上。所述结合表面可为半导体或封装衬底的一部分。所述粗糙化工艺可通过化学或机械工艺执行。在另一实施例中,电子封装系统包含半导体或封装衬底的结合表面。将钝化层沉积在所述结合表面上,且使所述钝化层的一部分粗糙化以改进粘合度。将涂覆材料沉积在所述钝化层的所述粗糙化部分上。
Description
技术领域
本发明大体涉及电子封装,且特定来说涉及用于改进电子封装系统中的粘合度的表面制备方法。
背景技术
在电子封装中,可将一个或一个以上裸片耦合在一起或耦合到有机衬底以形成封装。电子封装的可靠性可归因于翘曲和其它物理缺陷而受到负面影响。对于薄裸片和精细间距倒装芯片应用来说尤其如此,在这些应用中,可能难以在制造过程中将一裸片粘合或耦合到另一裸片或封装衬底。薄裸片(例如)可具有小于100μm的厚度,且封装衬底可具有小于300μm的厚度。
当将一裸片耦合到另一裸片或封装衬底时,翘曲可能使裸片到裸片的附接或裸片到衬底的附接断开。在一些电子封装中,裸片和/或衬底之间使用的底部填充材料的类型可影响其间的结合强度。在其它电子封装中,需要匹配或协调两个裸片之间的热膨胀系数(例如)以避免翘曲。然而,这在裸片到衬底系统中常常可能难以实现。其它解决方案包含使用与所结合系统的热膨胀系数对应或匹配的不同类型的底部填充材料。然而,匹配热膨胀系数可能归因于不同材料的特性而难以实现。
因此,将需要改进裸片到裸片的附接、裸片到衬底的附接或衬底到衬底的附接之间的结合强度。
发明内容
为更完整地理解本发明,现参考以下详细描述和附图。
在一示范性实施例中,提供一种用于封装集成电路的方法。所述方法包含在第一结合表面上沉积第一钝化层,以及使第一钝化层的至少一部分粗糙化。第一涂覆材料可沉积在第一钝化物上,且在一些情况下,还可使第一涂覆材料的一部分粗糙化。粗糙化工艺可为例如等离子体轰击或蚀刻等化学或机械工艺。第一涂覆材料可为疏水或亲水的。
所述方法还可包含将第一结合表面粘合到第二结合表面。将第二钝化层沉积在第二结合表面上,且使第二钝化层的至少一部分粗糙化。第二涂覆材料可沉积在第二钝化层上。另外,所述方法可进一步包含在第一钝化层与第二钝化层之间沉积底部填充材料。底部填充材料可包括多个层,使得一个层可安置在第一钝化层附近或与之接触,且不同层可安置在第二钝化层附近或与之接触。底部填充材料和/或涂覆材料可经选择以实现其之间的最大粘合度。
在另一实施例中,提供一种电子封装,其包含第一半导体或封装衬底的第一结合表面。第一钝化层安置在第一结合表面上,且第一涂覆材料安置在第一钝化层上。第一钝化层或第一涂覆材料的至少一部分经粗糙化以改进粘合度。第一涂覆材料可为亲水或疏水的。在第一结合表面为半导体的一部分的情况下,半导体的厚度小于100μm。在第一结合表面为封装衬底的一部分的情况下,衬底的厚度小于300μm。
电子封装还可包含由半导体或封装衬底形成的第二结合表面。第二钝化层可安置在第二钝化层上,且第二涂覆材料可安置在第二钝化层上。第二钝化层或第二涂覆材料的一部分经粗糙化以改进粘合度。单一或多层底部填充材料可安置在第一与第二钝化层之间。
在不同实施例中,提供一种电子封装系统。所述系统包含:第一结合表面,其具有安置在其上的第一钝化层;以及第二结合表面,其具有安置在其上的第二钝化层。并且,涂覆材料安置在第一和第二钝化层上。第一钝化层、第二钝化层和涂覆材料中的一者的一部分经粗糙化以改进粘合度。所述系统可进一步包含安置在第一与第二钝化层之间的单一或多层底部填充材料。涂覆材料可为疏水或亲水的。
在另一示范性实施例中,提供一种电子封装中的集成电路。所述集成电路包括半导体或封装衬底的结合表面。所述电路进一步包含用于保护半导体或封装衬底的结合表面的装置,以及用于将电路结合到另一表面的装置。所述用于结合的装置可沉积在所述用于保护的装置上。所述用于保护的装置或用于结合的装置的一部分经粗糙化以改进粘合度。所述用于结合的装置可包含疏水或亲水材料。另外,所述用于保护的装置安置在结合表面上。
上述实施例有利地改进所结合系统之间的结合强度。特定来说,薄裸片和衬底可较好地彼此粘合。另一优点是可通过遵循现有制造方法实现改进的表面粘合度。可通过等离子体轰击或蚀刻工艺来使钝化层或涂覆材料粗糙化。用于实现裸片到裸片的附接、裸片到衬底的附接或衬底到衬底的附接的现有技术方法一直不能实现薄裸片与衬底之间的充分粘合。因此,本发明克服现有技术的缺点,且改进薄裸片与封装衬底之间的粘合度。
附图说明
图1是电子封装的横截面图;
图2是图1的电子封装中的裸片到裸片耦合的横截面图;
图3是沿着图2的裸片到裸片耦合的表面的经粗糙化钝化层的一部分的横截面图;
图4是用于改进电子封装中的粘合度的表面制备方法的流程图;以及
图5是展示示范性无线通信系统的方框图,在所述无线通信系统中可有利地采用具有改进的结合强度的电子封装系统。
具体实施方式
参看图1所示的示范性实施例,电子封装100具备改进的结合强度以防止或减少翘曲。封装100包含衬底102、第一裸片104和第二裸片106。第一裸片104可称为下部或层级1裸片,且第二裸片106可称为上部或层级2裸片。可由硅、玻璃或其它半导体材料制成的衬底102可通过多个焊锡球108或倒装芯片凸块而耦合到系统主板(未图示)或另一封装衬底。同样,第一裸片104可通过凸块110(例如,微凸块、焊锡球等)或用于实现裸片到衬底的附接的任何其它装置而耦合到衬底102。还可将底部填充层122添加在第一裸片104与衬底102之间以改进封装可靠性。同样,底部填充材料124可安置在第一与第二裸片之间。
在第一裸片104的前表面附近,可形成前道工序(FEOL)和后道工序(BEOL)区(简单展示为单一层112)。FEOL区可包含用于有源装置的若干顶部层,且BEOL区可包含多个金属层。
多个通孔120可制造在第一裸片104中。多个通孔120(其可为例如穿硅通孔)可通过最后打孔工艺(via last process)或用于形成通孔的任何其它工艺而形成。多个通孔120可用铜或其它导电材料填充。另外,一个或一个以上金属层114可安置在第一裸片104的背表面处。所述一个或一个以上金属层114可由例如铜或钛等任何导热材料形成。金属层中的至少一者可称为种子层,其将参看图4更详细描述。
第一裸片104和第二裸片106可以改进的结合强度耦合在一起。为此,可将第一裸片104的背表面上所形成的微凸块耦合到第二裸片106的前表面上所形成的微凸块。出于澄清的目的,第一裸片104的背表面(即,图1中的顶部表面)和第二裸片106的前表面(即,图1中的底部表面)朝向彼此定向。在图1中,裸片到裸片耦合200被展示为矩形形状116,但在图2和3中,更详细说明耦合200。
第二裸片106也可包含一个或一个以上金属层118,其类似于安置在第一裸片104的背表面附近的一个或一个以上金属层114。这些金属层118中的至少一者可为用于形成微凸块的种子层,如下文将进一步详细阐释。所述一个或一个以上金属层118可由例如铜或钛等导电材料制成。第一和第二裸片可由硅或任何其它裸片材料制成。
参看图2,更详细展示裸片到裸片耦合200。如上所述,第一裸片104或层级1裸片可由硅制成,且包含延伸穿过其的多个通孔120。第一钝化层202可沉积在第一裸片104的背表面上,如图2所示。第一钝化层202可由氮化硅、氧化硅、聚酰亚胺或任何其它钝化材料制成。第一钝化层202可部分围绕由铜或其它导电材料制成的金属层204。金属层204被展示为导电性地耦合到第一裸片104中的多个通孔120中的一者。
金属层204进一步导电性地耦合到称为种子层114的另一金属层。种子层114(其为凸块下方金属化(UBM)的一部分)可由铜或钛制成。第一微凸块206由种子层114形成,且耦合到由第二裸片106形成的第二微凸块214。第一微凸块206包含例如镍层208,镍层208可耦合到第二微凸块214的另一镍层212。两个镍层208、212通过焊锡层210耦合。
第二裸片106或层级2裸片也可包含类似于上文描述的第一钝化层202的第二钝化层216。第二钝化层216可围绕或接触由铜或其它导电材料制成的第二金属层218。第二金属218还可导电性地耦合到形成第二微凸块214的种子层118。由第一裸片104形成的第一微凸块206和由第二裸片106形成的第二微凸块214可由铜或其它导电材料制成。如上所述,底部填充材料124安置在第一与第二裸片之间以改进电子封装的可靠性并保护界面接点。
电子封装100以改进的结合强度制造于至少第一裸片104与第二裸片106之间。第一裸片104与封装衬底102也可通过类似方式以改进的结合强度耦合。尽管未图示,但在另一实施例中,衬底到衬底的附接可以如本文描述的改进的粘合度耦合。参看图3,展示第一钝化层202与底部填充材料124之间的界面的增强视图。为实现改进的结合强度,通过湿式或干式工艺(例如,化学或机械工艺)使第一钝化层202的表面302粗糙化。举例来说,粗糙化工艺可包含等离子体轰击、喷砂、蚀刻或其它已知工艺。
涂覆材料304沉积在第一钝化层202的粗糙化表面302上以进一步增加结合强度。涂覆材料304可为疏水材料(例如,环氧树脂、氮化物等)或亲水材料(例如,聚乙二醇)。可通过选择最符合裸片之间使用的底部填充材料124的类型的涂覆材料304来增加结合强度。换句话说,如果底部填充材料124将较好地符合亲水材料,那么当涂覆材料304为亲水的,第一与第二裸片之间的结合强度增加。在另一实施例中,涂覆材料304可沉积在钝化层上,且涂覆材料304的外表面可经粗糙化以实现所要结合强度。
在图2的实施例中,底部填充材料124可为单层或多层底部填充。换句话说,安置在第一钝化层202附近的底部填充材料可不同于安置在第二钝化层216附近的底部填充材料。如此,为改进第一与第二裸片之间的结合强度,沉积在第一钝化层202上的涂覆材料304可不同于沉积在第二钝化层216上的涂覆材料304的类型。作为非限制性实例,沉积在第一钝化层202上的涂覆材料304可为疏水材料,而沉积在第二钝化层216上的涂覆材料304可为亲水材料。沉积在钝化层上的涂覆材料的类型有利地与底部填充材料对应,以实现两个裸片之间的较大结合强度。
在不同实施例中,提供一种制造具有改进的粘合度和增加的结合强度的电子封装的方法400。参看图4,方法400包含制备晶片,将从所述晶片形成多个裸片。在方框402和404中,举例来说,制备晶片包含前道工序(FEOL)处理和后道工序(BEOL)处理。在FEOL处理(其为已知的)期间,晶体管和其它装置形成在晶片上。BEOL处理(其也是已知的)包含形成金属互连线以形成电路,且使所述线与电介质材料隔离。将晶片(例如)安装在例如塑料带等载体上。
在晶片上于将形成微凸块的位置处形成热接点。为此,在方框406中,将钝化物沉积在晶片的将制造微凸块的前或后表面上。钝化物可充当裸片的保护层。举例来说,钝化物保护裸片使其免受例如结合等制造工艺期间的碎屑影响。材料可旋涂、喷涂、化学气相沉积(CVD)或物理气相沉积(PVD)在裸片上。
一旦沉积钝化物,就在方框408中将涂覆材料沉积到钝化层上。涂覆材料可为亲水(例如,聚乙二醇)或疏水的(例如、环氧树脂、氮化物等)。所沉积的涂覆材料的类型可取决于所使用的底部填充材料的类型。或者,底部填充材料可包含多个层,使得所使用的底部填充层的类型基于沉积在钝化层上的涂覆材料的类型来选择。涂覆材料可旋涂到钝化层。例如分子气相沉积(MVD)等其它沉积工艺可能用于将涂覆材料沉积到钝化层。
在方框410中,对钝化层或涂覆材料的外表面的至少一部分执行粗糙化工艺。粗糙化工艺可为任何干式或湿式工艺,例如化学或机械工艺。在一个实施例中,举例来说,粗糙化工艺可通过等离子体轰击实现。在不同实施例中,粗糙化工艺可通过喷砂实现。在另一实施例中,粗糙化工艺可通过蚀刻执行。
一旦钝化层或涂覆材料的表面经粗糙化,就执行方框412和414。为此,在钝化物中形成开口,使得可在下伏晶片与不久要形成的微凸块之间制造热接点。换句话说,钝化物为热绝缘且电绝缘的,使得当在其中形成开口时,在裸片与微凸块(一旦形成)之间提供导电路径。如果钝化物为光敏的,那么使用光刻形成钝化物中的开口。在此情况下,将掩模放置在晶片的上面将制造微凸块的表面上,且将紫外光或强光导向掩模上。接着将经掩蔽的晶片放置到化学溶液(例如,显影剂)中以冲洗掉或移除曝露于光的区域。然而,如果钝化物不是光敏的,那么旋涂或层压光敏抗蚀剂材料,且执行类似的光刻工艺。
在方框416中,通过物理气相沉积(PVD)工艺将薄“种子”金属层沉积在晶片上。在此工艺中,例如通过例如电子或离子束等高能量源来轰击由“种子”金属组成的目标。如此,来自目标表面的原子被驱逐或汽化并沉积到晶片表面上。种子层(其例如在图2中展示为制造于第一裸片104的背表面上的金属层114和制造于第二裸片106的前表面上的金属层118)充当镀敷工艺期间的导电层,且可具有小于1微米的厚度。种子金属可例如为铜或钛。其它金属也可用于形成种子层。
参看方框418,光致抗蚀剂通过旋涂或化学气相沉积(CVD)工艺而沉积在晶片上。晶片接着曝露于紫外光或强光的图案。在此过程期间,建立不久要形成的微凸块的横截面或图案。如此,如果晶片上的区域暴露于穿过掩模的强光的圆形图案,那么正在所述区域中形成的微凸块将具有圆形横截面。掩模可改变正曝露于晶片上的所述区域的紫外光或强光的图案,使得微凸块可具有任何形状的横截面。这在以下情况下尤其重要:裸片上的可用区域具有特定形状,使得形成在此区域中的微凸块可最大化以实现裸片和/或衬底之间的所要粘合度(当将裸片附接到封装衬底或将一封装衬底附接到另一封装衬底时,此过程是类似的)。举例来说,如果裸片上的可用区域为大体环形,那么紫外光或强光的经掩蔽图案可为大体环形以形成具有特定横截面的一个或一个以上微凸块,用于占据裸片上的大体环形区域。
在方框420中,将光致抗蚀剂浸渍到电解浴中,控制电流和时间两者。铜或任何其它热传导电解金属可以电解方式沉积在具有曝露的种子层的那些区域中。如此,一个或一个以上微凸块与晶片一体式形成。在正形成单一微凸块的情况中,可通过改变光致抗蚀剂浸渍到电解浴中的时间量来改变微凸块的大小。
还是在方框420中,可剥离光致抗蚀剂。一种剥离光致抗蚀剂的方式是通过在干式工艺中使用等离子体轰击。或者,在湿式工艺中,可通过用化学方法改变抗蚀剂来溶解剩余抗蚀剂,使得其不再粘合到晶片。在其它实施例中,可将抗蚀剂从晶片剥除。在光致抗蚀剂较厚的实施例中,等离子体轰击或剥除方法是优选的。现可蚀刻掉种子层。另外,通过等离子体轰击移除少量材料。
一旦在晶片的前或后表面上形成所述一个或一个以上微凸块,在方框422中,将晶片切割或分割为多个裸片。单一裸片可(例如)通过将裸片附接到衬底而集成到电封装中。第二裸片可安装到第一裸片上(例如,图2中的实施例),且额外裸片可经堆叠以形成多裸片封装。一旦集成到封装中,就可完成封装后端组装以形成电封装。
可实行类似工艺以将裸片耦合到衬底或将一衬底耦合到另一衬底。
通过在方框410中使钝化层或涂覆材料的表面粗糙化来增加电子封装的结合强度。特定来说,在裸片到裸片配置中,裸片与底部填充或环氧树脂材料之间的粘合度有所改进。另外,当基于底部填充材料的类型来选择涂覆材料的类型(例如,亲水或疏水)时,反之亦然,涂覆材料进一步增加裸片(或衬底)与底部填充材料之间的结合强度。
上述实施例当用于将薄裸片或精细间距倒装芯片结合到另一裸片或衬底时尤其有利。薄裸片(例如)可具有小于100μm的厚度,且封装衬底可具有小于300μm的厚度。包含上文在背景技术中描述的解决方案的已知解决方案一直不能实现此类薄裸片与封装衬底之间的理想粘合度。然而,通过执行上文揭示的表面制备方法,薄裸片和/或衬底之间的结合强度可增加到理想水平。
图5展示示范性无线通信系统500,在无线通信系统500中,可有利地采用具有改进的结合强度的电子封装系统的实施例。出于说明的目的,图5展示三个远程单元520、530和550以及两个基站540。应认识到,典型的无线通信系统可具有更多远程单元和基站。远程单元520、530和550中的任一者可包含例如本文揭示的具有改进的结合强度的电子封装系统。图5展示从基站540到远程单元520、530和550的前向链路信号580,以及从远程单元520、530和550到基站540的反向链路信号590。
图5中,远程单元520被展示为移动电话,远程单元530被展示为便携式计算机,且远程单元550被展示为无线本地回路系统中的固定位置远程单元。举例来说,所述远程单元可为蜂窝式电话、手持式个人通信系统(PCS)单元、例如个人数据助理等便携式数据单元、音乐和/或视频播放器、娱乐单元、导航装置,或例如仪表读取设备等固定位置数据单元。尽管图5说明可包含如本文揭示的具有改进的结合强度的电子封装系统的某些示范性远程单元,但封装衬底不限于这些所说明的示范性单元。实施例可适当地用于其中需要具有改进的结合强度的电子封装系统的任何电子装置中。
虽然在上文中已揭示并入有本发明的原理的示范性实施例,但本发明不限于所揭示的实施例。事实上,本申请案希望涵盖本发明的使用其一般原理的任何变体、用途或修改。此外,本申请案希望涵盖在本发明所属的技术中已知或常规实务内且落在所附权利要求书的限制内的与本发明的此类偏离。
Claims (39)
1.一种用于封装集成电路的方法,其包括:
在第一结合表面上沉积第一钝化层;
使所述第一钝化层的至少一部分粗糙化;以及
将第一涂覆材料沉积在所述第一钝化层上。
2.根据权利要求1所述的方法,其进一步包括使所述第一涂覆材料的至少一部分粗糙化。
3.根据权利要求1所述的方法,其中所述使至少一部分粗糙化是化学或机械工艺。
4.根据权利要求3所述的方法,其中所述使至少一部分粗糙化包括等离子体轰击或蚀刻工艺。
5.根据权利要求1所述的方法,其中所述第一涂覆材料为疏水或亲水的。
6.根据权利要求1所述的方法,其进一步包括将所述第一结合表面粘合到第二结合表面。
7.根据权利要求6所述的方法,其进一步包括:
将第二钝化层沉积在所述第二结合表面上;
使所述第二钝化层的至少一部分粗糙化;以及
将第二涂覆材料沉积在所述第二钝化层上。
8.根据权利要求7所述的方法,其进一步包括在所述第一钝化层与第二钝化层之间沉积底部填充材料。
9.根据权利要求8所述的方法,其中所述沉积底部填充材料包括在所述第一钝化层与所述第二钝化层之间沉积多层底部填充材料。
10.根据权利要求8所述的方法,其进一步包括选择所述底部填充材料以及所述第一和第二涂覆材料以促进材料之间的粘合度。
11.根据权利要求6所述的方法,其中所述第一和第二结合表面是由半导体或封装衬底形成。
12.根据权利要求11所述的方法,其中当所述第一或第二结合表面是由半导体形成时,所述半导体具有小于100μm的厚度。
13.根据权利要求11所述的方法,其中当所述第一或第二结合表面是由封装衬底形成时,所述封装衬底具有小于300μm的厚度。
14.根据权利要求1所述的方法,其并入到选自由以下各项组成的群组的装置中:音乐播放器、视频播放器、娱乐单元、导航装置、通信装置、个人数字助理PDA、固定位置数据单元和计算机。
15.一种电子封装,其包括:
第一半导体或封装衬底的第一结合表面;
第一钝化层,其安置在所述第一结合表面上;以及
第一涂覆材料,其安置在所述第一钝化层上;
其中所述第一钝化层或所述第一涂覆材料的至少一部分经粗糙化以改进粘合度。
16.根据权利要求15所述的电子封装,其中所述第一涂覆材料为亲水或疏水的。
17.根据权利要求15所述的电子封装,其中当所述第一结合表面为半导体的一部分时,所述半导体的厚度小于100μm。
18.根据权利要求15所述的电子封装,其中当所述第一结合表面为封装衬底的一部分时,所述封装衬底的厚度小于300μm。
19.根据权利要求15所述的电子封装,其进一步包括:
第二结合表面,其由第二半导体或封装衬底形成;
第二钝化层,其安置在所述第二结合表面上;以及
第二涂覆材料,其安置在所述第二钝化层上;
其中所述第二钝化层或第二涂覆材料的至少一部分经粗糙化以改进粘合度。
20.根据权利要求19所述的电子封装,其进一步包括安置在所述第一钝化层与所述第二钝化层之间的底部填充材料。
21.根据权利要求20所述的电子封装,其中所述底部填充材料包括多层底部填充材料。
22.根据权利要求21所述的电子封装,其中接触所述第一钝化层的所述底部填充材料不同于接触所述第二钝化层的所述底部填充材料。
23.根据权利要求15所述的电子封装,其并入到选自由以下各项组成的群组的装置中:音乐播放器、视频播放器、娱乐单元、导航装置、通信装置、个人数字助理PDA、固定位置数据单元和计算机。
24.一种电子封装系统,其包括:
第一结合表面,其具有安置在其上的第一钝化层;
第二结合表面,其具有安置在其上的第二钝化层;
涂覆材料,其安置在所述第一钝化层和所述第二钝化层上;
其中所述第一钝化层、第二钝化层和涂覆材料之一的至少一部分经粗糙化。
25.根据权利要求24所述的电子封装系统,其进一步包括安置在所述第一与第二钝化层之间的底部填充材料。
26.根据权利要求25所述的电子封装系统,其中所述底部填充材料包括多层底部填充材料。
27.根据权利要求24所述的电子封装系统,其中安置在所述第一钝化层上的所述涂覆材料不同于安置在所述第二钝化层上的所述涂覆材料。
28.根据权利要求24所述的电子封装系统,其中所述涂覆材料为疏水或亲水的。
29.根据权利要求24所述的电子封装系统,其中所述第一结合表面是半导体或封装衬底的一部分。
30.根据权利要求29所述的电子封装系统,其中所述第二结合表面是半导体或封装衬底的一部分。
31.根据权利要求30所述的电子封装系统,其中如果所述第一或第二结合表面之一是半导体的一部分,那么所述半导体的厚度小于100μm。
32.根据权利要求30所述的电子封装系统,其中如果所述第一或第二结合表面之一是封装衬底的一部分,那么所述封装衬底的厚度小于300μm。
33.根据权利要求24所述的电子封装系统,其中所述第一钝化层或第二钝化层之一的所述部分是通过化学或机械工艺而粗糙化。
34.根据权利要求33所述的电子封装系统,其中所述工艺包括等离子体轰击或蚀刻。
35.根据权利要求24所述的电子封装系统,其并入到选自由以下各项组成的群组的装置中:音乐播放器、视频播放器、娱乐单元、导航装置、通信装置、个人数字助理PDA、固定位置数据单元和计算机。
36.一种电子封装中的集成电路,其包括:
半导体或封装衬底的结合表面;
用于保护所述半导体或封装衬底的所述结合表面的装置;
用于将所述电路结合到另一表面的装置,所述用于结合的装置沉积在所述用于保护的装置上;
其中所述用于保护的装置或所述用于结合的装置的至少一部分经粗糙化。
37.根据权利要求36所述的集成电路,其中所述用于结合的装置包括亲水或疏水材料。
38.根据权利要求36所述的集成电路,其中所述用于保护的装置安置在所述结合表面上。
39.根据权利要求36所述的集成电路,其并入到选自由以下各项组成的群组的装置中:音乐播放器、视频播放器、娱乐单元、导航装置、通信装置、个人数字助理PDA、固定位置数据单元和计算机。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/701,201 US20110193211A1 (en) | 2010-02-05 | 2010-02-05 | Surface Preparation of Die for Improved Bonding Strength |
US12/701,201 | 2010-02-05 | ||
PCT/US2011/023726 WO2011097464A1 (en) | 2010-02-05 | 2011-02-04 | Surface preparation of die for improved bonding strength |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102812542A true CN102812542A (zh) | 2012-12-05 |
CN102812542B CN102812542B (zh) | 2016-04-27 |
Family
ID=43734250
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201180012477.6A Expired - Fee Related CN102812542B (zh) | 2010-02-05 | 2011-02-04 | 用于改进结合强度的裸片的表面制备 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20110193211A1 (zh) |
EP (1) | EP2532023A1 (zh) |
JP (2) | JP5766213B2 (zh) |
KR (1) | KR101512804B1 (zh) |
CN (1) | CN102812542B (zh) |
WO (1) | WO2011097464A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106601632A (zh) * | 2015-10-14 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制造方法 |
CN107675156A (zh) * | 2017-08-14 | 2018-02-09 | 合肥市田源精铸有限公司 | 一种增强离合器壳机械性能的处理方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8525342B2 (en) * | 2010-04-12 | 2013-09-03 | Qualcomm Incorporated | Dual-side interconnected CMOS for stacked integrated circuits |
EP2701189B1 (en) * | 2012-08-24 | 2016-01-20 | Imec | Substrate, fabrication method of such a substrate, method of self-assembly of such substrates and device obtained thereof |
US8846548B2 (en) * | 2013-01-09 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post-passivation interconnect structure and methods for forming the same |
US9466547B1 (en) * | 2015-06-09 | 2016-10-11 | Globalfoundries Inc. | Passivation layer topography |
US9773741B1 (en) | 2016-08-17 | 2017-09-26 | Qualcomm Incorporated | Bondable device including a hydrophilic layer |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19634845C1 (de) * | 1996-08-28 | 1998-02-26 | Siemens Ag | Verfahren zur Optimierung der Adhäsion zwischen Preßmasse und Passivierungsschicht in einem Kunststoffchipgehäuse |
US20050127533A1 (en) * | 2003-12-10 | 2005-06-16 | Odegard Charles A. | Patterned plasma treatment to improve distribution of underfill material |
US20050212149A1 (en) * | 2001-09-14 | 2005-09-29 | Cowens Marvin W | Adhesion by plasma conditioning of semiconductor chip surfaces |
WO2006092117A1 (de) * | 2005-03-03 | 2006-09-08 | Infineon Technologies Ag | Halbleiterbauelement sowie verfahren zum herstellen eines halbleiterbauelements |
US20070108623A1 (en) * | 2005-11-11 | 2007-05-17 | Jui-Meng Jao | Chip and package structure |
CN101047154A (zh) * | 2006-03-29 | 2007-10-03 | 台湾积体电路制造股份有限公司 | 半导体装置及其形成方法 |
US20090001605A1 (en) * | 2007-06-26 | 2009-01-01 | Jong Hoon Kim | Semiconductor package and method for manufacturing the same |
US20090194890A1 (en) * | 2008-01-31 | 2009-08-06 | Knut Kahlisch | Integrated Circuit and Memory Module |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62150859A (ja) * | 1985-12-25 | 1987-07-04 | Toshiba Corp | 半導体装置 |
JPH05136298A (ja) * | 1991-11-14 | 1993-06-01 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH0870067A (ja) * | 1994-08-26 | 1996-03-12 | Nippon Steel Corp | 半導体装置 |
US6399426B1 (en) * | 1998-07-21 | 2002-06-04 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
JP4239528B2 (ja) * | 2002-09-03 | 2009-03-18 | ソニー株式会社 | 半導体装置の製造方法 |
US7247683B2 (en) * | 2004-08-05 | 2007-07-24 | Fry's Metals, Inc. | Low voiding no flow fluxing underfill for electronic devices |
JP2006332576A (ja) * | 2005-04-25 | 2006-12-07 | Matsushita Electric Works Ltd | 半導体装置およびその製造方法 |
JP2006351935A (ja) * | 2005-06-17 | 2006-12-28 | Shinko Electric Ind Co Ltd | 半導体チップ実装基板及びそれを用いた半導体装置 |
US8440272B2 (en) * | 2006-12-04 | 2013-05-14 | Megica Corporation | Method for forming post passivation Au layer with clean surface |
JP5125309B2 (ja) * | 2007-08-20 | 2013-01-23 | 株式会社デンソー | 半導体装置の製造方法 |
US8043893B2 (en) * | 2007-09-14 | 2011-10-25 | International Business Machines Corporation | Thermo-compression bonded electrical interconnect structure and method |
US7868457B2 (en) * | 2007-09-14 | 2011-01-11 | International Business Machines Corporation | Thermo-compression bonded electrical interconnect structure and method |
JP5446867B2 (ja) * | 2007-10-10 | 2014-03-19 | 日本電気株式会社 | 半導体装置 |
JP2009099597A (ja) * | 2007-10-12 | 2009-05-07 | Nec Electronics Corp | 半導体装置およびその製造方法 |
-
2010
- 2010-02-05 US US12/701,201 patent/US20110193211A1/en not_active Abandoned
-
2011
- 2011-02-04 CN CN201180012477.6A patent/CN102812542B/zh not_active Expired - Fee Related
- 2011-02-04 EP EP11703795A patent/EP2532023A1/en not_active Ceased
- 2011-02-04 KR KR1020127023149A patent/KR101512804B1/ko not_active IP Right Cessation
- 2011-02-04 JP JP2012552103A patent/JP5766213B2/ja not_active Expired - Fee Related
- 2011-02-04 WO PCT/US2011/023726 patent/WO2011097464A1/en active Application Filing
-
2015
- 2015-01-15 JP JP2015005717A patent/JP2015079995A/ja active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19634845C1 (de) * | 1996-08-28 | 1998-02-26 | Siemens Ag | Verfahren zur Optimierung der Adhäsion zwischen Preßmasse und Passivierungsschicht in einem Kunststoffchipgehäuse |
US20050212149A1 (en) * | 2001-09-14 | 2005-09-29 | Cowens Marvin W | Adhesion by plasma conditioning of semiconductor chip surfaces |
US20050127533A1 (en) * | 2003-12-10 | 2005-06-16 | Odegard Charles A. | Patterned plasma treatment to improve distribution of underfill material |
WO2006092117A1 (de) * | 2005-03-03 | 2006-09-08 | Infineon Technologies Ag | Halbleiterbauelement sowie verfahren zum herstellen eines halbleiterbauelements |
US20070108623A1 (en) * | 2005-11-11 | 2007-05-17 | Jui-Meng Jao | Chip and package structure |
CN101047154A (zh) * | 2006-03-29 | 2007-10-03 | 台湾积体电路制造股份有限公司 | 半导体装置及其形成方法 |
US20090001605A1 (en) * | 2007-06-26 | 2009-01-01 | Jong Hoon Kim | Semiconductor package and method for manufacturing the same |
US20090194890A1 (en) * | 2008-01-31 | 2009-08-06 | Knut Kahlisch | Integrated Circuit and Memory Module |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106601632A (zh) * | 2015-10-14 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制造方法 |
CN107675156A (zh) * | 2017-08-14 | 2018-02-09 | 合肥市田源精铸有限公司 | 一种增强离合器壳机械性能的处理方法 |
CN107675156B (zh) * | 2017-08-14 | 2019-07-26 | 合肥市田源精铸有限公司 | 一种增强离合器壳机械性能的处理方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2013519235A (ja) | 2013-05-23 |
JP5766213B2 (ja) | 2015-08-19 |
CN102812542B (zh) | 2016-04-27 |
EP2532023A1 (en) | 2012-12-12 |
WO2011097464A1 (en) | 2011-08-11 |
US20110193211A1 (en) | 2011-08-11 |
KR20120127481A (ko) | 2012-11-21 |
JP2015079995A (ja) | 2015-04-23 |
KR101512804B1 (ko) | 2015-04-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101996893B (zh) | 半导体器件及其制造方法 | |
TWI819252B (zh) | 半導體核心組件 | |
CN102082128B (zh) | 半导体封装和半导体管芯安装到tsv衬底相对侧的方法 | |
CN101996894B (zh) | 半导体器件和围绕管芯周边形成坝材料以减小翘曲的方法 | |
CN101996896B (zh) | 半导体器件及其制造方法 | |
CN101996895B (zh) | 半导体器件及其制造方法 | |
US9583446B2 (en) | Semiconductor device and method of forming a shielding layer between stacked semiconductor die | |
US9478486B2 (en) | Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV | |
TWI499030B (zh) | 在矽穿孔插入物中形成開放孔穴以包含在晶圓級晶片尺寸模組封裝的半導體晶粒之半導體裝置和方法 | |
CN102244012B (zh) | 半导体器件及其制造方法 | |
CN102543772B (zh) | 结合晶片级不同尺寸半导体管芯的方法和半导体器件 | |
CN102812542B (zh) | 用于改进结合强度的裸片的表面制备 | |
US10163744B2 (en) | Semiconductor device and method of forming a low profile dual-purpose shield and heat-dissipation structure | |
CN103325727A (zh) | 形成扇出封装体叠层器件的半导体方法和器件 | |
CN102637608A (zh) | 半导体器件和形成用于3d fo-wlcsp的垂直互连结构的方法 | |
TW201216421A (en) | Semiconductor device and method of forming adhesive material over semiconductor die and carrier to reduce die shifting during encapsulation | |
CN102237281A (zh) | 半导体器件及其制造方法 | |
US8877563B2 (en) | Microfabricated pillar fins for thermal management | |
CN101996955A (zh) | 芯片封装体及其制造方法 | |
US11316247B2 (en) | Semiconductor packaging structure having antenna module | |
CN112005369B (zh) | 制造半导体器件的方法及半导体器件 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160427 Termination date: 20220204 |