CN102237281A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN102237281A CN102237281A CN2011101066197A CN201110106619A CN102237281A CN 102237281 A CN102237281 A CN 102237281A CN 2011101066197 A CN2011101066197 A CN 2011101066197A CN 201110106619 A CN201110106619 A CN 201110106619A CN 102237281 A CN102237281 A CN 102237281A
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Abstract
本发明涉及半导体器件及其制造方法。一种半导体器件具有被安装到衬底内部的管芯附着区的倒装芯片型或PoP半导体管芯。该衬底具有在管芯附着区周围的接触焊盘区和在管芯附着区与接触焊盘区之间的流动控制区。第一沟渠形成在流动控制区内的衬底的表面中。第一沟渠在管芯附着区外围周围延伸。第一坝材料被形成得邻近流动控制区内的第一沟渠。底部填充材料被沉积在管芯和衬底之间。第一沟渠和第一坝材料控制底部填充材料向外流以防止过多的底部填充材料覆盖接触焊盘区。第二沟渠可以被形成得邻近第一坝材料。第二坝材料可以被形成得邻近第一沟渠。
Description
技术领域
本发明总体上涉及半导体器件,并且更具体地说涉及半导体器件和在衬底上的管芯附着区周围形成相邻沟渠(channel)和坝材料以控制过多的底部填充材料向外流的方法。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件,例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池、以及数字微镜器件(DMD)。
半导体器件执行多种功能,例如高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流(base current)或者通过掺杂工艺来操纵(manipulated)它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构(包括双极和场效应晶体管)控制电流的流动。通过改变掺杂水平并且施加电场或基极电流,晶体管促进或限制电流的流动。无源结构(包括电阻器、电容器、和电感器)产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路,所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件,即前端制造和后端制造,每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化(singulating)单个管芯并且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外,更小的半导体器件具有更小的占地面积(footprint),其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的管芯的前端工艺可以实现更小的管芯尺寸。通过改善电互连和封装材料,后端工艺可以产生具有更小占地面积的半导体器件封装。
半导体管芯或封装通常被安装到衬底或PCB。在倒装芯片型半导体管芯的情形下,形成在管芯的有源表面上的凸块被用冶金的方法且电性地连接到衬底上的接触焊盘。半导体管芯和衬底之间的空隙可以被填充底部填充材料用于结构支撑和环境隔离。分配适量底部填充材料是难以控制的。过多的底部填充材料通常会溢出或向外流,超过半导体管芯的占用空间。所述过多的底部填充材料可能无意地覆盖衬底的其它部分,例如接近管芯但是在管芯的占用空间外部的接触焊盘。已经在半导体管芯的周围形成坝材料以试图阻止过多的底部填充材料。由于难以分配适量底部填充材料,只有坝材料经常不足以控制过量底部填充材料向外流。
发明内容
存在对控制过多底部填充材料从衬底的管芯附着区向外流的需要。因此,在一个实施例中,本发明是制造半导体器件的方法,所述方法包括以下步骤:提供衬底,该衬底具有在衬底内部的管芯附着区和在管芯附着区周围的接触焊盘区以及在衬底表面上在管芯附着区和接触焊盘区之间的流动控制区,以及在流动控制区内的衬底的表面中形成第一沟渠。第一沟渠在管芯附着区的外围周围延伸。所述方法进一步包括以下步骤:在流动控制区内形成邻近第一沟渠的第一坝材料,将半导体管芯安装到衬底的管芯附着区,以及在半导体管芯和衬底之间沉积底部填充材料。第一沟渠和第一坝材料控制底部填充材料向外流以防止过多的底部填充材料覆盖接触焊盘区。
在另一个实施例中,本发明是制造半导体器件的方法,所述方法包括以下步骤:提供衬底,该衬底具有在衬底内部的管芯附着区和在管芯附着区周围的接触焊盘区以及在管芯附着区和接触焊盘区之间的流动控制区,在流动控制区内的衬底中形成第一沟渠,在流动控制区内形成邻近第一沟渠的第一坝材料,将半导体管芯安装到衬底的管芯附着区,以及在半导体管芯和衬底之间沉积底部填充材料。第一沟渠和第一坝材料控制底部填充材料向外流以防止过多的底部填充材料覆盖接触焊盘区。
在另一个实施例中,本发明是制造半导体器件的方法,所述方法包括以下步骤:提供具有管芯附着区的衬底,在管芯附着区周围的衬底中形成第一沟渠,形成邻近第一沟渠的第一坝材料,将半导体管芯安装到衬底的管芯附着区,以及在半导体管芯和衬底之间沉积底部填充材料。第一沟渠和第一坝材料控制过多的底部填充材料向外流。
在另一个实施例中,本发明是包括衬底的半导体器件,所述衬底具有管芯附着区和在管芯附着区周围的接触焊盘区。第一沟渠形成在管芯附着区和接触焊盘区之间的衬底中。坝材料被形成得邻近管芯附着区和接触焊盘区之间的第一沟渠。半导体管芯被安装到衬底的管芯附着区。底部填充材料被沉积在半导体管芯和衬底之间。第一沟渠和第一坝材料控制底部填充材料向外流以防止过多的底部填充材料覆盖接触焊盘区。
附图说明
图1示出具有安装到其表面的不同类型封装的PCB;
图2a-2c示出安装到所述PCB的典型半导体封装的更多细节;
图3a-3h示出在衬底上的管芯附着区周围形成相邻沟渠和坝材料以控制过多的底部填充材料向外流的过程;
图4a-4b示出在管芯附着区周围的相邻沟渠和坝材料的另一个实施例;
图5a-5b示出在管芯附着区周围的邻近沟渠的两个坝材料;以及
图6a-6b示出在管芯附着区周围的邻近坝材料的两个沟渠。
具体实施方式
参考附图在下列描述中的一个或多个实施例中描述本发明,在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明,但是本领域技术人员将理解的是,它旨在覆盖可以被包含在由被下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型、和等效物。
一般利用两个复杂的制造工艺制造半导体器件:前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件,所述有源和无源电部件被电连接以形成功能电路。有源电部件,例如晶体管和二极管,具有控制电流的流动的能力。无源电部件,例如电容器、电感器、电阻器、和变压器,产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性,将半导体材料转变成绝缘体、导体,或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域,所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如,薄膜沉积可以包括化学汽相沉积(CVD)、物理汽相沉积(PVD)、电解电镀、以及无电极电镀(electroless plating)工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层,所述光刻包括在将被图案化的层上沉积光敏材料,例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。利用溶剂将经受光的光致抗蚀剂图案部分除去,暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去,留下被图案化的层。可替换地,利用例如无电极电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间,磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌(topography),产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯,并且然后封装管芯用于结构支撑和环境隔离。为单体化管芯,沿被叫做划片街区(saw street)或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后,单个管芯被安装到封装衬底,所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块(stud bump)、导电胶、或线结合(wirebond)来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图1示出具有芯片载体衬底或印刷电路板(PCB)52的电子器件50,所述芯片载体衬底或印刷电路板(PCB)52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装,这取决于应用。为了说明的目的,在图1中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地,电子器件50可以是更大系统的子部件。例如,电子器件50可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。
在图1中,PCB 52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电极电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线(trace)54形成在PCB 52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中,半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中,半导体器件可以仅具有第一级封装,其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的,几种第一级封装,包括线结合封装56和倒装芯片58,被示出在PCB 52上。另外,几种第二级封装,包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插式封装(DIP)64、岸面栅格阵列(land grid array,LGA)66、多芯片模块(MCM)68、四侧无引脚扁平封装(quad flat non-leaded package,QFN)70、以及四侧扁平封装72被示出安装在PCB 52上。根据系统要求,利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件,可以被连接到PCB 52。在一些实施例中,电子器件50包括单个附着的半导体封装,虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装,制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能,所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少,对用户而言导致更低的成本。
图2a-2c示出示范性半导体封装。图2a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区,所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如,电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是导电材料(例如铝(AL)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、或银(Ag))的一个或多个层,并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间,利用金硅共晶层或粘附材料(例如热的环氧或环氧树脂)将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料,例如聚合物或陶瓷。导体引线80和线结合82在半导体管芯74和PCB 52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染管芯74或线结合82来进行环境保护。
图2b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填充材料或环氧树脂粘附材料92被安装到载体90上。线结合94在接触焊盘96和98之间提供第一级封装互连。模塑料或密封剂100被沉积在半导体管芯88和线结合94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电极电镀这样合适的金属沉积形成在PCB 52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104被形成在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间。
在图2c中,利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路,所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如,该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被电连接和机械连接到载体106。
BGA 60 利用凸块112电连接和机械连接到具有BGA型第二级封装的PCB 52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中,半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 52。
图3a-3g相对于图1和图2a-2c示出在衬底上的管芯附着区周围形成相邻的沟渠和坝材料以控制过多的底部填充材料向外流的过程。图3a示出具有顶表面122和对向的底表面124的衬底或PCB 120。衬底120包括水平导电层126和形成在绝缘或介电材料130之上或之内的垂直导电层128。另外,多个接触焊盘132形成在衬底120的顶表面122中。衬底120通过导电层126和128以及接触焊盘132为半导体管芯提供结构支撑和电互连。
在图3b中,衬底120的顶表面122具有指定用于安装半导体管芯的管芯附着区138和被接触焊盘132占有的接触焊盘区139。管芯附着区138通常位于衬底120的内部空间内。接触焊盘区139位于管芯附着区138周围、半导体管芯的占用空间外部(例如在衬底120的外围周围)。位于管芯附着区138和接触焊盘区139之间的流动控制区135被指定用于控制过多的底部填充材料向外流。利用锯条或激光切割工具136在衬底120的绝缘材料130中切割沟槽或沟渠134。沟渠134被形成得部分或完全在流动控制区135内的管芯附着区138的外围周围,即在管芯附着区138和接触焊盘区139之间。
在图3c中,坝材料140被形成得邻近流动控制区135内的沟渠134。在这种情形下,坝材料140被部分或完全形成在沟渠134的外围周围,即在沟渠的最接近接触焊盘区139的一侧。坝材料140可以是阻焊剂、粘合剂、绝缘体、聚合物、金属、或其它合适的屏障材料。取决于材料,通过丝网印刷、电解电镀、无电极电镀、喷涂、或其它合适的沉积工艺形成坝材料140。在一个实施例中,沟渠134具有进入到绝缘层130之中最小5微米(μm)的深度并且坝材料140具有在顶表面122上延伸最小5μm的高度。
图3d示出具有形成在管芯附着区138的外围周围的沟渠134和形成在最接近接触焊盘区139的沟渠134的外围周围的坝材料140的衬底120的顶视图。沟渠134和坝材料140两者都在流动控制区135内。
图3e示出具有形成在面向下朝向衬底120的有源表面148上的接触焊盘146的半导体管芯或部件144。多个凸块150形成在接触焊盘146上。有源表面148包括被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层的模拟或数字电路。例如,所述电路可以包括一个或多个晶体管、二极管、以及形成在有源表面148内的其它电路元件以实现模拟电路或数字电路,例如数字信号处理器(DSP)、ASIC、存储器、或其它信号处理电路。半导体管芯144也可以包括IPD,例如电感器、电容器、和电阻器,用于RF信号处理。
在图3f中,半导体管芯144与管芯附着区138对准并且通过回流凸块150被安装到衬底120以将凸块用冶金的方法且电性地连接到导电层126。在一个实施例中,半导体管芯144是倒装芯片型半导体管芯。可替换地,层叠封装(PoP)半导体器件可以被安装到衬底120的管芯附着区138。接触焊盘132根据半导体管芯144的电设计和功能被电连接到导电层126和128。接触焊盘132提供从衬底120到外部电路部件的附加电互连。
在图3g中,底部填充材料154,例如环氧树脂或粘合剂,利用分配器156被沉积在衬底120和半导体管芯144之间。沟渠134和坝材料140控制底部填充材料154向外流以防止过多的底部填充材料到达接触焊盘区139并且覆盖接触焊盘132。可以选择沟渠134的深度和坝材料140的高度以控制过多的底部填充材料154向外流。图3h示出控制过多的底部填充材料154向外流的沟渠134和坝材料140的顶视图。接触焊盘132保持没有底部填充材料154,以用于从衬底120到外部部件的优良电连接。
导电凸块材料利用蒸发、电解电镀、无电极电镀、球滴、或丝网印刷工艺被沉积在形成在底表面124上的导电层126上。所述凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其组合,以及可选的焊剂溶液。例如,凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。凸块材料利用合适的附着或结合工艺被结合到导电层126。在一个实施例中,通过将凸块材料加热到它的熔点以上,所述凸块材料回流以形成球形球或凸块158。在一些应用中,凸块158被二次回流以改善到导电层126的电接触。凸块也可以被压缩结合到导电层126。凸块158表示一种可以形成在导电层126上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
沟渠和坝材料的另一个实施例在图4a中示出。从图3a中所示的结构继续,利用锯条或激光切割工具在衬底120的绝缘材料130中切割沟槽或沟渠160,类似于图3b。沟渠160被部分或完全形成在流动控制区135内的管芯附着区138的外围周围。
坝材料164被形成得邻近流动控制区135内的沟渠160。在这种情形下,坝材料164被部分或完全形成在管芯附着区138的外围周围,即在沟渠的最接近管芯附着区的一侧。坝材料164可以是阻焊剂、粘合剂、绝缘体、聚合物、金属、或其它合适的屏障材料。取决于材料,通过丝网印刷、电解电镀、无电极电镀、喷涂、或其它合适的沉积工艺形成坝材料164。在一个实施例中,沟渠160具有进入到绝缘层130之中最小5 μm的深度并且坝材料164具有在顶表面122上延伸最小5μm的高度。
类似于图3e,半导体管芯或部件166具有形成在面向下朝向衬底120的有源表面170上的接触焊盘168。多个凸块172形成在接触焊盘168上。有源表面170包括被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层的模拟或数字电路。例如,所述电路可以包括一个或多个晶体管、二极管、以及形成在有源表面170内的其它电路元件以实现模拟电路或数字电路,例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯166也可以包括IPD,例如电感器、电容器、和电阻器,用于RF信号处理。
半导体管芯166与管芯附着区138对准并且通过回流凸块172被安装到衬底120以将凸块用冶金的方法且电性地连接到导电层126。在一个实施例中,半导体管芯166是倒装芯片型半导体管芯。可替换地,PoP半导体器件可以被安装到衬底120的管芯附着区138。多个凸块174形成在底表面124上的导电层126上。接触焊盘132根据半导体管芯166的电设计和功能被电连接到导电层126和128。接触焊盘132提供从衬底120到外部电路部件的附加电互连。
类似于图3g,底部填充材料176,例如环氧树脂或粘合剂,利用分配器被沉积在衬底120和半导体管芯166之间。沟渠160和坝材料164控制底部填充材料176向外流以防止过多的底部填充材料到达接触焊盘区139并且覆盖接触焊盘132。可以选择沟渠160的深度和坝材料164的高度以控制过多的底部填充材料176向外流。图4b示出控制过多的底部填充材料176向外流的沟渠160和坝材料164的顶视图。接触焊盘132保持没有底部填充材料176,以用于从衬底120到外部部件的优良电连接。
沟渠和坝材料的另一个实施例在图5a中示出。从图3a中所示的结构继续,利用锯条或激光切割工具在衬底120的绝缘材料130中切割沟槽或沟渠180,类似于图3b。沟渠180被部分或完全形成在流动控制区135内的管芯附着区138的外围周围。
坝材料184被形成得邻近流动控制区135内的沟渠180。在这种情形下,坝材料184被部分或完全形成在管芯附着区138的外围周围,即在沟渠的最接近管芯附着区的一侧。坝材料185被形成在部分或完全地在与坝材料184相对的沟渠180外围周围的流动控制区135内,即在沟渠的最接近接触焊盘区139的一侧。坝材料184和185可以是阻焊剂、粘合剂、绝缘体、聚合物、金属、或其它合适的屏障材料。取决于材料,通过丝网印刷、电解电镀、无电极电镀、喷涂、或其它合适的沉积工艺形成坝材料184和185。在一个实施例中,沟渠180具有进入到绝缘层130之中最小5 μm的深度并且坝材料184和185具有在顶表面122上延伸最小5μm的高度。
类似于图3e,半导体管芯或部件186具有形成在面向下朝向衬底120的有源表面190上的接触焊盘188。多个凸块192形成在接触焊盘188上。有源表面190包括被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层的模拟或数字电路。例如,所述电路可以包括一个或多个晶体管、二极管、以及形成在有源表面190内的其它电路元件以实现模拟电路或数字电路,例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯186也可以包括IPD,例如电感器、电容器、和电阻器,用于RF信号处理。
半导体管芯186与管芯附着区138对准并且通过回流凸块192被安装到衬底120以将凸块用冶金的方法且电性地连接到导电层126。在一个实施例中,半导体管芯186是倒装芯片型半导体管芯。可替换地,PoP半导体器件可以被安装到衬底120的管芯附着区138。多个凸块194形成在底表面124上的导电层126上。接触焊盘132根据半导体管芯186的电设计和功能被电连接到导电层126和128。接触焊盘132提供从衬底120到外部电路部件的附加电互连。
类似于图3g,底部填充材料196,例如环氧树脂或粘合剂,利用分配器被沉积在衬底120和半导体管芯186之间。沟渠180与坝材料184和185控制底部填充材料196向外流以防止过多的底部填充材料到达接触焊盘区139并且覆盖接触焊盘132。可以选择沟渠180的深度和坝材料184和185的高度以控制过多的底部填充材料196向外流。图5b示出控制过多的底部填充材料196向外流的沟渠180和坝材料184和185的顶视图。接触焊盘132保持没有底部填充材料196,以用于从衬底120到外部部件的优良电连接。
沟渠和坝材料的另一个实施例在图6a中示出。从图3a中所示的结构继续,利用锯条或激光切割工具在衬底120的绝缘材料130中切割沟槽或沟渠200,类似于图3b。在最接近接触焊盘区139的沟渠200的外围周围的衬底120的绝缘材料130中切割另一个沟渠201,与沟渠200分隔开。沟渠200和201被部分或完全地形成在流动控制区135内的管芯附着区138的外围周围。
坝材料204被部分或完全地形成在流动控制区135内的沟渠200和201之间的间隔周围。坝材料204可以是阻焊剂、粘合剂、绝缘体、聚合物、金属、或其它合适的屏障材料。取决于材料,通过丝网印刷、电解电镀、无电极电镀、喷涂、或其它合适的沉积工艺形成坝材料204。在一个实施例中,沟渠200和201具有进入到绝缘层130之中最小5 μm的深度并且坝材料204具有在顶表面122上延伸最小5μm的高度。
类似于图3e,半导体管芯或部件206具有形成在面向下朝向衬底120的有源表面210上的接触焊盘208。多个凸块212形成在接触焊盘208上。有源表面210包括被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层的模拟或数字电路。例如,所述电路可以包括一个或多个晶体管、二极管、以及形成在有源表面210内的其它电路元件以实现模拟电路或数字电路,例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯206也可以包括IPD,例如电感器、电容器、和电阻器,用于RF信号处理。
半导体管芯206与管芯附着区138对准并且通过回流凸块212被安装到衬底120以将凸块用冶金的方法且电性地连接到导电层126。在一个实施例中,半导体管芯206是倒装芯片型半导体管芯。可替换地,PoP半导体器件可以被安装到衬底120的管芯附着区138。多个凸块214形成在底表面124上的导电层126上。接触焊盘132根据半导体管芯206的电设计和功能被电连接到导电层126和128。接触焊盘132提供从衬底120到外部电路部件的附加电互连。
类似于图3g,底部填充材料216,例如环氧树脂或粘合剂,利用分配器被沉积在衬底120和半导体管芯206之间。沟渠200和201与坝材料204控制底部填充材料216向外流以防止过多的底部填充材料到达接触焊盘区139并且覆盖接触焊盘132。可以选择沟渠200和201的深度和坝材料204的高度以控制过多的底部填充材料216向外流。图6b示出控制过多的底部填充材料216向外流的沟渠200和201与坝材料204的顶视图。接触焊盘132保持没有底部填充材料216,以用于从衬底120到外部部件的优良电连接。
虽然已经详细说明本发明的一个或多个实施例,但是本领域技术人员将理解的是,在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。
Claims (25)
1.一种制造半导体器件的方法,包括:
提供衬底,所述衬底具有在衬底内部的管芯附着区和在管芯附着区周围的接触焊盘区以及在衬底表面上在管芯附着区和接触焊盘区之间的流动控制区;
在流动控制区内的衬底的表面中形成第一沟渠,第一沟渠在管芯附着区的外围周围延伸;
在流动控制区内形成邻近第一沟渠的第一坝材料;
将半导体管芯安装到衬底的管芯附着区;以及
在半导体管芯和衬底之间沉积底部填充材料,其中第一沟渠和第一坝材料控制底部填充材料向外流以防止过多的底部填充材料覆盖接触焊盘区。
2.根据权利要求1的方法,在第一沟渠和管芯附着区之间形成第一坝材料。
3.根据权利要求1的方法,在第一沟渠和接触焊盘区之间形成第一坝材料。
4.根据权利要求1的方法,进一步包括在流动控制区内形成邻近第一坝材料的第二沟渠。
5.根据权利要求1的方法,进一步包括在流动控制区内形成邻近第一沟渠的第二坝材料。
6.根据权利要求1的方法,其中所述半导体管芯是倒装芯片型半导体管芯或层叠封装半导体器件。
7.一种制造半导体器件的方法,包括:
提供衬底,所述衬底具有在衬底内部的管芯附着区和在管芯附着区周围的接触焊盘区以及在管芯附着区和接触焊盘区之间的流动控制区;
在流动控制区内的衬底中形成第一沟渠;
在流动控制区内形成邻近第一沟渠的第一坝材料;
将半导体管芯安装到衬底的管芯附着区;以及
在半导体管芯和衬底之间沉积底部填充材料,其中第一沟渠和第一坝材料控制过多的底部填充材料向外流以防止底部填充材料覆盖接触焊盘区。
8.根据权利要求7的方法,在第一沟渠和管芯附着区之间形成第一坝材料。
9.根据权利要求7的方法,在第一沟渠和接触焊盘区之间形成第一坝材料。
10.根据权利要求7的方法,进一步包括在流动控制区内形成邻近第一坝材料的第二沟渠。
11.根据权利要求7的方法,进一步包括在流动控制区内形成邻近第一沟渠的第二坝材料。
12.根据权利要求7的方法,其中第一沟渠在管芯附着区外围周围延伸。
13.根据权利要求7的方法,其中所述半导体管芯是倒装芯片型半导体管芯或层叠封装半导体器件。
14.一种制造半导体器件的方法,包括:
提供具有管芯附着区的衬底;
在管芯附着区周围的衬底中形成第一沟渠;
形成邻近第一沟渠的第一坝材料;
将半导体管芯安装到衬底的管芯附着区;以及
在半导体管芯和衬底之间沉积底部填充材料,其中第一沟渠和第一坝材料控制过多的底部填充材料向外流。
15.根据权利要求14的方法,在第一沟渠和管芯附着区之间形成第一坝材料。
16.根据权利要求14的方法,其中所述衬底具有在管芯附着区周围的接触焊盘区。
17.根据权利要求16的方法,在第一沟渠和接触焊盘区之间形成第一坝材料。
18.根据权利要求14的方法,进一步包括形成邻近第一坝材料的第二沟渠。
19.根据权利要求14的方法,进一步包括形成邻近第一沟渠的第二坝材料。
20.根据权利要求14的方法,其中第一沟渠在管芯附着区外围周围延伸。
21.一种半导体器件,包括:
具有管芯附着区和在管芯附着区周围的接触焊盘区的衬底;
形成在管芯附着区和接触焊盘区之间的衬底中的第一沟渠;
被形成得邻近管芯附着区和接触焊盘区之间的第一沟渠的第一坝材料;
被安装到衬底的管芯附着区的半导体管芯;以及
被沉积在半导体管芯和衬底之间的底部填充材料,其中第一沟渠和第一坝材料控制过多的底部填充材料向外流以防止底部填充材料覆盖接触焊盘区。
22.根据权利要求21的半导体器件,在第一沟渠和管芯附着区之间形成第一坝材料。
23.根据权利要求21的半导体器件,在第一沟渠和接触焊盘区之间形成第一坝材料。
24.根据权利要求21的半导体器件,进一步包括形成邻近第一坝材料的第二沟渠。
25.根据权利要求21的半导体器件,进一步包括形成邻近第一沟渠的第二坝材料。
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CN105280581A (zh) * | 2014-07-03 | 2016-01-27 | 英特尔公司 | 电子封装及连接第一管芯至第二管芯以形成电子封装的方法 |
CN105280581B (zh) * | 2014-07-03 | 2018-04-06 | 英特尔公司 | 电子封装及连接第一管芯至第二管芯以形成电子封装的方法 |
CN109786273A (zh) * | 2017-11-14 | 2019-05-21 | 中芯国际集成电路制造(上海)有限公司 | 集成电路结构及其形成方法 |
CN110957437A (zh) * | 2018-09-27 | 2020-04-03 | 台湾积体电路制造股份有限公司 | 封装结构及其制造方法 |
CN110957437B (zh) * | 2018-09-27 | 2022-07-26 | 台湾积体电路制造股份有限公司 | 封装结构及其制造方法 |
CN111128975A (zh) * | 2018-10-31 | 2020-05-08 | 台湾积体电路制造股份有限公司 | 集成电路封装件及其形成方法 |
US11424173B2 (en) | 2018-10-31 | 2022-08-23 | Taiwan Semiconductor Manufacturing Company. Ltd. | Integrated circuit package and method of forming same |
US11810831B2 (en) | 2018-10-31 | 2023-11-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method of forming same |
Also Published As
Publication number | Publication date |
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TWI590347B (zh) | 2017-07-01 |
US8399300B2 (en) | 2013-03-19 |
KR101647853B1 (ko) | 2016-08-12 |
US9030030B2 (en) | 2015-05-12 |
US20130147065A1 (en) | 2013-06-13 |
CN102237281B (zh) | 2015-07-08 |
TW201201297A (en) | 2012-01-01 |
US20110260338A1 (en) | 2011-10-27 |
KR20110119566A (ko) | 2011-11-02 |
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