CN103779300A - 封装基板及芯片封装构件 - Google Patents

封装基板及芯片封装构件 Download PDF

Info

Publication number
CN103779300A
CN103779300A CN201310223267.2A CN201310223267A CN103779300A CN 103779300 A CN103779300 A CN 103779300A CN 201310223267 A CN201310223267 A CN 201310223267A CN 103779300 A CN103779300 A CN 103779300A
Authority
CN
China
Prior art keywords
base plate
packaging
chip
resisting layer
dam structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310223267.2A
Other languages
English (en)
Inventor
林柏均
裴汉宁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanya Technology Corp
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Publication of CN103779300A publication Critical patent/CN103779300A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/85951—Forming additional members, e.g. for reinforcing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
    • Y10T428/24612—Composite web or sheet

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明公开了一种封装基板，包括一基材，以及一坝体结构或一凹沟结构，位于所述基材的至少一侧，其中所述基材可以是铜箔基板芯材、模封材料或环氧树脂基底。

Description

封装基板及芯片封装构件
技术领域
本发明涉及一种半导体器件，尤其涉及一种封装基板及芯片封装构件。
背景技术
因半导体芯片数量越来越多的输入输出接脚数，目前集成电路封装领域中已持续朝着高密度封装发展。随着半导体芯片的输入输出接脚数增加，当采用打线封装技术时，相邻接合打线的间隔或线距即变得越来越小，越来越密。
已知半导体芯片为保护其不被外界环境影响破坏，通常会以模塑材料密封包覆。上述模塑材料先被充填或注入模具的模穴内，然后以一定流速流到半导体芯片上，最后经过固化处理，形成封装构件。然而，模塑材料却容易溢流到防焊层上。
上述模塑材溢出的现象会影响到后续打线工艺的可靠度，导致外部接点的不良电性接触以及封装构件外观上的瑕疵。为了去除上述模塑材溢出现象，需额外进行基板的处理工序，此亦造成工艺上的困扰与成本的增加。
发明内容
为解决上述技术问题，本发明公开了一种封装基板，包含有一基材，以及一坝体结构以及/或一凹沟结构，设于所述基材的至少一面上。其中所述基材包含铜箔基板芯材、模封材料或环氧树脂基底。
根据本发明实施例，上述封装基板可以包含有一基材，具有一第一面以及相对于所述第一面的第二面；一第一防焊层，设在所述基材的第一面；以及一第二防焊层，设在所述基材的第二面，其中至少所述第一防焊层或所述第二防焊层上设有一坝体结构以及/或一凹沟结构。
根据本发明实施例，本发明公开了一种芯片封装构件，包含有一封装基板，包含有一芯片安置面，以及一底面，相对于所述芯片安置面；一半导体芯片，设在所述芯片安置面上；以及一坝体结构以及/或一凹沟结构，设于所述封装基板的芯片安置面上或底面上。
为让本发明的上述目的、特征及优点能更明显易懂，下文中特举出本发明的优选实施方式，并配合附图作详细说明如下。然而如下的优选实施方式与图式仅供参考与说明用，并非用来对本发明加以限制。
附图说明
图1为依据本发明实施例所绘示的封装基板部分的横断面示意图。
图2是依据本发明另一实施例所绘示的用于DRAM芯片的球栅阵列封装的横断面示意图。
其中，附图标记说明如下：
1    封装基板      24   黏着层
10   基材          26   接合打线
10a  开孔          30   模封材料
12   第一防焊层    100  芯片封装构件
12a  坝体结构      100a 芯片安置面
12b  凹沟结构      100b 底面
14   第二防焊层    200  锡球
20   半导体芯片    210  锡球置入区
22   接合垫
具体实施方式
图1为依据本发明实施例所绘示的封装基板部分的横断面示意图。如图1所示，封装基板1包括一基材10，如铜箔基板芯材，其上具有至少一电路图案。为简化说明，上述的铜箔基板芯材及电路图案在图中并未特别被绘示出来。熟知该项技术的技术人员应理解在芯材两面的电路图案可以通过电镀通孔被电连结起来。此外，封装基板1可以包括有多层的电路图案。封装基板1也可以是不同种类的基板，例如，仅由模封材料构成而未使用铜箔基板芯材或防焊层的基板，或者，基材10可以是环氧树脂基底。
根据本发明实施例，在基材10的第一面提供有一第一防焊层12，且在第一防焊层12上形成有一坝体结构12a，上述坝体结构12a由第一防焊层12的主表面凸出，且具有一宽度w1，例如介于0.001mm至2mm之间，高度h1介于0.001mm至2mm之间。从上往下俯视时，上述坝体结构12a可以有各种不同形状，例如，直线、蛇形或弯曲形状。熟知该项技术的技术人员应理解上述坝体结构12a可以形成在芯材上、模封材料上或者金属层上，端视半导体封装构件选择的基板形式。此外，熟知该项技术的技术人员应理解在其它实施例中，上述坝体结构12a可以与底层(图中标号12)不同材料所构成者。例如，底层(图中标号12)可以是由环氧树脂、铜箔基板、双马来酰亚胺-三氮杂苯(Bismaleimide Triazine，简称BT树脂)、金属或防焊层等，而非只限定在防焊层。
另外，可以选择在靠近坝体结构12a处另外设置一凹沟结构12b。上述凹沟结构12b可以具有一宽度w2，如介于0.001mm至2mm之间，以及一深度h2，如介于0.001mm至2mm之间。同样的，上述凹沟结构12b可以有不同形状，包括直线、蛇形或弯曲形状。根据本发明实施例，上述坝体结构12a基本上与上述凹沟结构12b彼此平行设置。基材10的第二面上可以覆盖有一第二防焊层14。熟知该项技术的技术人员应理解，虽然图中未显示出来，但是上述的坝体结构12a以及/或凹沟结构12b也可以形成在基材10第二面的第二防焊层14上。
图2是依据本发明另一实施例所绘示的用于DRAM芯片的窗式球栅阵列封装(window BGA package)的横断面示意图。如图2所示，芯片封装构件100包含有封装基板1，其细部特征如图1所示。特定来说，封装基板1包含有一芯片安置面100a以及一底面100b相对于芯片安置面100a。芯片安置面100a上设有一半导体芯片20，如DRAM芯片。半导体芯片20可以利用涂布在第二防焊层14上的黏着层24加以固定在芯片安置面100a上。在其它实施例中，标号24可以代表一凸块，而不需使用到黏着层。在又一实施例中，标号24可以同时代表凸块以及黏着层。同样的，标号14并不限于防焊层，而可以是环氧树脂、铜箔基板材、BT树脂或金属等。
封装基板1中设有一开孔10a，又称做“窗”，贯通封装基板1并介于芯片安置面100a与底面100b之间。半导体芯片20的有源面即借由接合打线26穿过开孔10a与封装基板1的底面100b电连结。详细来说，上述接合打线26的一端电连结至半导体芯片20有源面上的接合垫22，另一端则电连结至封装基板1的底面100b上的导线或金手指(未示于图中)。上述第一防焊层12可以提供导线电性上的绝缘及物理上的保护。熟知该项技术的技术人员应理解，标号12并不限于防焊层，而可以是环氧树脂、铜箔基板材、BT树脂或金属等。模封材料30则是用来填满开孔10a并封住接合垫22、接合打线26以及位于封装基板1底面100b的金手指。
根据本发明实施例，第一防焊层12上形成有一坝体结构12a，上述坝体结构12a由第一防焊层12的主表面凸出来。从上往下俯视时，上述坝体结构12a可以有各种不同形状，例如直线、蛇形或弯曲形状。另外，可以选择在靠近坝体结构12a处另外设置一凹沟结构12b。在此例中，凹沟结构12b比坝体结构12a更靠近开孔10a。在成型过程中，第一防焊层12中的凹沟结构12b可以导引溢流的模塑材料至一缓冲区(未示于图中)，而坝体结构12a可以将溢流的模塑材料挡住并停止其继续扩散流动而污染到另一侧的锡球植入区210，其中在锡球植入区210内设有多个锡球200。本发明公开的结构同时能够避免膏状材料的溢流现象。此外，熟知该项技术的技术人员应理解，虽然图中未绘示出来，但是上述的坝体结构12a以及/或凹沟结构12b也可以形成在芯片安置面100a上。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (12)

1.一种封装基板，其特征在于，包含：
一基材，以及
一坝体结构以及/或一凹沟结构，设于所述基材的至少一面上。
2.根据权利要求1所述的封装基板，其特征在于，所述基材包含铜箔基板芯材、模封材料或环氧树脂基底。
3.根据权利要求1所述的封装基板，其特征在于，所述坝体结构的形状为直线、蛇形或弯曲形。
4.根据权利要求1所述的封装基板，其特征在于，所述凹沟结构的形状为直线、蛇形或弯曲形。
5.一种封装基板，其特征在于，包含：
一基材，具有一第一面以及相对于所述第一面的第二面；
一第一防焊层，设在所述基材的第一面；以及
一第二防焊层，设在所述基材的第二面，其中至少所述第一防焊层或所述第二防焊层上设有一坝体结构以及/或一凹沟结构。
6.根据权利要求5所述的封装基板，其特征在于，所述基材包含铜箔基板芯材以及至少一层的线路图案。
7.根据权利要求5所述的封装基板，其特征在于，所述坝体结构的形状为直线、蛇形或弯曲形。
8.根据权利要求5所述的封装基板，其特征在于，所述坝体结构与所述凹沟结构彼此平行设置。
9.一种芯片封装构件，其特征在于，包含：
一封装基板，包含有一芯片安置面，以及一底面，相对于所述芯片安置面；
一半导体芯片，设在所述芯片安置面上；以及
一坝体结构以及/或一凹沟结构，设于所述封装基板的所述芯片安置面上或所述底面上。
10.根据权利要求9所述的芯片封装构件，其特征在于，所述坝体结构以及/或所述凹沟结构形成在一防焊层中、一模封材料中或一金属层中。
11.根据权利要求10所述的芯片封装构件，其特征在于，所述坝体结构的形状为直线、蛇形或弯曲形。
12.根据权利要求10所述的芯片封装构件，其特征在于，所述凹沟结构的形状为直线、蛇形或弯曲形。
CN201310223267.2A 2012-10-25 2013-06-06 封装基板及芯片封装构件 Pending CN103779300A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/659,916 US20140118978A1 (en) 2012-10-25 2012-10-25 Package substrate and chip package using the same
US13/659,916 2012-10-25

Publications (1)

Publication Number Publication Date
CN103779300A true CN103779300A (zh) 2014-05-07

Family

ID=50546979

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310223267.2A Pending CN103779300A (zh) 2012-10-25 2013-06-06 封装基板及芯片封装构件

Country Status (3)

Country Link
US (2) US20140118978A1 (zh)
CN (1) CN103779300A (zh)
TW (1) TWI563619B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108886032A (zh) * 2017-01-03 2018-11-23 深圳市汇顶科技股份有限公司 一种封装芯片的基板结构

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180166419A1 (en) * 2016-12-12 2018-06-14 Nanya Technology Corporation Semiconductor package
EP3799539B1 (de) * 2019-09-27 2022-03-16 Siemens Aktiengesellschaft Schaltungsträger, package und verfahren zu ihrer herstellung

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6987058B2 (en) * 2003-03-18 2006-01-17 Micron Technology, Inc. Methods for underfilling and encapsulating semiconductor device assemblies with a single dielectric material
WO2011063168A1 (en) * 2009-11-19 2011-05-26 Qualcomm Incorporated Underfilled semiconductor package using dam and trench structures and manufacturig methods thereof
CN102237281A (zh) * 2010-04-27 2011-11-09 新科金朋有限公司 半导体器件及其制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6483178B1 (en) * 2000-07-14 2002-11-19 Siliconware Precision Industries Co., Ltd. Semiconductor device package structure
US6661083B2 (en) * 2001-02-27 2003-12-09 Chippac, Inc Plastic semiconductor package
JP4963148B2 (ja) * 2001-09-18 2012-06-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN101019228B (zh) * 2004-09-17 2010-12-08 富士通半导体股份有限公司 半导体器件及其制造方法
TWI240393B (en) * 2004-09-29 2005-09-21 Siliconware Precision Industries Co Ltd Flip-chip ball grid array chip packaging structure and the manufacturing process for the same
US8252615B2 (en) * 2006-12-22 2012-08-28 Stats Chippac Ltd. Integrated circuit package system employing mold flash prevention technology
US7759171B2 (en) * 2007-08-28 2010-07-20 Spansion Llc Method and structure of minimizing mold bleeding on a substrate surface of a semiconductor package
US7834436B2 (en) * 2008-03-18 2010-11-16 Mediatek Inc. Semiconductor chip package
TW200952591A (en) * 2008-06-02 2009-12-16 Phoenix Prec Technology Corp Printed circuit board having capacitance component and method of fabricating the same
US8227903B2 (en) * 2010-09-15 2012-07-24 Stats Chippac Ltd Integrated circuit packaging system with encapsulant containment and method of manufacture thereof
US8982577B1 (en) * 2012-02-17 2015-03-17 Amkor Technology, Inc. Electronic component package having bleed channel structure and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6987058B2 (en) * 2003-03-18 2006-01-17 Micron Technology, Inc. Methods for underfilling and encapsulating semiconductor device assemblies with a single dielectric material
WO2011063168A1 (en) * 2009-11-19 2011-05-26 Qualcomm Incorporated Underfilled semiconductor package using dam and trench structures and manufacturig methods thereof
CN102237281A (zh) * 2010-04-27 2011-11-09 新科金朋有限公司 半导体器件及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108886032A (zh) * 2017-01-03 2018-11-23 深圳市汇顶科技股份有限公司 一种封装芯片的基板结构

Also Published As

Publication number Publication date
US20140118978A1 (en) 2014-05-01
US20150041182A1 (en) 2015-02-12
TWI563619B (en) 2016-12-21
TW201417231A (zh) 2014-05-01

Similar Documents

Publication Publication Date Title
US9947625B2 (en) Wiring board with embedded component and integrated stiffener and method of making the same
US9013028B2 (en) Integrated circuit package and method of making
KR102223245B1 (ko) 패키징된 반도체 디바이스
CN103179788A (zh) 用于模塑底部填充的印刷电路板和印刷电路板模塑结构
US9793242B2 (en) Packages with die stack including exposed molding underfill
CN103779300A (zh) 封装基板及芯片封装构件
KR102152041B1 (ko) 높은 신뢰성을 갖는 전자 패키지 구조체, 회로 보드 및 디바이스
CN104779175A (zh) 半导体封装件及其制法
US20120100669A1 (en) Method of manufacturing tmv package-on-package device
US20120264257A1 (en) Mold array process method to prevent exposure of substrate peripheries
CN104576407A (zh) 一种引线框架管脚端面镀锡的封装方法及封装结构
CN103050449A (zh) 封装件及其制法
CN105762127B (zh) 封装基板、半导体封装件及其制法
JP4579258B2 (ja) Ｂｇａ型パッケージ
US9064882B2 (en) Package substrate, manufacturing method thereof, and mold therefor
JP5754864B2 (ja) 基板ストリップ
CN105428251A (zh) 半导体堆叠封装方法
CN206584961U (zh) 一种led支架、led支架阵列、led器件及led显示屏
CN104617077A (zh) 封装基板和集成电路芯片
CN209843691U (zh) 一种双面塑封的芯片封装结构
CN104051373B (zh) 散热结构及半导体封装件的制法
CN103354226B (zh) 堆叠封装器件
CN103715107A (zh) 封装堆栈结构的制法
CN102751203A (zh) 半导体封装结构及其制作方法
CN103354225A (zh) 堆叠封装器件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20140507