TW201417231A - 封裝基板及晶片封裝構件 - Google Patents

封裝基板及晶片封裝構件 Download PDF

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TW201417231A
TW201417231A TW102111974A TW102111974A TW201417231A TW 201417231 A TW201417231 A TW 201417231A TW 102111974 A TW102111974 A TW 102111974A TW 102111974 A TW102111974 A TW 102111974A TW 201417231 A TW201417231 A TW 201417231A
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substrate
package
shape
package substrate
dam structure
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TWI563619B (en
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Po-Chun Lin
Han-Ning Pei
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Nanya Technology Corp
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Abstract

本發明披露一種封裝基板，包括一基材，以及一壩體結構或一凹溝結構，位於該基材的至少一側，其中該基材可以是銅箔基板核心材、模封材料或環氧樹脂基底。

Description

封裝基板及晶片封裝構件
本發明係有關於一種半導體裝置，特別是有關於一種封裝基板及晶片封裝構件。
因應半導體晶片數量越來越多的輸入輸出接腳數，目前積體電路封裝領域中已持續朝著高密度封裝發展。隨著半導體晶片的輸入輸出接腳數增加，當採用打線封裝技術時，相鄰接合打線的間隔或線距即變得越來越小，越來越密。
已知半導體晶片為保護其不被外界環境影響破壞，通常係以模塑材料密封包覆。上述模塑材料係先被充填或射入模具的模穴內，然後以一定流速流到半導體晶片上，最後經過硬化處理，形成封裝構件。然而，模塑材料卻容易溢流到防銲層上。
上述模塑材溢出現象會影響到後續打線製程的可靠度，導致外部接點的不良電性接觸以及封裝構件外觀上的瑕疵。為了去除上述模塑材溢出現象，需額外進行基板的處理工序，此亦造成製程上的困擾與成本的增加。
為達上述目的，本發明披露一種封裝基板，包含有一基材，以及一壩體結構以及/或一凹溝結構，設於該基材的至少一面上。其中該基材包含銅箔基板核心材、模封材料或環氧樹脂基底。
根據本發明實施例，上述封裝基板可以包含有一基材，具有一第一面以及相對於該第一面的第二面；一第一防銲層，設在該基材的該第一面； 以及一第二防銲層，設在該基材的該第二面，其中至少該第一防銲層或該第二防銲層上設有一壩體結構以及/或一凹溝結構。
根據本發明實施例，本發明披露一種晶片封裝構件，包含有一封裝基板，包含有一晶片安置面，以及一底面，相對於該晶片安置面；一半導體晶片，設在該晶片安置面上；以及一壩體結構以及/或一凹溝結構，設於該封裝基板的該晶片安置面上或該底面上。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
1‧‧‧封裝基板
10‧‧‧基材
10a‧‧‧開孔
12‧‧‧第一防銲層
12a‧‧‧壩體結構
12b‧‧‧凹溝結構
14‧‧‧第二防銲層
20‧‧‧半導體晶片
22‧‧‧接合墊
24‧‧‧黏著層
26‧‧‧接合打線
30‧‧‧模封材料
100‧‧‧晶片封裝構件
100a‧‧‧晶片安置面
100b‧‧‧底面
200‧‧‧錫球
210‧‧‧錫球植入區
第1圖為依據本發明實施例所繪示的封裝基板部分剖面示意圖。
第2圖是依據本發明另一實施例所繪示的用於DRAM晶片的窗式球格陣列封裝之剖面示意圖。
第1圖為依據本發明實施例所繪示的封裝基板部分剖面示意圖。如第1圖所示，封裝基板1包括一基材10，例如，銅箔基板核心材，其上具有至少一電路圖案。為簡化說明，上述銅箔基板核心材及電路圖案並未特別被繪示出來。熟習該項技藝者應理解在核心材兩面的電路圖案可以透過電鍍通孔被電連結起來。此外，封裝基板1可以包括有複數層的電路圖案。封裝基板1亦可以是不同種類的基板，例如，僅由模封材料構成的基板，而未使用銅箔基板核心材或防銲層，或者，基材10可以是環氧樹脂基底。
根據本發明實施例，在基材10的第一面提供有一第一防銲層12，且在第一防銲層12上形成有一壩體結構12a，上述壩體結構12a由該第一防銲層12的主表面凸出來，且具有一寬度w1，例如介於0.001mm至2mm之 間，高度h1介於0.001mm至2mm之間。從上往下俯視時，上述壩體結構12a可以有各種不同形狀，例如，直線、蛇形或彎曲形狀。熟習該項技藝者應理解上述壩體結構12a可以形成在核心材上、模封材料上或者金屬層上，端視半導體封裝構件選擇的基板形式。此外，熟習該項技藝者應理解在其他實施例中，上述壩體結構12a可以與底層(圖中標號12)不同材料所構成者。例如，底層(圖中標號12)可以是由環氧樹脂、銅箔基板、雙馬來醯亞胺-三氮雜苯(Bismaleimide Triazine，簡稱BT樹脂)、金屬或防銲層，而非限定於防銲層。
另外，可以選擇在靠近壩體結構12a處另外設置一凹溝結構12b。上述凹溝結構12b可以具有一寬度w2，例如，介於0.001mm至2mm之間，以及一深度h2，例如，介於0.001mm至2mm之間。同樣的，上述凹溝結構12b可以有不同形狀，包括直線、蛇形或彎曲形狀。根據本發明實施例，上述壩體結構12a基本上與上述凹溝結構12b彼此平行設置。在基材10的第二面上，可以覆蓋有一第二防銲層14。熟習該項技藝者應理解，雖然圖中未顯示出來，但是上述的壩體結構12a以及/或凹溝結構12b亦可以形成在基材10的第二面的第二防銲層14上。
第2圖是依據本發明另一實施例所繪示的用於DRAM晶片的窗式球格陣列封裝(window BGA package)之剖面示意圖。如第2圖所示，晶片封裝構件100包含有封裝基板1，其細部特徵如第1圖所示。特定言之，封裝基板1包含有一晶片安置面100a以及一底面100b，相對於晶片安置面100a。在晶片安置面100a上，設有一半導體晶片20，例如，DRAM晶片。半導體晶片20可以利用塗佈在第二防銲層14上的黏著層24加以固定在晶片安置面100a上。在其他實施例中，標號24可以代表一凸塊，而不需使用到黏著層。在又另一實施例中，標號24可以同時代表凸塊以及黏著層。同樣的，標號14並不限於防銲層，而可以是環氧樹脂、銅箔基板材、BT樹脂或金屬等。
在封裝基板1中設有一開孔10a，又稱做”窗”，貫通封裝基板1並介於晶片安置面100a與底面100b之間。半導體晶片20的主動面即藉由接 合打線26穿過開孔10a與封裝基板1的底面100b電連結。細言之，上述接合打線26一端係電連結至半導體晶片20主動面上的接合墊22，另一端則電連結至封裝基板1的底面100b上的導線或金手指(圖未示)。上述第一防銲層12可以提供導線電性上的絕緣及物理上的保護。熟習該項技藝者應理解，標號12並不限於防銲層，而可以是環氧樹脂、銅箔基板材、BT樹脂或金屬等。模封材料30則是用來填滿開孔10a並封住接合墊22、接合打線26以及位於封裝基板1底面100b的金手指。
根據本發明實施例，在第一防銲層12上形成有一壩體結構12a，上述壩體結構12a由第一防銲層12的主表面凸出來。從上往下俯視時，上述壩體結構12a可以有各種不同形狀，例如，直線、蛇形或彎曲形狀。另外，可以選擇在靠近壩體結構12a處另外設置一凹溝結構12b。在此例中，凹溝結構12b比壩體結構12a更靠近開孔10a。在成型過程中，第一防銲層12中的凹溝結構12b可以導引溢流模塑材料至一緩衝區(圖未示)，而壩體結構12a可以將溢流模塑材料擋住並停止其繼續擴散流動而污染到另一側的錫球值入區210，其中在錫球植入區210內設有複數個錫球200。本發明披露的結構同時能夠避免膏狀材料的溢流現象。此外，熟習該項技藝者應理解，雖然圖中未顯示出來，但是上述的壩體結構12a以及/或凹溝結構12b亦可以形成在晶片安置面100a上。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1‧‧‧封裝基板
10‧‧‧基材
12‧‧‧第一防銲層
12a‧‧‧壩體結構
12b‧‧‧凹溝結構
14‧‧‧第二防銲層

Claims (12)

  1. 一種封裝基板，包含有：一基材，以及一壩體結構以及/或一凹溝結構，設於該基材的至少一面上。
  2. 如申請專利範圍第1項所述之封裝基板，其中該基材包含銅箔基板核心材、模封材料或環氧樹脂基底。
  3. 如申請專利範圍第1項所述之封裝基板，其中該壩體結構之形狀為直線、蛇形或彎曲形。
  4. 如申請專利範圍第1項所述之封裝基板，其中該凹溝結構之形狀為直線、蛇形或彎曲形。
  5. 一種封裝基板，包含有：一基材，具有一第一面以及相對於該第一面的第二面；一第一防銲層，設在該基材的該第一面；以及一第二防銲層，設在該基材的該第二面，其中至少該第一防銲層或該第二防銲層上設有一壩體結構以及/或一凹溝結構。
  6. 如申請專利範圍第5項所述之封裝基板，其中該基材包含銅箔基板核心材以及至少一層的線路圖案。
  7. 如申請專利範圍第5項所述之封裝基板，其中該壩體結構之形狀為直線、蛇形或彎曲形。
  8. 如申請專利範圍第5項所述之封裝基板，其中該壩體結構與該凹溝結構彼此平行設置。
  9. 一種晶片封裝構件，包含有：一封裝基板，包含有一晶片安置面，以及一底面，相對於該晶片安置面；一半導體晶片，設在該晶片安置面上；以及一壩體結構以及/或一凹溝結構，設於該封裝基板的該晶片安置面上或該底面上。
  10. 如申請專利範圍第9項所述之晶片封裝構件，其中該壩體結構以及/或該凹溝結構係形成在一防銲層中、一模封材料中或一金屬層中。
  11. 如申請專利範圍第10項所述之晶片封裝構件，其中該該壩體結構之形狀為直線、蛇形或彎曲形。
  12. 如申請專利範圍第10項所述之晶片封裝構件，其中該凹溝結構之形狀為直線、蛇形或彎曲形。
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