200952591 九、發明說明： ;【發明所屬之技術領域】 ' 本發明係有關於—種半導體裝置及其製法，尤指-種 具電容元件之電路板及其製法。 【先前技術】 包子產。口在冋功能及兩速化的趨勢下 封裝件上整合有例如電阻、電容及電感等被動 += (Pass1Ve component) ’以提昇或穩定電子產品的電性功 於。 弟1圖所示 1技術係將被動元件12設置於電 路板1上，但為避免該被動元件12阻礙電路板丨上例如 為半導體晶片11之主動元件與複數焊接塾（圖略）間之 電性連接，通常係將該被動元件12接置於該電路板i之 邊緣或角落的位置上，或該半導體晶片U接置區域以外 之佈局區域上；惟，該被動元件12之設置將降低電路板 i表面線路佈局之靈活性；同時需考量焊接墊設置的位 %，導㈣被動元件12料數量受到偈限，而不利於半 導體裝置高度集積化之發展趨冑；甚者，該被動元件12 佈設數篁隨著半導體裝置高性能之要求而相肖地遽增，如 此，該電路板1表面必須同時容納多數半導體晶片丨丨及 大量被動元件12,迫使封裝件體積增大，而無法符合半 導體裝置輕薄短小之發展潮流。 因此，隨著各式電子產品輕薄短小化之發展趨勢，業 界遂發展出將例如半導體晶片之主動元件，以及例如電 110688 6 200952591 阻、電容、電感 -板上製作線路， ，路板結構。 等之被動元件嵌埋於電路板中， 藉以形成嵌埋有主動元件及被動 再於電路 元件之電 動係顯示習知在電路㈣埋被 = :2A圖所示’提供一係為樹脂壓合銅落之核心板 心板2V;=板21之表面具有薄金屬層21a，且於該核 〜板21中形成至少一貫穿之開孔210。 ❹如第2A、2B圖所示，接著，於該薄金 孔210之孔壁上形成一導電層22。 及開 如第2C圖所示，於該薄金屬層2U及開孔21〇中的 導電層22上電鍍形成金屬層23，使該開孔2 電通孔231。 导 〃如第2D圖所示，再於該導電通孔231之空隙中填滿 係如樹脂之塞孔材料24。 如第2E圖所示，接著，對該金屬層23、導電層22 及薄金屬層21a進行圖案化製程，以在該核心板21表面 形成由金屬層23、導電層22及薄金制21a所構成之第 一線路層25a’且該第一線路層25a具有複數第一電極板 251’並使該導電通孔231電性連接至該核心板21表面之 第一線路層25t該圖案化製程係為成熟之技術，於此不 為文贅述。 如第2F圖所示，於該核心板21及第一線路層25a 上形成有高介電材料層26。 110688 7 200952591 如第2G圖所示，於該高介電材料層26上形成有第二 .線路層25b’該第二線路層25b具有複數第二電極板252, .且該些第二電極板252對應各該第一電極板251，使該第 笔極板251、而介電材料層26及第二電極板252構成 一電容元件20。 如第2H圖所示’於該第二線路層25b及高介電材料 層26上形成有增層結構27，該增層結構27係包括至少 一介電層271、設於該介電層271上之第三線路層25c、 ❹及設於該介電層271中並電性連接至該第三線路層25c 及第二線路層25b之導電盲孔273，且該增層結構27上 設有電性連接至該第三線路層25c之電性接觸墊274，並 於該增層結構27上形成有防焊層28，且該防焊層烈具 有複數防焊層開孔280以露出該電性接觸墊274。 惟，前述習知喪埋有電容元件之電路板，由於高介電 材料層％之陶究填充材（FiUer)含量較高而導致流膠性 田該帛 '線路層25a厚度過厚或該高介電材料層Μ :度降低時，易於該第'線路層25a之線路間發生填充不 實，而造成孔洞、凹陷等狀況。 ΓΗ. h目：：^ 一種習知方式係將一高介電薄型核心層 lg hln c〇re)作為電路板結構之核心板，作 介電薄型核心層之高介電常扳仁該-^ ^ ^ , , 中双；丨罨層厚度小於30//m且 板結構之線路完成後，該高介電薄型 核心層因無銅箔支撐而容易碎裂。 因此如何提供—種具電容元件之電路板及製法，以 110688 8 200952591 避免習知技術所引起的種種缺失，實已成爲目前業界亟待 •克服之課題。 ,【發明内容】 鑒於上述習知技術之缺失，本發明之一目的在於提供 .一種具電容元件之電路板及其製法，能避免高介電材料因 •無法完全填充於線路與線路間，而產生空洞或凹陷等現 象。 本發明之另 的隹於提供一種丹.¾谷兀件之電路 ❹板及其製法，能避免以高介電材料層作核心板，於 路製造後產生電路板結構碎裂。 v 為達上述及其他目的，本發明提出一種具電容元件 電路板，係包括：核心板，係具有相對應之第—表面 外表面i該第一表面具有第一線路層，該第二表面具有 路層，該第—線路層並電性連接至該第二線路層； 系覆設於該核心板之第二表面及第二線路層 •層表層:係形成於該第二介電層中，該第三線路 i面路於第二介電層之表面上，且與該第二介電層 表面知平’該第三線路層並 · 材料層係覆設於該第1電層:二' -極板’南介電 路層，係开4、— 線路層上；第五線 數形成於電材料層上，該第五線路層具有複 /成於該向介電材 該高介電材料層Μ二 複數形成於 形成於該介電材料層中之第三導電盲孔、及複數 電性連接至嗲第電極板，且該第二導電盲孔 違弟二線路層，該第三導電盲孔電性連接至該 110688 9 200952591 第二線路層，並使該第三線路層之第一電極板 -料層、及第二電極板構成電容元件。 μ電材 :依上，之具電容元件之電路板，該核心板 通孔，以電性連接該第一線路層及第二線路層。有導電 * 依上述之結構，復包括第一介雷屏，仫 .板之第-表面及其第一線丄:，電層:係覆設於該核心 成於該第-介電層上，並及細線路層，係形 r 、該弟一介電層中形成有篥一逡 電盲孔以電性連接至該第一線路層。 ¥ U复包括於該第一介電層及第四線路層上形成有第一 二=，該第一增層結構係包括至少一第三介電 電層上之第六線路層、及複數形成“第： 孔，且該第六線路声呈右盗叙^ 日（弟四導電盲 介電声6 θ，、有禝數之電性接觸墊，且於該第二 2層及弟六線路層表面上形成有第第： :層並形成有複數對應各該電性接觸塾之第；二-二 ❹孔，以露出各該電性接觸墊。 曰開 於該高介電材料層及第五線路層上形成有第 开 層結構:該第二增層結構係包括至少-第三介電二第 :介；介電層上之第六線路層、及複數形成於該0第 日連接至該第五及第六線路層之第 上2二該第六線路層具有複數之電性接觸塾，且4 該電性接觸;層，該第二防焊層並形成有複數對應： 墊。 之4二防焊層開孔，以露出各該電性接觸 Π0688 10 200952591 本發明之另-貫施結構，復包括於該第—介 路層上形成有第-防谭層，該第—防焊層並形= 焊層開孔’以露出部份之第四線路層而成為電性 接觸塾；又於該高介電材料層及第五線路層上形成有第 一：烊層’該第二防焊層並形成有複數第二防焊層開孔， 以路出部份之第五線路層而成為電性接觸塾。 她月復提供-種具電容元件之電路板製法，係包 .提供一核心板，係具有相對應之第-表面及第二表 0面，且該第一表面具有第'線路層’該第二表面 二 線路層，且該第-線路層電性連接至該第二線路層；於該 核心板之第二表面及其第二線路層上形成有第二介電 供-承載板，於該承载板上依序形成有第二金屬 曰门”電材料層、及第二線路層，並以該高介電材料層 及其上之第三線路層壓合在該第二介電層中，且該第三線 路層具有複數第-電極板；移除該承載板，以露出該第二 cm該第二金屬一層進行圖案化製程以形成具有複 一；、目孔及複數第二電極板之第五線路層’且該第 二導電盲孔電性連接至該第三線路層，並使該第三線路層 之第一電極板、高介電材料層、及第二電極板構成電容元 件。 、依上述之具電容元件之電路板製法，該核心板復具有 ^電通孔’以電性連接至該第—線路層及第二線路層。 依上述之製法，復包括提供一具有第一金屬層之第一 介電層，並以該第-介層壓合在該核心板之第-表面及其 110688 11 200952591 第一線路層上；於該第一金 ，該第-阻層中形成有第一開口二形成有第-阻層，且於 :層；移除該第-開π區中之“部份之第—金屬 層中形成有第-開孔，並露出夕屬層’以於該第-金屬 第一阻層，以露出該第__ π第—介電層；移除該 % ^ 金屬層； 介電層形成有第三開孔以露出部份之这弟：開孔中之第-一金屬層'第-與第三開孔之孔壁刀之及弟-線路層；於該第 線路層上形成有第-導電層;於該第之第-气阻二且該第三阻料形成有第導 弟一導電層；於該第三開口㊣中 彳路出4份之 線路層、及於該第一與第三開 =層上形成第四 第-導電盲孔以電性連接至該第：第-導電層上形成該 第三阻層及其覆蓋之第—導電層與第曰’以及移除該 第四線路層。 弟金屬層，以顯露該 又依上述之製法’該具有複 二電極板之第五線路層的势法，/二導電目孔及複數第 ”成有第二阻層’且於該第二阻 = -金屬屢’以於該第二金屬層中形成有第命第 部份之高介電材料層；移除該汗，以路出 屬層;於該第二開孔中之高二金 孔以露出部份之第三線路層； ς 弟四開 四開孔之孔壁、及第四開孔中之第三線路上形成有第ιί 電層；於該第二導電層上形成有一ν 不 丨丑層且該第四阻層 110688 12 200952591 中形成有第四開口口、 -開口區中之第二導：：路出部份之第二導電層’·於該第四 •五線路層、及於該第上形成具有複數第二電極板之第 有複數第二導電盲/、第四開孔中之第二導電層上形成 ‘二電極板對應該第=連接至❹三線路層，且該第 .覆蓋之第二導電層°反遥:及移除該第四阻層及其 復包括於部份~ ’ _ ’以顯露該第五線路層。 第五開孔’以露出计了孔中的第二介電層中形成有 ❹第五開孔中形成該第並於該第四開孔及 中之第二導電層上形該/四開孔及第五開孔 第二線路層。 電盲孔，以電性連接至該 復包括於該第—介 增層結構，該第四路層上形成有第一 上 日層結構係包括至少一坌-入兩府 成於該第三介電層上 弟二介電層、形 介電層中並電性連拉/ 層、及複數形成於該第三 U電连連接至該第四及 盲孔，且該第六線路層 料層之弟四導電 ❹三介電層及第六線路/表面上1麵墊，且於該第 防焊層並形成有複數對應各該=有接第一防焊層，該第一 開孔，以露出各該電性接觸墊。電接觸塾之第一防焊層 復包括於該高彳電材料屬卩第 二增層結構’該第二增層結構係包括至少層^形成有第 形成於該第三介電層上之第一第三介電層、 三介電岸t f # Μ# ’ θ及複數形成於該第 ㈣接至該第五及第 電盲孔’且該第六線路層具有複數之電性接觸;之= 】10688 】3 200952591 上形成有第二防焊層，該第二防 ，該電性接觸墊之第二防焊声形成有複數對應各 :墊。 弟料層開孔，以露出各該電性接觸 本發明之另一實施製法，復包括於該第一入 四線路声卜私士女@ 第"電層及第 ' 形成有第一防焊層，該第-防焯层 -數第一防嬋層開孔，以露出部份之>成有複 接觸塾；又於該高介電材料層及 二成為電性 二防焊層，哕坌深路層上形成有第 μ ^ 層並形成有複數帛Μ il以露出部份之坌石綠抑a 丨々杆增開孔， ° 伤之第五線路層而成為電性接觸墊。 本發明具電容元件之電路 之第三表面上先設置且右莖'“介電材料層 該第—介電層及該具有 "以 於該核心板之间介電材料層壓合 料層之第四上線路層上，且於該高介電材 第二電極板之第五圖案化製程，以形成具有 極板，俾使該第一電 _ +應該苐一電 ❹成電容元件;該二:二:電材料層及第二電極板形 避免於線路間或線㈣合填充於線路之間，以 發生孔洞、凹陷等狀況、所形成之間隙’填充不實而 壓合於該核心板之第-矣品 以弟—介電層 . 表面，而以該核心板作支撐，使該 ^材科板非為電路板結構m ^ ^亥 【實施方式】 …外教之虞慮。 以下係藉由特定的具體實例說 — 式，熟悉此技藝之人_μ 發月之貫施方 人士可由本說明書所揭示之内容輕易地 110688 14 200952591 瞭解本發明之其他優點與功效。 - 請參閱第3A至3 J圖，係顯示本發明具電容元件之電 .路板製法之流程示意圖。 如弟3 A及3 B圖所不’首先’提供一核心板3 〇，係 _ 具有相對應之第一表面30a及第二表面3〇b，且該第一表 面30a具有第一線路層31a，該第二表面3〇b具有第二線 路層31b，且該核心板30具有導電通孔3〇1，以電性連接 該第一線路層31a及第二線路層31b;並提供係如樹脂壓 φδ銅V#(RCC)之具有第一金屬層33a之第一介電層 且以該第一介電層32a壓合在該核心板30之第一表 及/、上之第一線路層31a上；再於該核心板之 一表面30b及其第二線路層上壓合有第二介電屉 犯b;又提供一承載板35，於該承載板35上依序形曰 第一金屬層33b、高介電材料層34、及第三線路層3丨有 並以該高介電材料層34壓合在該第二介電層犯/上，c、’ ^其上之第三線路層31c埋入該第二介電層咖中^ 弟二線路層31c表面與第二介電層32b表面齊平。^ 如第3C圖所示，移除該承載板託，以 屬板33b。 二金 阻芦如第3D圖所示，於該第一金屬層聊上形成有第一 曰a且於該第一阻層36a中形成有第一 3:，以露出部份之第一金屬層咖：於該第二：：區 33b上形成有第兔屬層 有弟—開 口區 3 β (1 h，丨v »ij Art、 抑Ub以硌出部份之第二金屬層33b; 成 辕第 310688 右裳η弟層且於該第二阻層36b中形 有乐二開口庶 qβ. . τ ^ 15 200952591 -及第二阻層36a，36b係為乾膜或液態光阻等光阻層。 •如第3E圖所示，以钱刻方式移除該第一開口區曰施 .中之第一金屬層33a’以於該第—金屬層咖中形成有複 數弟-開孔咖a，並露出部份之第一介電層…，並以蝕 刻方式移除該第二開口區36〇b中之第二金屬層咖，以 於該第二金屬層33b中形成有複數第二開孔魏，並露 出部份之高介電材料層34。 如弟3F圖所示，移除該第一及第二阻層 ❹以露出該第一及第二金屬層33a，33b;接著，於該些第一 金屬層33a之第-開孔33Gat的第—介電層他以係如 雷射鑽孔形成有對應之第三開孔32〇a，以露出部份之第 一線路廣31a，且於該些第二開孔33〇b中之高介電材料 層34以係如雷射鑽孔形成有對應之第四開孔，以露 出部份之第三線路層31c，其中部份之第四開孔3训令之 第二介電層32b形成有第五開孔32〇b，以露出部份之第 二線路層31b。 ❿ 如第3G圖所示，於該第一金屬層33a、第一開孔33〇& 與第三開孔320a之孔壁、及第三開孔32〇a中之第一線路 層31a上形成有第一導電層37a，再於該第一導電層 上形成有第三阻層36c ’且該第三阻層36c中形成有第三 開口區360c以露出部份之第一導電層37a ;又於該第二 金屬層33b、第二開孔330b與第四開孔340之孔壁、第 四開孔340中之第三線路層31c、於該第二、第四開孔 330b，340與第五開孔320b之孔壁、及第五開孔32〇b中 110688 16 200952591 y第：線路層31b上形成有第二導電層m，接著，於該 .=-¥電層37b上形成有第四阻層36d，且該第四阻層_ 中形成有第四開π區3_以露出部份之第二導電層 ^卜上迖之第一導電層3?&及第二導電層抓主要作為 -後^鑛金屬材料所需之電流傳導路徑，其可由金屬或沉 .所構成，如選自銅、锡、鎳、鉻、鈦、銅- 鉻等早層或多層結構，或可使用例如聚乙快 機硫聚合物等導電高分子材料；又該第三及第四阻= |36c，36d係為乾膜或液態光阻等光阻層。 如第3H圖所示，於該第三開口區36〇c中之第一導電 二37a上形成第四線路層31d、及於該第一與第三開孔 a’32〇a中之第—導電|…上形成有第—導電盲孔 311d以電性連接i马·楚 , 360d中之第二導電；37b:、’’曰，於該第四開口區 電層37b上形成具有複數第二電極板312 之第五線路層31e、於該第二與第四開孔330b，340令之 第二導電層37b上形成有複數第二導電盲孔3仏以電性 連接至該第三線路層q〗 3鳥，340鳥中之第導：:弟二、第四與第五開孔 T之弟一導電層37b上形成有第三導電盲 孔312e’以電性連接至該第二線路層31b，且該第二電極 板312對應該第一電極板311。 夺 如第3ί圖所示，移除該第三阻層36c及其覆蓋之第 -導電層37a與第-金屬層咖，以顯露該第四線路層 3H’·並移除該第四阻層36d及其覆蓋之第二導電層^ 與第-金屬層33b，以顯露該第五線路層31e，使該第： 110688 17 200952591 線路層31c之第一^ ^ 书極板311、高介電材料層34、及第二 -電極板312構成電容元件38。 . 如第3J及3J’圖所示，於該第-介電層32a及第四 線路層31d上形成有第一防焊層撕，該第一防谭層咖 、、’/成有複數第防焊層開孔39Oa，以露出部份之第四 線路層而成為電性接觸塾404;又於該高介電材料層 3甘4及第五線路層3le上形成有第二防焊層勘，該第二防 :層，b亚形成有複數第二防焊層開孔390b，以露出部 ’之第五線路層31e而成為電性接觸墊404,，如第3j圖 所不，或於該第一介電層32a及第四線路層上形成有 第一增層結構4〇、及該高介電材料層34及第五線路層仏 上形成有第二增層結構40，，其中該第一增層結構4〇係 包=至少一第三介電層401、形成於該第三介電層4〇1上 之第六線路層402、及複數形成於該第三介電層4〇1中並 電性連接該第四及第六線路I 31d’402之第四導電盲孔 t 3並於該第-增層結構4Q上形成有複數電性連接該第 ，、線路層繼之電性接觸墊4G4,且於該第-增層結構4〇 ^形成有第—防焊層咖，該第—防焊層咖並形成有複 +對應各該電性接觸墊4G4之第—防焊層開孔39〇&，以 露出各該電性接觸墊404,而該第二增層 至少-第三介電層卿、形成於該第三介電層二： 第六線路層402，、及複數形成於該第三介電層4〇1，中並 電性連接該第五及第六線路層31e，4〇2，之第四導電盲孔 4〇3，亚於該第二增層結構4〇，上形成有複數電性連接該 110688 18 200952591 第…線路層402,之電性接觸塾4〇4, -構40,上形成有第二防 於咸弟二增層結 成有複數對庫各’念/ 第一防烊層39b並形 .成有稷數對應各該電性接觸墊4〇4，之 390b ’以露出各兮啻w ώ a 丨万斤層開孔 =各㈣性接觸墊·，，如第❿圖所示。 4達上述及其他目的，本發明㈣—種具 .Γ:Γ第係表包面括:核心板3°，係具有相對應之第-表面 厚…μ 且该第一表面心形成有第-線路 層&，該第二表面30b形成有第二線路層31b，且該第 ❹一線路層31a電性連接至該第二線路層训 =:.?於該核心板30之第二表面3〇b及第二= 一’弟—線路層31c，係形成於該第二介電層32b中， 該第三線路層31c表面係裸露於該第二介電層咖之表面 上，且與該第二介電層321}表面齊平，該第三線路層& 並具有複數第-電極板311;高介電材料層34係覆設於 該第二介電層32b及第三線路層31c上；第五線路層 ❹31e，係形成於該高介電材料層34上，該第五線路層3k 具有複數形成於該高介電材料層34中之第二導電盲孔 311e、複數形成於該高介電材料層以及第二介電層犯匕 中之第三導電盲孔312e、及複數形成於該介電材料層 上之第二電極板312，且該第二導電盲孔3Ue電性連接 至該第三線路層31c，該第三導電盲孔312e電性連接至 該第二線路層31b，並使該第三線路層31c之第一電極板 311、高介電材料層34、及第二電極板312構成電容元件 38 ° 110688 19 200952591 依上述之具電容元件 $ 〒您书路板，該核心板30復呈有 導電通孔301，以電性連接★ 设/、名 層31b。 逻接忒弟一線路層31a及第二線路 人攸上延之結構，復包括第一介 該核心板3〇之第-表面3〇um…广"又於 M 叫川a及其第一線路層31a上；以 及弟四線路層係形成於該第一介電層如上，並於 該第-介電層32a中形成有第一導電盲孔311 連 接至該第一線路層31a„ $ ❹〜復包括於該第-介電層32a及第四線路層⑽上形成 有第一增層結構40，該第一增層結構4〇係包括至少一第 三介電層40卜形成於該第三介電層4〇1上之第六線路芦 術、及複數形成於該第三介電層4〇1中並電性連接該第 四線路層31d及第六線路層4〇2之第四導電盲孔4〇3，且 該第六線路層402具有複數之電性接觸墊4〇4，且於該第 三介電層401及第六線路層4〇2表面上形成有第一防^層 ❹39a，該第一防焊層並形成有複數對應各該電性接^ 墊404之第一防焊層開孔39〇a ’以露出各該電性接觸墊 404;又於該高介電材料層34及第五線路層3ie上形成有 第二增層結構40,，該第二增層結構4〇,係包括至少一第 三介電層401，、形成於該第三介電層4〇1，上之第六線路 層402’、及複數形成於該第三介電層4〇1，中並電性連接 至該第五線路層31e及第六線路層402,之第四導電盲孔 403’’且該第六線路層4〇2,具有複數之電性接觸墊， 且於該上形成有第二防焊層39b ’該第二防焊層39b並形 110688 20 200952591 成有複數對應各該電性接觸墊4〇4，之第二防焊層開孔 .39〇b，以露出各該電性接觸墊4〇4,。 本發明具電容元件之電路板，復提供另一實施態樣， 復包括於該第-介電層32a及第四線路層川上形成有第 I防焊層咖，該第一防烊層39a並形成有複數第一防焊 層開孔39Ga’以露出部份之第四線路層3η而成為電性 接觸墊4〇4;又於該高介電材料層34及第五線路層31e ::成有第二防焊層39b’該第二防焊層幾並形成有複 〇弟一防焊層開孔390b，以露出部份之第五線路層31e 而成為電性接觸墊404。 本發明具電容元件之電路板及其製法係於高介電材 =層之第三表面上先設置具有第一電極板之第三線路 二再以該第二介電層及該具有第三線路層之高介電材料 二：合於該核心板之第二表面及第二線路層上且於該高 2電材料層之第四表面的第二金屬層經圖案化製程，以形 C電極板之第五線路層，且該第二電極板對應該 極板’俾使該第一電極板、高介電材料層及第二電 板形成電容元件；該電容材料板無彡諸合填充於線路之 二以避免於線路間或線路與介電層所形成之間隙，填充 :而發生孔洞、凹陷等狀況；且該高介電材料層二 rrt合於該核心板之第二表面，而以該核心板作支 牙使以电谷材料板非為電路板結構之核心層，而 之虞慮。 ”、 上述實把例僅例不性說明本發明之原理及其功效，而 110688 21 200952591 ::用於限制本發明。任何熟習此項技藝之人士均可在不違 -二本u之精神及範_ T m述實施例進行修飾與改 * 因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。 j •【圖式簡單說明】 • 帛1圖係為習知電路板之立體示意圖； 第2A至2H圖# A羽a $ 流程示意圖； 電路板嵌埋被動元件之製法之 ❹第㈣】圖係為本發明之具電容 之示意圖；以及 之k路板製法 【主要元件符號說明】 1 電路板 11 半導體晶片 12 被動元件 20、38 電容元件 ^1 ' 30 核心板 21a 薄金屬層 21 ' 30 核心板 210 開孔 22 導電層 23 金屬層 231 、 301 導電通孔 24 塞孔材料 第3Γ圖為第3J圖之另—實施例。 110688 22 200952591 25a 、 31a 第一線路層 -25b 、 31b 第二線路層 25c ' 31c 第三線路層 251 、 311 第一電極板 252 、 312 第二電極板 26、34 高介電材料層 27 增層結構 271 介電層 273 導電盲孔 274 、 404 、404’ 電性接觸墊 28 防焊層 280 防焊層開孔 30a 第一表面 30b 弟·一表面 31d 第四線路層 311d 第一導電盲孔 ❿31e 第五線路層 311e 第二導電盲孔 312e 第三導電盲孔 32a 第一介電層 320a 第三開孔 32b 第二介電層 320b 第五開孔 33a 第一金屬層 330a 第一開孔 23 110688 200952591 33b -330b ,34 340 35 36a 360a 36b 360b o 36c 360c 36d 360d 37a 37b 39a ❹390a 39b 390b 40 40， 403 、 403, 401 、 401， 402 、 402, 第二金屬層 第二開孔 南介電材料層 第四開孔 承載板 第一阻層 第一開口區 第二阻層 第二開口區 第三阻層 第三開口區 第四阻層 第四開口區 第一導電層 第二導電層 第一防焊層 第一防焊層開孔 第二防焊層 第二防焊層開孔 第一增層結構 第二增層結構 第四導電盲孔 第三介電層 第六線路層 24 110688200952591 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a circuit board having a capacitor element and a method of fabricating the same. [Prior Art] Buns are produced. The port is integrated with a passive += (Pass1Ve component) such as resistors, capacitors and inductors to enhance or stabilize the electrical function of the electronic product. The first technique shown in FIG. 1 is to place the passive component 12 on the circuit board 1, but to prevent the passive component 12 from blocking the electrical connection between the active component of the semiconductor wafer 11 and the plurality of soldering pads (not shown) on the circuit board. Sexual connection, usually the passive component 12 is placed at the edge or corner of the circuit board i, or the layout area outside the semiconductor wafer U connection area; however, the passive component 12 is set to lower the circuit The flexibility of the surface layout of the board i; at the same time, it is necessary to consider the bit % of the solder pad setting, and the number of materials of the passive component 12 is limited, which is not conducive to the development of high integration of semiconductor devices; even, the passive component 12 The number of layouts increases with the high performance requirements of semiconductor devices. Thus, the surface of the circuit board 1 must accommodate a large number of semiconductor wafers and a large number of passive components 12, forcing the package to increase in size and fail to conform to the semiconductor. The development trend of the device is light and short. Therefore, with the trend of light and thin various electronic products, the industry has developed active components such as semiconductor wafers, and, for example, resistors, capacitors, inductors, on-board fabrication lines, and road board structures. The passive components are embedded in the circuit board, so as to form an electric system embedded with the active components and passively in the circuit components. In the circuit (4) buried in the circuit =: 2A, the figure is provided as a resin-bonded copper. The falling core plate 2V; = the surface of the plate 21 has a thin metal layer 21a, and at least one through hole 210 is formed in the core ~ plate 21. For example, as shown in Figs. 2A and 2B, a conductive layer 22 is formed on the wall of the thin gold hole 210. And opening, as shown in Fig. 2C, a metal layer 23 is formed on the conductive layer 22 in the thin metal layer 2U and the opening 21, so that the opening 2 is electrically connected to the hole 231. As shown in Fig. 2D, the gap of the conductive via 231 is filled with a plug material 24 such as a resin. As shown in FIG. 2E, the metal layer 23, the conductive layer 22, and the thin metal layer 21a are patterned to form a metal layer 23, a conductive layer 22, and a thin gold 21a on the surface of the core plate 21. The first circuit layer 25a' is formed, and the first circuit layer 25a has a plurality of first electrode plates 251' and the conductive vias 231 are electrically connected to the first circuit layer 25t of the surface of the core plate 21. The patterning process system For mature technology, this is not a text. As shown in FIG. 2F, a high dielectric material layer 26 is formed on the core plate 21 and the first wiring layer 25a. 110688 7 200952591 As shown in FIG. 2G, a second circuit layer 25b' is formed on the high dielectric material layer 26, the second circuit layer 25b has a plurality of second electrode plates 252, and the second electrode plates 252 corresponds to each of the first electrode plates 251, and the pen electrode plates 251 and the dielectric material layer 26 and the second electrode plates 252 constitute a capacitor element 20. As shown in FIG. 2H, a build-up structure 27 is formed on the second circuit layer 25b and the high dielectric material layer 26, and the build-up structure 27 includes at least one dielectric layer 271 disposed on the dielectric layer 271. a third circuit layer 25c, a conductive via 273 disposed in the dielectric layer 271 and electrically connected to the third circuit layer 25c and the second circuit layer 25b, and the build-up structure 27 is provided Electrically connected to the electrical contact pad 274 of the third circuit layer 25c, and a solder resist layer 28 is formed on the build-up structure 27, and the solder resist layer has a plurality of solder resist openings 280 to expose the electricity Sexual contact pads 274. However, in the above-mentioned circuit board in which the capacitor element is buried, the thickness of the high dielectric material layer (FiUer) is high, which causes the thickness of the circuit layer 25a to be too thick or high. Dielectric material layer Μ: When the degree is lowered, it is easy to cause the filling between the lines of the 'th line layer 25a to be unreal, and cause voids, depressions, and the like.目. h目::^ A conventional method is to use a high dielectric thin core layer lg hln c〇re) as the core board of the circuit board structure, and to make the dielectric thin core layer high dielectric constant puller. ^ ^ , , 中双; After the thickness of the ruthenium layer is less than 30//m and the circuit of the plate structure is completed, the high dielectric thin core layer is easily broken due to the absence of copper foil support. Therefore, how to provide a circuit board and a manufacturing method with a capacitive component, to avoid all kinds of defects caused by the conventional technology, has become an urgent problem to be overcome in the industry. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a circuit board having a capacitor element and a method of manufacturing the same, which can prevent a high dielectric material from being completely filled between a line and a line. Create holes or depressions. Another advantage of the present invention is to provide a circuit board and a method for manufacturing the same, which can avoid the use of a high dielectric material layer as a core board, and the circuit board structure is broken after the road is manufactured. For the above and other purposes, the present invention provides a circuit board having a capacitive component, comprising: a core plate having a corresponding first surface outer surface i, the first surface having a first circuit layer, the second surface having a second layer of the core layer, and a second layer of the second layer and a layer of the layer: formed in the second dielectric layer, the first layer is electrically connected to the second layer The third line i is disposed on the surface of the second dielectric layer and is flush with the surface of the second dielectric layer. The third circuit layer and the material layer are overlaid on the first electrical layer: - a plate "Southern circuit layer", which is opened on the circuit layer; a fifth line number is formed on the layer of electrical material, the fifth circuit layer having the high dielectric material complexed/formed to the dielectric material The second layer is formed in the third conductive blind hole formed in the dielectric material layer, and is electrically connected to the first electrode plate, and the second conductive blind hole is in violation of the second circuit layer, and the third conductive blind is The hole is electrically connected to the 110688 9 200952591 second circuit layer, and the first electrode plate of the third circuit layer The material layer and the second electrode plate constitute a capacitor element.电Electrical material: According to the circuit board of the capacitor component, the core board through hole is electrically connected to the first circuit layer and the second circuit layer. Conductive* according to the above structure, comprising a first screen, a first surface of the board and a first line thereof: an electrical layer: the layer is disposed on the core to form the first dielectric layer And a thin circuit layer, a system r, and a dielectric blind layer formed in the dielectric layer to electrically connect to the first circuit layer. The U complex includes a first two on the first dielectric layer and the fourth circuit layer, and the first build-up structure includes at least a sixth circuit layer on the third dielectric layer, and a plurality of forms No.: the hole, and the sound of the sixth line is right-handed on the day of the day (the fourth conductive blind dielectric sound 6 θ, the electrical contact pad having a number of turns, and the surface of the second layer 2 and the sixth layer Forming a first:: layer and forming a plurality of corresponding to each of the electrical contact turns; two-two holes to expose each of the electrical contact pads. Opening the high dielectric material layer and the fifth line Forming an open-layer structure on the layer: the second build-up structure includes at least a third dielectric second: a sixth circuit layer on the dielectric layer, and a plurality formed on the 0th day connected to the first The second and sixth circuit layers of the second and second circuit layers have a plurality of electrical contact ports, and 4 of the electrical contact; the layer, the second solder resist layer is formed with a plurality of corresponding: pad. The solder resist layer is opened to expose the electrical contact Π 0688 10 200952591. The other embodiment of the present invention is further included in the first dielectric layer a first-anti-tank layer, the first solder mask layer = solder layer opening 'to expose a portion of the fourth circuit layer to become an electrical contact 塾; and the high dielectric material layer and the fifth circuit layer Formed on the first: the second layer of the second solder mask and formed with a plurality of second solder mask opening, and the fifth circuit layer of the exit portion becomes an electrical contact 塾. A circuit board manufacturing method with a capacitive element, a package comprising a core plate having a corresponding first surface and a second surface 0, and the first surface having a 'circuit layer' and the second surface and two circuit layers And the first circuit layer is electrically connected to the second circuit layer; a second dielectric supply-supporting plate is formed on the second surface of the core plate and the second circuit layer thereof, and sequentially formed on the carrier plate a second metal gate" electrical material layer and a second wiring layer, and the high dielectric material layer and the third line thereon are laminated in the second dielectric layer, and the third circuit layer Having a plurality of first electrode plates; removing the carrier plate to expose the second cm of the second metal layer for patterning process to form And a second circuit layer of the second electrode plate and the second conductive blind hole is electrically connected to the third circuit layer, and the first electrode plate of the third circuit layer is high The dielectric material layer and the second electrode plate constitute a capacitor element. According to the circuit board manufacturing method of the capacitor element, the core board has an electrical via hole to electrically connect to the first circuit layer and the second circuit layer. According to the above method, a first dielectric layer having a first metal layer is provided, and the first dielectric layer is laminated on the first surface of the core board and the first circuit layer of 110688 11 200952591; In the first gold, a first opening 2 is formed in the first resist layer, and a first resist layer is formed on the layer; and the layer is formed in the first metal layer in the first-open π region a first opening, and exposing a solar layer to the first metal first resist layer to expose the first _ π first dielectric layer; removing the % ^ metal layer; the dielectric layer is formed a three-opening hole to expose a part of the younger brother: the first-metal layer in the opening, the first- and third-opening hole-wall knives and the younger-line layer; a first conductive layer is formed on the first circuit layer; a first conductive layer is formed on the first first gas barrier and the third resistive material is formed; and 4 lines are formed in the middle of the third opening And forming a fourth first conductive via hole on the first and third open=layers to be electrically connected to the first:first conductive layer to form the third resistive layer and the covered first conductive layer thereof Dijon' and remove the fourth circuit layer. a metal layer to expose the method according to the above method, wherein the second circuit layer having the second electrode plate has a second circuit layer and a plurality of second holes and a second resistance layer = - metal repeatedly "the second metal layer is formed with a first portion of the high dielectric material layer; the sweat is removed to the subordinate layer; the second gold hole in the second opening is Exposed part of the third circuit layer; the fourth wall of the fourth opening of the fourth opening of the brother and the third line of the fourth opening are formed with an ι 电 electric layer; a ν is formed on the second conductive layer a fourth opening of the fourth resistive layer 110688 12 200952591, a second conductive opening in the open area: a second conductive layer of the outgoing portion, and the fourth and fifth circuit layers Forming on the second conductive layer of the first plurality of second conductive blind/fourth openings having a plurality of second electrode plates, forming a 'two-electrode plate corresponding to the second connection to the third circuit layer, and the first Covering the second conductive layer ° reverse: and removing the fourth resistive layer and its complex portion is included in the portion ~ ' _ ' to reveal the fifth line a fifth opening 'to expose the second dielectric layer formed in the hole, the fifth opening is formed in the fifth opening, and the second conductive layer is formed on the second opening and the fourth conductive layer The second circuit layer of the opening and the fifth opening. The electrical blind hole is electrically connected to the first interlayer structure, and the first upper layer structure is formed on the fourth layer a 坌-into two occupants on the third dielectric layer, the second dielectric layer, the dielectric layer and the electrical connection/layer, and the plurality of U-connections are connected to the fourth a blind hole, and a fourth dielectric layer of the sixth circuit layer and a first surface of the sixth line/surface, and the plurality of corresponding layers are formed on the first solder resist layer. a solder resist layer, the first opening, to expose each of the electrical contact pads. The first solder resist layer of the electrical contact is included in the second buildup structure of the sorghum electrical material. The method includes forming at least a first third dielectric layer formed on the third dielectric layer, a third dielectric bank tf # Μ# ' θ, and a plurality of forms formed on the fourth (fourth) 5 and the electric blind hole 'and the sixth circuit layer has a plurality of electrical contacts; the = 10688 】 3 200952591 is formed with a second solder mask, the second guard, the second contact of the electrical contact pad The welding sound is formed with a plurality of corresponding mats: the pad layer is opened to expose the electrical contact with another embodiment of the present invention, and is included in the first four-line sound vocabulary @第" The layer and the first portion are formed with a first solder resist layer, the first anti-mite layer - the first anti-mite layer is opened to expose a portion of the composite layer; and the high dielectric material layer and Second, it becomes an electrical two solder mask. The μ μ layer is formed on the deep road layer and a plurality of 帛Μ il are formed to expose part of the vermiculite green a mast increase hole, ° the fifth of the injury The circuit layer becomes an electrical contact pad. The third surface of the circuit with the capacitive element of the present invention is first disposed and the right stem 'the dielectric material layer of the first dielectric layer and the layer having a dielectric layer laminated between the core plates a fifth patterning process on the fourth upper circuit layer and the second electrode plate of the high dielectric material to form a plate, so that the first electric _+ should be electrically formed into a capacitive element; : 2: the electric material layer and the second electrode plate shape are prevented from being filled between the lines or the line (4), and the holes, the depressions, and the like are formed, and the gap formed is not filled and is pressed against the core plate. The first - product is the younger-dielectric layer. The surface is supported by the core board, so that the board is not a circuit board structure m ^ ^ Hai [Implementation] ... foreign teachers are concerned. The following is by Specific specific examples - the person skilled in the art can easily understand the other advantages and effects of the present invention by the contents disclosed in this specification. - Please refer to Figures 3A to 3 J diagram shows the method of manufacturing the electric circuit board with the capacitor element of the present invention. Schematic diagram of the process. If the figures 3A and 3B do not 'first' provide a core board 3 〇, the system has a corresponding first surface 30a and a second surface 3〇b, and the first surface 30a has the first a circuit layer 31a, the second surface 3b has a second circuit layer 31b, and the core plate 30 has a conductive via 3〇1 for electrically connecting the first circuit layer 31a and the second circuit layer 31b; For example, the first dielectric layer of the first metal layer 33a of the resin pressure φδ copper V# (RCC) and the first surface and/or the upper surface of the core board 30 are pressed by the first dielectric layer 32a. a circuit layer 31a; a second dielectric drawer b is pressed onto the surface 30b of the core board and the second circuit layer; and a carrier 35 is provided on the carrier board 35. The first metal layer 33b, the high dielectric material layer 34, and the third wiring layer 3 are bonded and pressed by the high dielectric material layer 34 on the second dielectric layer, c, '^ The third circuit layer 31c is buried in the second dielectric layer, and the surface of the second circuit layer 31c is flush with the surface of the second dielectric layer 32b. ^ As shown in FIG. 3C, the carrier is removed. Board 33b As shown in FIG. 3D, the first metal layer is formed with a first layer a and a first layer 3 is formed in the first layer 36a to expose a portion of the first metal layer.咖: On the second:: area 33b, a second metal layer 33b is formed on the third layer of the rabbit layer, the open area 3 β (1 h, 丨v » ij Art, and Ub is removed); The third layer of the right layer and the second resist layer 36b have a second opening 庶qβ. τ ^ 15 200952591 - and the second resistive layer 36a, 36b is a dry film or a liquid photoresist such as a photoresist layer . • As shown in FIG. 3E, the first metal layer 33a′ in the first open area region is removed in a motive manner, so that a plurality of brothers are formed in the first metal layer, and Exposing a portion of the first dielectric layer... and etching the second metal layer in the second opening region 36〇b to form a plurality of second openings in the second metal layer 33b And a portion of the high dielectric material layer 34 is exposed. As shown in FIG. 3F, the first and second resist layers are removed to expose the first and second metal layers 33a, 33b; and then, the first opening 33Gat of the first metal layers 33a a dielectric layer, such as a laser drilled hole, formed with a corresponding third opening 32〇a to expose a portion of the first line width 31a, and a high medium in the second openings 33〇b The electrical material layer 34 is formed with a corresponding fourth opening by, for example, laser drilling to expose a portion of the third circuit layer 31c, wherein a portion of the fourth opening 3 is formed by the second dielectric layer 32b. The fifth opening 32〇b is to expose a portion of the second wiring layer 31b. As shown in FIG. 3G, the first metal layer 33a, the first opening 33〇& and the third opening 320a, and the first opening 31a of the third opening 32a are formed. a first conductive layer 37a is formed, and a third resist layer 36c' is formed on the first conductive layer, and a third open region 360c is formed in the third resist layer 36c to expose a portion of the first conductive layer 37a; Further, the second metal layer 33b, the second opening 330b and the fourth opening 340, the third circuit layer 31c of the fourth opening 340, and the second and fourth openings 330b, 340 and The hole wall of the fifth opening 320b and the fifth opening 32b are 110688 16 200952591 y: the second conductive layer m is formed on the circuit layer 31b, and then formed on the .=-¥ electric layer 37b a fourth resistive layer 36d, and a fourth open π region 3_ is formed in the fourth resistive layer _ to expose a portion of the second conductive layer, the first conductive layer 3, and the second conductive layer Grasping the current conduction path required for the main metal material, which may be composed of metal or sinking, such as an early layer or a multilayer structure selected from copper, tin, nickel, chromium, titanium, copper-chromium, or the like. Use case For example, a conductive polymer material such as a polysulfide thiopolymer; and the third and fourth resistors = |36c, 36d are photoresist layers such as dry film or liquid photoresist. As shown in FIG. 3H, a fourth circuit layer 31d is formed on the first conductive layer 37a in the third opening region 36〇c, and a first one of the first and third openings a'32〇a is formed. Conductive | is formed with a first conductive via 311d electrically connected to i Ma Chu, the second conductive in 360d; 37b:, ''曰, formed on the fourth open electrical layer 37b with a plurality of second a fifth circuit layer 31e of the electrode plate 312, and a plurality of second conductive blind holes 3B formed on the second conductive layer 37b of the second and fourth openings 330b, 340 to be electrically connected to the third circuit layer q〗 3 birds, 340 birds in the guide:: brother 2, the fourth and fifth openings T brother a conductive layer 37b is formed with a third conductive blind hole 312e' to electrically connect to the second circuit layer 31b, and the second electrode plate 312 corresponds to the first electrode plate 311. As shown in FIG. 3, the third resistive layer 36c and its covered first conductive layer 37a and the first metal layer are removed to expose the fourth wiring layer 3H'· and the fourth resistive layer is removed. 36d and the second conductive layer and the third metal layer 33b are covered to expose the fifth circuit layer 31e, so that the first: 110688 17 200952591 circuit layer 31c of the first circuit board 311, high dielectric material The layer 34 and the second electrode plate 312 constitute a capacitor element 38. As shown in FIGS. 3J and 3J', a first solder resist layer is formed on the first dielectric layer 32a and the fourth wiring layer 31d, and the first anti-tank layer, '/ has a plurality of The solder mask opening 39Oa is formed to expose a portion of the fourth circuit layer to form an electrical contact 404; and a second solder mask is formed on the high dielectric material layer 3 and the fifth wiring layer 3le The second protection layer: b is formed with a plurality of second solder mask opening 390b to expose the fifth circuit layer 31e of the portion to become the electrical contact pad 404, as shown in FIG. 3j, or A first build-up structure 4 is formed on the first dielectric layer 32a and the fourth circuit layer, and a second build-up structure 40 is formed on the high dielectric material layer 34 and the fifth circuit layer. The first build-up structure 4 includes at least one third dielectric layer 401, a sixth circuit layer 402 formed on the third dielectric layer 401, and a plurality of third dielectric layers 4 1 and electrically connected to the fourth conductive blind vias t 3 of the fourth and sixth lines I 31d'402 and formed with a plurality of electrical connections on the first build-up structure 4Q, and the circuit layer is followed by Sexual contact pad 4 G4, and forming a first solder mask layer in the first build-up structure 4〇, the first solder mask layer is formed with a complex + corresponding to each of the electrical contact pads 4G4 - a solder mask opening 39〇& to expose each of the electrical contact pads 404, and the second build-up layer is formed at least the third dielectric layer, the third dielectric layer 2: the sixth circuit layer 402, and the plurality of layers In the third dielectric layer 4〇1, electrically connected to the fifth and sixth circuit layers 31e, 4〇2, the fourth conductive blind via 4〇3, adjacent to the second build-up structure 4〇 a plurality of electrical connections are formed on the 110688 18 200952591 first circuit layer 402, the electrical contact 塾4〇4, - structure 40, formed on the second anti-Salty two-layered layer formed into a plurality of pairs of libraries each The first anti-mite layer 39b is shaped and formed into a number corresponding to each of the electrical contact pads 4〇4, 390b′ to expose each of the 兮啻w ώ a 丨 丨 斤 = = = = = (4) sexual contact pads , as shown in the figure below. 4 to achieve the above and other objects, the present invention (4) - the species: Γ: Γ 系 表 : : 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心 核心The second layer 30b is formed with a second circuit layer 31b, and the second circuit layer 31a is electrically connected to the second circuit layer: the second surface 3 of the core board 30 〇b and the second=1'-the circuit layer 31c are formed in the second dielectric layer 32b, the surface of the third circuit layer 31c is exposed on the surface of the second dielectric layer, and The second dielectric layer 321} is flush, the third circuit layer & and has a plurality of first electrode plates 311; the high dielectric material layer 34 is coated on the second dielectric layer 32b and the third circuit layer 31c The fifth circuit layer 31e is formed on the high dielectric material layer 34. The fifth circuit layer 3k has a plurality of second conductive vias 311e formed in the high dielectric material layer 34. a high-dielectric material layer and a third conductive via 312e in the second dielectric layer, and a plurality of second electrode plates 312 formed on the dielectric material layer, and the The second conductive via hole 3Ue is electrically connected to the third circuit layer 31c. The third conductive blind via 312e is electrically connected to the second circuit layer 31b, and the first electrode plate 311 of the third circuit layer 31c is high. The dielectric material layer 34 and the second electrode plate 312 constitute a capacitor element 38 ° 110688 19 200952591 According to the above-mentioned capacitor element $ 〒 your book board, the core board 30 is formed with a conductive through hole 301 to electrically connect ★ Set the /, name layer 31b. The structure of the first layer of the core layer 31a and the second line is extended, including the first surface of the core board 3〇 ... um... wide " and M is called Chuan and its first The circuit layer 31a; and the fourth circuit layer are formed on the first dielectric layer as above, and a first conductive blind via 311 is formed in the first dielectric layer 32a to be connected to the first circuit layer 31a. The first build-up structure 40 is formed on the first dielectric layer 32a and the fourth circuit layer (10), and the first build-up structure 4 includes at least one third dielectric layer 40 formed on the first layer The sixth line of the three-dielectric layer 4〇1 is formed in the third dielectric layer 〇1 and electrically connected to the fourth circuit layer 31d and the fourth circuit layer 4〇2 The conductive via hole 4〇3, and the sixth circuit layer 402 has a plurality of electrical contact pads 4〇4, and a first protection layer is formed on the surfaces of the third dielectric layer 401 and the sixth circuit layer 4〇2. The first solder resist layer is formed with a plurality of first solder mask openings 39〇a' corresponding to the respective electrical pads 404 to expose the respective electrical contact pads 404; and the high dielectric material A second build-up structure 40 is formed on the layer 34 and the fifth circuit layer 3ie. The second build-up structure 4 includes at least a third dielectric layer 401 formed on the third dielectric layer 4 The sixth circuit layer 402' is formed on the third circuit layer 402', and the fourth conductive layer is electrically connected to the fifth circuit layer 31e and the sixth circuit layer 402. 403′′ and the sixth circuit layer 4〇2 has a plurality of electrical contact pads, and a second solder resist layer 39b is formed thereon. The second solder resist layer 39b has a plurality of corresponding shapes 110688 20 200952591 Each of the electrical contact pads 4〇4, the second solder resist layer is opened. 39〇b, to expose each of the electrical contact pads 4〇4. The circuit board with the capacitor element of the present invention provides another implementation In a state, a first solder mask layer is formed on the first dielectric layer 32a and the fourth circuit layer, and the first anti-corrugated layer 39a is formed with a plurality of first solder resist openings 39Ga' to be exposed. a portion of the fourth circuit layer 3n becomes the electrical contact pad 4〇4; and the high dielectric material layer 34 and the fifth circuit layer 31e :: the second solder resist layer 39b' is formed with the second solder resist layer A plurality of solder mask openings 390b are formed to expose a portion of the fifth circuit layer 31e to form an electrical contact pad 404. The circuit board having the capacitor element and the method of manufacturing the same are used for the high dielectric material. The third surface of the layer is provided with a third line having a first electrode plate, a second dielectric layer, and a high dielectric material having a third circuit layer: a second surface of the core plate And a second metal layer on the second circuit layer and on the fourth surface of the high electric material layer is patterned to form a fifth circuit layer of the C electrode plate, and the second electrode plate corresponds to the electrode plate The first electrode plate, the high dielectric material layer and the second electric plate form a capacitive element; the capacitive material plate is filled in the second line to avoid a gap formed between the lines or between the line and the dielectric layer. Filling: a hole, a recess, etc. occurs; and the high dielectric material layer rr is combined with the second surface of the core plate, and the core plate is used as a supporting tooth so that the electric grain material plate is not a circuit board structure. The core layer, and then worry. The above examples are merely illustrative of the principles and effects of the present invention, and 110688 21 200952591:: is intended to limit the invention. Anyone skilled in the art can do without the spirit of Modifications and modifications are made to the embodiments. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described later. j • [Simple description of the drawings] • 帛1 is a conventional circuit board 3D to 2HFig. 2 A feather a $ flow diagram; circuit board embedding passive component manufacturing method (4)] diagram is a schematic diagram of the capacitor of the invention; and k-plate method [main component symbol Description] 1 Circuit board 11 Semiconductor wafer 12 Passive component 20, 38 Capacitor component ^1 ' 30 Core plate 21a Thin metal layer 21 ' 30 Core plate 210 Opening 22 Conductive layer 23 Metal layer 231, 301 Conductive through hole 24 Plug material Figure 3 is a further embodiment of Figure 3J. 110688 22 200952591 25a, 31a first circuit layer -25b, 31b second circuit layer 25c' 31c third circuit layer 251, 311 first electrode plate 252, 312 Two electrode plates 26, 34 high dielectric material layer 27 buildup structure 271 dielectric layer 273 conductive blind holes 274, 404, 404' electrical contact pads 28 solder resist layer 280 solder mask opening 30a first surface 30b a surface 31d, a fourth circuit layer 311d, a first conductive blind via 31e, a fifth circuit layer 311e, a second conductive via 312e, a third conductive via 32a, a first dielectric layer 320a, a third opening 32b, a second dielectric layer 320b, a fifth Opening 33a first metal layer 330a first opening 23 110688 200952591 33b - 330b , 34 340 35 36a 360a 36b 360b o 36c 360c 36d 360d 37a 37b 39a ❹ 390a 39b 390b 40 40, 403, 403, 401, 401, 402 402, second metal layer second opening south dielectric material layer fourth opening carrier plate first resistance layer first opening region second resistance layer second opening region third resistance layer third opening region fourth resistance layer Four open area first conductive layer second conductive layer first solder resist layer first solder resist layer opening second solder resist layer second solder resist layer opening first buildup structure second buildup structure fourth conductive blind hole Third dielectric layer sixth circuit layer 24 110688