1301734 九、發明說明： 【發明所屬之技術領域】 *币本發明係指一種電路板結構及其製法，尤指一種利用 導電通孔提供層⑽路作電性連接之電路板結構及其製 ,法。 ^【先前技術】 白知雙層電路板之製程係如第丨A至^ E圖所示，首先 =供=例如樹脂壓合銅M(Resin coated c〇pper，Rcc)之 孟屬壓合芯層板l〇〇，並於其中鑽設有多數個貫穿孔1⑽ (如第1A圖所示）。再經過鍍銅以於該芯層板1〇〇之表面上 及該貫穿孔102之孔壁上沈積有金屬銅層1〇3(如第1β圖 所示）。復於該芯層板100之上覆蓋一係如光阻之阻層 104,並使該阻層1〇4填充於該貫穿孔1〇2中，再對該阻層 10 4進行圖案化，以形成複數外露出部分覆蓋其下之金屬 銅層103之開口 i〇4a(如第lc圖所示）。接著透過蝕刻方 #式移除未為該阻層104所覆蓋之金屬銅層1〇3(如第id圖 所不）e之後再移除該阻層丨04，藉以在該芯層板丨表面 形成有圖案化線路層Μ% (如第Μ圖所示）。後續，即可 在該形成有線路層之芯層板上形成圖案化防焊層，藉以形 成一具有雙層線路層之電路板。 在上述製程中，主要係於該芯層板及其貫穿孔表面形 成一定厚度之金屬銅層，其後於該芯層板上形成一例如乾 膜或光阻之阻層（未圖示），並經過曝光（Exp〇Sure)、顯影 (Deve 10pment)等製程加以圖案化，以使該阻層形成有多數 6 18418 1301734 開口以外露出該芯層板表面之金屬層，俾經由钱刻製程 ^ tr %11 Ve Pr°eeSS )以移除未為該阻相覆蓋之金屬 層部分’藉以形成線路。 蜀 =在上述之自知製程中’易有例如乾膜或綠之阻層 於.充至芯層板貫穿孔時因蓋孔性不良，導致線路圖宰化 刻製程所使用的姓刻液滲透至該芯層板貫穿孔中，甚 而姓刻該貫穿孔孔壁上的金屬銅層，以致_液咬㈣貫 :孔孔壁之金屬層’而使該芯層板上下表 ， :::貫：孔:L壁之金屬層電性導接，影響電路板層；導； :。之电f生p牛低了產品良率。亦或於蝕刻製程時，覆蓋於 該芯層板貫穿孔位置處之阻層被蝴液沖破致使該貫=孔 :上壁：金屬層被蝕刻液咬蝕斷裂，造成電路板層間導電处 構之V電性不良，產品良率降低。 、° 不易=述之1知技術中，由於貫穿孔孔壁之金屬層厚度 " 使仵後續進行圖案化製程以形成線路時，為避 1免:虫刻液過度咬蝕該貫穿孔孔壁之金屬層，使得該貫穿孔 :壁：金屬層超出設計規格，而無法提供細間距之線路結 構’造成製程上的瓶頸。 ° 因此，如何提供一種電路板之製法，以避免習知 所引起的製程良率降低、製程複雜、及電路板層間社 構可靠性不佳、電性功能降低等缺失，實 i 亟待解決之難題。 月』菜界 【發明内容] 鑒於上述習知技術之缺失，本發明之主要目的即在於 7 18418 1301734 =::重電广反結構及其製法，以確保電路板層間導電結 構t电性功能及電路板製程良率。 為達上述及其他目的，本發 製法，係包括：提供一芯層板，且路板結構之 、， 且5亥心層中形成至少一貫 1严；亚於該芯層板表面及該貫穿孔孔壁形成-定厚度之 於該芯層板表面之金屬層上覆蓋一阻層，且令該 且^對應該貫穿孔位置形成有開口，以外露出該· 孔壁之金屬層；於該阻層開口中之 :二： •護層；以及移除該阻層，並圖宰㈣：二上：成一金屬保 、… 木化邊4層板表面之金眉屌 :乂：成圖案化線路層。後續復可於該形成有線路層之芯; f面絕緣保護層，且該絕緣保護層中形成有多^ # 口以外路“線路層中作爲電性連接端之部分，並使得 該絕緣保護層得以填滿該貫穿孔之殘留空隙，藉以形成導 電通孔，以電性導接該芯層板表面之線路。之後，可" 絕緣保護層開口之電性連接端上形成另—金屬保護層，以 t形成電路板」抑或可將該表面形成有線路層之芯層板作為 核心電路板:，並透過線路增層製程而形成具有多層線路層 之電路板。 透過前述製法，本發明亦揭露一種電路板結構，係包 括：具至少-貫穿孔之芯層板，該貫穿孔孔壁具有一金屬 層；形成於該芯層板表面之線路層，該線路層係透過設於 該貫穿孔孔壁上之金屬層而相互電性連接；以及形成於該 貫穿孔孔壁金屬層上之金屬保護層。本發明之電路板結構 復包含有形成於該芯層板上且填充至該貫穿孔殘留空隙之 18418 8 1301734 絕緣保護層，且該絕緣保護層中形成有多數開口以外露出 該線路層中作爲電性連接端之部分；以及形成於該電性連 接端上之另一金屬保護層。 口此’本务明之電路板結構及其製法，主要係先於電 ，路板線路製程之前，在該芯層板之貫穿孔孔壁金屬層上形 —成層金屬保護層，以便後續對該芯層板表面之金屬層進 灯圖案化以形成線路時，可藉由該金屬保護層保護該貫穿 孔孔壁之金屬層，從而使得該貫穿孔孔壁之金屬層不被形 成線路所使用的蝕刻液過度侵蝕甚而導致斷裂，確保貫穿 孔孔壁之金屬層可靠性、導電性能，藉以提升製程良率， 俾可避免習知技術中由於例如乾膜或液態光阻之阻層蓋孔 性不良，導致蝕刻液滲漏至貫穿孔中侵蝕孔壁之金屬層， 亦或蝕刻液沖破該貫穿孔位置處之阻層，導致蝕刻液侵蝕 =壁之金屬層，造成孔壁之金屬層侵蝕過度甚至由於過度 $敍導致斷裂，使得孔壁之金屬層可靠性降低，甚至無法 φ電性連接芯層板表面之線路，造成製程良率降低。 ^此外，本發明係於芯層板貫穿孔孔壁之金屬層上預先 形成一金屬保護層，俾可於後續線路圖案化製程時，藉由 及金屬保護層保護該金屬層不受蝕刻液之侵蝕，因而可避 =白知技術中由於孔壁之金屬銅層厚度不易控制，使得孔 壁之金屬銅層因沒有保護而遭受過度侵蝕等缺失。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 18418 9 1301734 瞭解本發明之其他優點及功效。本發明亦可藉由 的具體實施例加以施行或應用， 9八不同 :基於不同的觀點與應用，在不悻::二 各種修I丰與變更。 甲下進行 請參閲第2A圖至第21圖’係詳細說 板結構之製法剖面示意圖。須注意 =路 之^、圖，僅以^方式說明本發明之電路板之 惟忒寺圖式僅顯示與本發明有關之元件，复 ,1301734 IX. Description of the invention: [Technical field to which the invention pertains] * The present invention relates to a circuit board structure and a method of manufacturing the same, and more particularly to a circuit board structure and a system for electrically connecting a layer (10) through a conductive via. law. ^ [Prior Art] The process of the two-layer circuit board is as shown in Figures 至A to E, first of all = for = for example, resin-bonded copper M (Resin coated c〇pper, Rcc) The laminate is 〇〇, and a plurality of through holes 1 (10) are drilled therein (as shown in FIG. 1A). Further, copper plating is performed to deposit a metal copper layer 1〇3 on the surface of the core layer 1 and the hole wall of the through hole 102 (as shown in Fig. 1). A resistive layer 104 such as a photoresist is overlaid on the core layer 100, and the resist layer 1〇4 is filled in the through hole 1〇2, and the resist layer 104 is patterned. A plurality of openings i 〇 4a (as shown in Fig. 1c) which partially expose the metal copper layer 103 underneath are formed. Then, the metal copper layer 1〇3 (not shown in FIG. id) that is not covered by the resist layer 104 is removed by etching, and then the resist layer 丨04 is removed, thereby forming a surface of the core layer. Formed with a patterned circuit layer Μ% (as shown in the figure below). Subsequently, a patterned solder resist layer can be formed on the core layer on which the wiring layer is formed, thereby forming a circuit board having a double layer wiring layer. In the above process, a metal copper layer having a certain thickness is formed on the surface of the core plate and the through hole thereof, and then a resist layer (not shown) such as a dry film or a photoresist is formed on the core plate. And exposing (Expes Sure), developing (Deve 10pment) and other processes to pattern, so that the resist layer is formed with a plurality of metal layers outside the opening of the 6 18418 1301734 opening to expose the core layer board, %11 Ve Pr°eeSS) to remove the portion of the metal layer that is not covered by the phase barrier to form a line.蜀=In the above-mentioned self-knowledge process, it is easy to have a resist layer such as dry film or green. When it is filled into the through hole of the core layer, the hole penetration is poor, resulting in the infiltration of the surname used in the process of the line drawing process. To the core plate through-hole, even the name of the metal copper layer on the wall of the hole, so that the liquid bite (four) through: the metal layer of the hole wall 'and the core plate on the table below, ::: : Hole: The electrical connection of the metal layer of the L wall affects the circuit board layer; The electricity f born p cattle low product yield. Or during the etching process, the resist layer covering the through-hole of the core layer is broken by the liquid to cause the through hole: the upper wall: the metal layer is etched and ruptured by the etching liquid, thereby causing the conductive layer between the circuit board layers. V is poor in electrical conductivity and product yield is reduced. , ° is not easy = in the 1 known technology, because the thickness of the metal layer through the hole wall " after the subsequent patterning process to form the line, in order to avoid 1: insect engraving excessively bite the through hole wall The metal layer makes the through hole: wall: the metal layer exceeds the design specification, and the fine pitch circuit structure cannot be provided', causing a bottleneck in the process. ° Therefore, how to provide a circuit board manufacturing method to avoid the lack of process yield reduction, complicated process, and poor reliability of the board layer and the reduction of electrical functions, etc. . In the light of the above-mentioned prior art, the main purpose of the present invention is to 7 18418 1301734 =:: heavy-duty wide-anti-structure and its manufacturing method to ensure the electrical function of the conductive structure between the circuit boards and Board process yield. In order to achieve the above and other purposes, the method of the present invention comprises: providing a core layer, and the structure of the road plate, and forming at least one of the layers in the core layer; the surface of the core layer and the through hole The hole wall is formed to cover a metal layer on the surface of the core plate with a resist layer, and the opening is formed with an opening to expose the metal layer of the hole wall; In the opening: 2: • sheath; and remove the barrier layer, and figure the slaughter (four): two on: a metal guarantee, ... the metallized edge of the four-layer board surface of the golden eyebrow: 乂: into a patterned circuit layer. Subsequently replenishing the core formed with the circuit layer; the f-side insulating protective layer, and the insulating protective layer is formed with a plurality of portions of the circuit layer as the electrical connection end, and the insulating protective layer is formed The residual space of the through hole is filled to form a conductive via hole to electrically connect the circuit of the surface of the core board. Thereafter, an additional metal protective layer can be formed on the electrical connection end of the opening of the insulating protective layer. The circuit board is formed by t. Alternatively, the core layer board having the circuit layer formed on the surface may be used as a core circuit board: and a circuit board having a plurality of circuit layers is formed through a line build-up process. The present invention also discloses a circuit board structure, comprising: a core layer having at least a through hole having a metal layer; a circuit layer formed on the surface of the core board, the circuit layer The two are electrically connected to each other through a metal layer disposed on the wall of the through hole; and a metal protective layer formed on the metal layer of the through hole. The circuit board structure of the present invention further comprises an 1818 8 1301734 insulating protective layer formed on the core layer and filled into the residual hole of the through hole, and the insulating protective layer is formed with a plurality of openings to expose the circuit layer as electricity. a portion of the sexual connection; and another metal protective layer formed on the electrical connection. The structure of the circuit board and its manufacturing method are mainly formed before the electric circuit and the circuit board circuit process, forming a metal protective layer on the metal layer of the through-hole hole wall of the core layer, so as to follow the core When the metal layer of the surface of the laminate is patterned into a lamp to form a line, the metal layer of the through-hole hole wall can be protected by the metal protective layer, so that the metal layer of the through-hole wall is not etched by the formed line. Excessive erosion of the liquid even leads to fracture, ensuring the reliability and electrical conductivity of the metal layer through the pore wall, thereby improving the process yield, and avoiding the poor porosity of the barrier layer due to, for example, dry film or liquid photoresist in the prior art. The etchant leaks into the metal layer of the through hole to erode the hole wall, or the etchant breaks through the resist layer at the position of the through hole, causing the etching solution to erode = the metal layer of the wall, causing excessive erosion of the metal layer of the hole wall or even due to Excessive $ narration leads to fracture, which makes the reliability of the metal layer of the hole wall lower, and even fails to electrically connect the circuit of the surface of the core plate, resulting in a decrease in process yield. In addition, the present invention pre-forms a metal protective layer on the metal layer of the core plate through the hole wall, and the metal layer can be protected from the etching liquid by the metal protective layer during the subsequent line patterning process. Erosion, and thus avoidable = in the white technology, because the thickness of the metal copper layer of the hole wall is not easy to control, the metal copper layer of the hole wall suffers from excessive erosion and the like due to lack of protection. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily appreciate the other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention can also be implemented or applied by the specific embodiments, which are different based on different viewpoints and applications, and are not limited to: Under the armor, please refer to Fig. 2A to Fig. 21 for a detailed sectional view of the structure of the plate structure. It should be noted that the circuit diagram of the circuit board of the present invention is only shown in the form of a ^, and only the components related to the present invention are shown.
Ab 月& 際實施時之態樣，其實際實施時之元件數:之::: 為一種選擇性之設計’且其元件佈局型態可 如第2Α及2Β圖所示’首先，提供一表面形成有全屬 層板2〇，該芯層板2〇亦可為-完成前處理之多 y电板或絕緣板。於本實施例之圖式中，該芯層板2〇 係由-絕緣層20。及形成於該絕緣層2。。表面之：屬薄層 2〇1所構成：復以機械或雷射鑽孔等方式於該芯層板2〇 I 鑽設至少-個貫穿孔2〇2(如第2B圖所示）。上述該絕緣層 7〇匕可為環氧樹脂（Epoxy resin)、聚乙醯胺（p〇iyimide)、 氰酯（Cyanate Ester)、玻璃纖維、雙順丁烯二酸醯亞胺/ 三氮阱^“贴^^丨加了^犯丨^打广或混合環氧樹脂盥玻 璃纖維之材質所製成，該金屬薄層2〇1 _般係以導電性較 佳之銅（Cu)為主，以作為訊號傳遞的導線材料，且該金^ 薄層201可先壓合或沉積於該絕緣層2〇〇上，或使用樹月胃旨 壓合銅箔（Resin coated copper，RCC)予以製作。本實施 18418 10 1301734 例採用一樹脂壓合銅箔（RCC)為例進行說明。 ^如第2C圖所示，接著，利用物理氣相沈積（pVD)、化 學氣相沈積（CVD)、無電電鍍或化學沈積等方式，例如濺鍍 (Sputtermg)、蒸鍍（Evap〇rati〇n)、電弧蒸氣沈積（Απ vapor deposition)、離子束濺鍍（I〇nbeam 、Ab month & implementation, the actual number of components in the implementation: it::: is a selective design 'and its component layout can be as shown in Figures 2 and 2' first, provide a The surface is formed with a full-size laminate 2〇, and the core laminate 2〇 can also be a multi-y-electric board or an insulating sheet that is pre-processed. In the drawings of this embodiment, the core layer 2 is made of an insulating layer 20. And formed on the insulating layer 2. . The surface is composed of a thin layer 2〇1: at least one through hole 2〇2 is drilled in the core layer 2〇I by mechanical or laser drilling (as shown in FIG. 2B). The insulating layer 7 can be an epoxy resin, a polypamine, a cyanate Ester, a glass fiber, a bis-succinimide/triazine ^"Paste ^^丨 added ^ 丨 丨 ^ wide or mixed epoxy resin 盥 glass fiber material, the thin metal layer 2 〇 1 _ like the best conductivity of copper (Cu), The wire material can be used as a signal transfer material, and the gold thin layer 201 can be first pressed or deposited on the insulating layer 2, or can be fabricated by using Resin coated copper (RCC). The embodiment of 18418 10 1301734 is described by taking a resin laminated copper foil (RCC) as an example. ^ As shown in Fig. 2C, followed by physical vapor deposition (pVD), chemical vapor deposition (CVD), electroless plating. Or chemical deposition, such as sputtering (Sputtermg), evaporation (Evap〇rati〇n), arc vapor deposition (离子π vapor deposition), ion beam sputtering (I〇nbeam,
锫射炫月史沈積（Laser ablat ion deposi t ion)、電浆促進之 $學氣相沈積或無電電鍍等，以於該芯層板2〇表面及其貫 穿孔202孔壁上形成一導電層（未圖示），俾藉由該導電層 作為電流傳導路徑，以在該芯層板2〇表面上以及於該貫穿 孔202孔壁上電鑛形成有一具預度厚度之金屬層2〇3。上 述該金屬層203之材料依實際操作之經驗，由於銅為成熟 之電鍍材料且成本較低，因此，該金屬層2〇3以由電鍍銅 所構成者為較佳，但非以此為限。 如弟2D圖所示，於該芯層板2〇表面之金屬層203上 覆蓋一阻層21，並進行圖案化製程，以使該阻層21形成 有開口 210，以外露出部分之金屬層2〇3。該阻層21可為 例如乾膜或液悲光阻等光阻層（ph〇t〇resi )，其係利用 印刷、旋塗或貼合等方式形成於該金屬層2〇3表面，再藉 由曝光（Exposure)、顯影（Devei〇pment)等方式加以圖案 化，而形成開口 210，該開口 21〇位置係對應該芯層板2〇 之貝牙孔202位置，以外露出該貫穿孔2〇2孔壁之金屬層 203。於本實施例中，該阻層之開口 21〇之尺寸係大於該貫 穿孔202之尺寸，以外露出該芯層板2〇表面之部分金屬 203。 11 18418 1301734 .如第2E圖所示，再對該芯層板2〇進行電鍍 (Electroplating)製程，藉由該金屬層2〇3具導電特性， 俾2行電鑛時可作為電流傳導路徑，以在對應芯層板2〇 貝牙孔202處且外露該阻層2丨之開口 中的金屬層 >上电鍍浴成一金屬保護層22，以藉由該金屬保護層 .保護該芯層板貫穿孔2〇2孔壁之金屬層2〇3，從而可提升 後續，成的導電通孔之電性連接品質及可靠度。上述該金 屬保護層22係可例如為鎳/金之雙層金屬之保護性金屬， 但非以鎳/金之雙層金屬層為限。 s尸此外，於本發明中亦可利用物理氣相沈積（PVD)、化 學氣相沈積（CVD)、無電電鍍或化學沈積等方式，以於外露 出5玄阻層開口 210中之金屬I 203上形成該金屬保護層 22 〇 如第2F圖所示，移除該阻層21。 如第2G圖所示，圖案化該芯層板2〇表面之金屬層2〇3 鲁及金屬薄層201，以形成一圖案化線路層2〇3a。其係可於 »玄心層板20上形成一例如乾膜或光阻之另一阻層（未圖 八）並、、、工過曝光（Exposure)、顯影（Devei〇pment)等製程 加以圖案化，以使該阻層形成有多數開口以外露出該芯層 板20之表面金屬層2〇3，俾經由蝕刻製程（subtractive process)以移除未為該阻層所覆蓋包括金屬層2〇3與金屬 薄層201部分，藉以形成一圖案化線路層2〇3a，以構成— 表面具有線路之電路板結構。由於本發明係於圖案化線路 層製程之前，在該貫穿孔202孔壁之金屬層203上預先形 18418 12 1301734 • ^一金屬保護層22,俾可於線路製程時藉由該金屬保護層 -22保護該貫穿孔202孔壁之金屬層203不受到蝕刻製^二 使用的蝕刻液之侵蝕，從而可提高孔壁金屬層2〇3之可靠 性、導電性能，以及電路板製程良率。 如第2H圖所示，於該形成有圖案化線路層203a之芯 '層板2G表面上形成絕緣保護層23，並使得魏緣保護^ * I3緊密填滿該芯層板貫穿孔202之殘留空隙，藉以形成曰導 • I =孔 2〇2a，再利用曝光（Exp〇SUre)、顯影（Development) 寺製程加以圖案化，以使該絕緣保護層23形成有開口 2刈 以2露出該圖案化線路層2〇3a中提供電路板用以與外界 作電性連接之電性連接端203b部分。 、如第21圖所示，復可於該芯層板上進行後續製程， 以在该電性連接端2〇3b外露表面形成一金屬保護層％， 例如為鎳/金之雙層金屬層，藉以供向外界作電性連接。 透過則述製法，本發明亦揭露一種電路板結構，係包 •鲁入二至夕貝牙孔2〇2之芯層板20，該貫穿孔孔壁具有 孟屬層，形成於該芯層板2〇表面之線路層2〇3a，該線 路f 203a係透過設於該貫穿孔2〇2孔壁上之金屬層2〇3 而電性連接；以及形成於該貫穿孔202孔壁金屬声2〇3上 =金屬保護層22。本發明電路板結構復包含有形成於該芯 ^板20上且填充至該貫穿孔2〇2殘留空隙之絕緣保護層 且ϋ亥、、，巴緣保蠖層23中形成有多數開口 230以外露出該 :复路層203a中作爲電性連接端2〇补部分；以及形成於該 电度連接端203b部分上之另一金屬保護層％。 18418 13 1301734 此外，亦可以利用第2G圖所示之該電路板作爲核心 -電路板（core circuit board)，以利用增層技術交互堆 疊絕緣層及線路層，並於該絕緣層中開設導電盲孔 (Conductive via)以供上下層線路之間電性連接，進而形 •成一具多層線路結構之電路板。 • 因此本發明之電路板結構及其製法主要係提供一形 成有至少一貫穿孔之芯層板，並於該芯層板表面及其貫穿 孔孔壁形成一金屬層，接著於該芯層板表面之金屬層上形 成阻層，且該阻層中相對於該貫穿孔位置形成有開口以露 出該貫穿孔孔壁之金屬層，俾於該阻層開口中之金屬層上 形成金屬保護層，其後復可移除該阻層，且對該芯層板表 面之金屬層進行圖案化以形成圖案化線路層，並藉由該貫 牙孔孔i之孟屬層電性連接該芯層板表面之圖案化線路 層0 相較於習知技術，本發明之電路板結構及#法，主 .要係先於線路製程之前在該芯層板之貫穿孔孔^全屬層 上形成-層金屬保護層，以便後續對該芯層板表面之^ 圖*化旧彡成線路時，可藉由該金屬保護層保護該 ==之金屬層，從而使得該貫穿孔孔壁之金屬層不 所使用的㈣液過度侵㈣至斷裂，以確保貫 之金屬層可靠性、導電性能，提升製程良率，俾 阻層蓋孔性不由於例如乾膜或液態光阻之 全屬声 a ¥致㈣液摩漏至貫穿孔中侵I虫孔壁之 B亦或餘刻液沖破該貫穿孔位置處之阻層，導致姓 18418 14 1301734 、刻液知钱孔壁之金屬層，造成孔壁之金屬層侵姓過度，甚 ，主導致斷裂，使得孔壁之金屬層可靠性降低，甚至無法有 效電性連接芯層板表面之線路，造成製程良率降低。 此外，本發明係於芯層板貫穿孔孔壁之金屬層上預先 /形成一金屬保護層，俾可於後續圖案化製程時，藉由該金 \ .屬保護層保護該金屬層不受蝕刻液之侵蝕，從而提昇孔壁 金屬層之可靠性及電性，因而可避免習知技術中由於孔壁 之金屬銅層厚度不易控制，使得孔壁之金屬銅層因沒有保 護而遭受過度侵姓，致使孔壁金屬層可靠性及製程良 低等問題。 上述實施例僅為例示性說明本發明之原理及i功 效，:非用於限制本發明。任何熟習此項技藝之;;士均可 f不違背本發明之精神及範嘴下，對上述實施例進行修 L所歹1此本發明之權利保護範圍，應如後述之中請專利範 鲁【圖式簡單説明】 弟1A圖至第1E圖係為習知雙層 意圖；以及 衣枉之糾面不 弟2 A圖至弟21圖係為本發明夕+ 佳告饮η '明之電路板結構之製法較 1土芦鈀例之剖面示意圖。 τ右孕乂 【主要元件符號說明】 100 芯層板 102 貫穿孔 103 金屬銅層 18418 15 1301734 103a 内層線路 -f H 1 1 塞孔材料 20 芯層板 200 絕緣層 ^ 201 金屬薄層 '202 貫穿子L • 203 金屬層 203a 圖案化線路層 • 203b 電性連接端 21 阻層 210 阻層開口 22 金屬保護層 23 絕緣保護層 230 絕緣保護層開 24 金屬保護層 16 18418Laser ablat ion deposi t ion, plasma-induced vapor deposition or electroless plating, etc., to form a conductive layer on the surface of the core plate 2 and the hole wall of the through hole 202 (not shown), by using the conductive layer as a current conduction path, to form a metal layer of a predetermined thickness on the surface of the core layer 2 and on the hole wall of the through hole 202. . The material of the metal layer 203 is based on the experience of practical operation. Since the copper is a mature electroplating material and the cost is low, the metal layer 2〇3 is preferably composed of electroplated copper, but not limited thereto. . As shown in FIG. 2D, a metal layer 203 on the surface of the core layer 2 is covered with a resist layer 21, and a patterning process is performed to form the resist layer 21 with an opening 210 and an exposed portion of the metal layer 2 〇 3. The resist layer 21 may be a photoresist layer such as a dry film or a liquid-resistance photoresist, which is formed on the surface of the metal layer 2〇3 by printing, spin coating or lamination. It is patterned by exposure, development, or the like to form an opening 210 which is positioned corresponding to the position of the bead hole 202 of the core layer 2, and the through hole 2 is exposed. 2 hole wall metal layer 203. In the embodiment, the opening 21 of the resist layer is larger than the size of the through hole 202, and a part of the metal 203 of the surface of the core plate 2 is exposed. 11 18418 1301734 . As shown in FIG. 2E , the core layer plate 2 is subjected to an electroplating process, and the metal layer 2 〇 3 has a conductive property, and the 行 2 row of electric ore can be used as a current conduction path. The metal layer is electroplated to form a metal protective layer 22 at a metal layer in the opening corresponding to the core plate 2 and exposed to the barrier layer 202 to protect the core layer by the metal protective layer. The metal layer 2〇3 of the hole wall of the through hole 2〇2 can improve the electrical connection quality and reliability of the subsequent conductive via. The metal protective layer 22 may be, for example, a protective metal of a nickel/gold double-layer metal, but is not limited to a nickel/gold double-layer metal layer. In addition, in the present invention, physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating or chemical deposition may be used to expose the metal I 203 in the opening 5 of the mystery barrier layer. The metal protective layer 22 is formed thereon, as shown in FIG. 2F, and the resist layer 21 is removed. As shown in FIG. 2G, the metal layer 2〇3 and the thin metal layer 201 on the surface of the core layer 2 are patterned to form a patterned wiring layer 2〇3a. The system can form a resist layer (not shown in FIG. 8), such as a dry film or a photoresist, on the X-shaped core layer 20, and can be patterned by exposure, development, and development (Devei〇pment). So that the resist layer is formed with a plurality of openings to expose the surface metal layer 2 〇 3 of the core layer 20, and is removed by a subtractive process to remove the metal layer 2 〇 3 not covered by the resist layer A portion of the thin metal layer 201 is formed to form a patterned wiring layer 2〇3a to constitute a circuit board structure having a surface. Since the present invention is prior to the process of patterning the wiring layer, a metal protective layer 22 is pre-formed on the metal layer 203 of the via hole of the through hole 202, and the metal protective layer can be used in the wiring process. The metal layer 203 protecting the hole wall of the through hole 202 is not eroded by the etching liquid used for the etching process, thereby improving the reliability, the electrical conductivity, and the circuit board process yield of the hole wall metal layer 2〇3. As shown in FIG. 2H, an insulating protective layer 23 is formed on the surface of the core 'layer 2G on which the patterned wiring layer 203a is formed, and the Wei edge protection ^ * I3 closely fills the residual of the core layer through hole 202. The voids are formed to form the conductive layer. I = the hole 2〇2a, and then patterned by exposure (Exp〇SUre) and development (Development) temple process, so that the insulating protective layer 23 is formed with an opening 2 to expose the pattern. The circuit layer 2〇3a provides a portion of the electrical connection end 203b for the circuit board to be electrically connected to the outside. As shown in FIG. 21, a subsequent process is performed on the core layer to form a metal protective layer % on the exposed surface of the electrical connection end 2〇3b, for example, a nickel/gold double layer metal layer. In order to make electrical connections to the outside world. Through the method of description, the present invention also discloses a circuit board structure, which is a core layer 20 of a 2 〇 2 hole, which has a Meng layer, and is formed on the core layer. a circuit layer 2〇3a of the surface, wherein the line f 203a is electrically connected through the metal layer 2〇3 disposed on the hole of the through hole 2〇2; and the metal sound formed on the hole wall of the through hole 202 〇3 upper = metal protective layer 22. The circuit board structure of the present invention further includes an insulating protective layer formed on the core board 20 and filled in the gaps of the through holes 2〇2, and the plurality of openings 230 are formed in the margin sealing layer 23 Exposed: the rectifying layer 203a serves as a complementary portion of the electrical connection end 2; and another metal protective layer % formed on the portion of the electrical connection end 203b. 18418 13 1301734 In addition, the circuit board shown in FIG. 2G can also be used as a core circuit board to alternately stack the insulating layer and the circuit layer by using a build-up technique, and to establish a conductive blind in the insulating layer. Conductive via is used to electrically connect the upper and lower lines, and then form a circuit board with a multi-layer circuit structure. The circuit board structure of the present invention and the method of manufacturing the same are mainly to provide a core layer formed with at least a uniform perforation, and to form a metal layer on the surface of the core layer and the through hole wall, and then on the surface of the core layer a resist layer is formed on the metal layer, and an opening is formed in the resist layer relative to the through hole to expose the metal layer of the through hole wall, and a metal protective layer is formed on the metal layer in the opening of the resist layer. Afterwards, the resist layer can be removed, and the metal layer on the surface of the core layer is patterned to form a patterned circuit layer, and the surface of the core layer is electrically connected by the Meng layer of the via hole Compared with the prior art, the circuit board structure and the method of the present invention form a layer metal on the through-hole of the core layer before the line process. Protecting the layer so that the metal layer of the == metal layer can be protected by the metal protective layer when the surface of the core layer is subsequently formed into a circuit, so that the metal layer of the through-hole wall is not used. (4) liquid over-invasion (four) to break to ensure that the gold Layer reliability, electrical conductivity, improve process yield, and the porosity of the barrier layer is not due to the fact that the dry film or liquid photoresist is all sounds a (4) liquid leakage to the through hole in the B hole Or the residual liquid breaks through the resistance layer at the position of the through hole, causing the metal layer of the wall of the hole to be known as 18418 14 1301734, causing the metal layer of the hole wall to invade the surname, and even the main causes the fracture, so that the hole wall The reliability of the metal layer is reduced, and even the circuit of the surface of the core board cannot be electrically connected, resulting in a decrease in process yield. In addition, the present invention pre-forms a metal protective layer on the metal layer of the core plate through the hole wall, and the metal layer can be protected from etching by the gold protective layer during the subsequent patterning process. The erosion of the liquid enhances the reliability and electrical properties of the metal layer of the hole wall, thereby avoiding the difficulty in controlling the thickness of the metal copper layer of the hole wall in the prior art, so that the metal copper layer of the hole wall is excessively invaded due to lack of protection. , resulting in the reliability of the metal layer of the hole wall and the low process. The above embodiments are merely illustrative of the principles and advantages of the present invention and are not intended to limit the invention. Anyone who is familiar with the art; can not be in violation of the spirit and scope of the present invention, the above embodiment is modified. The scope of protection of the present invention should be as described later. [Simple diagram of the diagram] The 1A to 1E diagrams of the brothers are the two-layered intentions of the well-known; and the corrections of the clothes are not brothers 2 A map to the brother 21 is the invention of the present day + the good drink η 'Ming's circuit board The structure of the structure is a schematic diagram of the cross section of the soil. τ右孕乂 [Main component symbol description] 100 core plate 102 through hole 103 metal copper layer 18418 15 1301734 103a inner layer line -f H 1 1 plug hole material 20 core layer board 200 insulation layer ^ 201 metal thin layer '202 through Sub L • 203 Metal layer 203a Patterned wiring layer • 203b Electrical connection 21 Resistive layer 210 Resistive layer opening 22 Metal protection layer 23 Insulation protection layer 230 Insulation protection layer Open 24 Metal protection layer 16 18418