1337398 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板結構及其製作方法， '匕 一種適用於維持電性連接墊及金屬保護層結構完整尤扎 5基板及其製作方法。 心•封裝 【先前技術】1337398 IX. Description of the Invention: [Technical Field] The present invention relates to a package substrate structure and a method of fabricating the same, and a method for maintaining an electrical connection pad and a metal protection layer structure . Heart • Packaging [Prior Art]
10 15 20 電子產業相關技術快速提昇，隨著電子產品輕小 勢’電路板或半導體晶片封裝基板製造業者亦面臨著制=趨 的許多關鍵處。其中，於在電路板或基板表面上會形 干由導電線路延伸之電性連接塾，以作為電子訊號或電源右 傳輸遞之構成用，而通常在電路板或基板之電性連接势之之 面，會覆上一鎳/金層（先形成鎳層，再形成金層卜作為元^ 相互間之電性連接。該等電性連接塾，如半導體晶片封裝美 板之打線料’即㈣體表面覆上一層鎳'/金層，於進^曰 片封裝打金線時，金線與基板之打線墊皆為金屬金之材質， 而有利於兩者完成電性耦合結構。 貝 一般而言，進行打線接合方式的封裝基板結構，係利 用封裝基板上的打線焊墊經由打線而與晶片電性連接。此 種封裝基板在製作打線焊墊的製程係請參考圖以至1E。首 =，如圖1A所示，提供一基板n，其係可進行線路圖案化 製裎（Circuit patterning pr〇cesses)，形成有電鍍導通孔！ η 以及一圖案化之線路層η2，線路層U2位於基板之上表面 113與下表面llb，上表面Ha之線路層112係電性導通至基 5 1337398 10 15 20 板1 1周緣之電鍍導線n 3 ;㈣導通孔π丨係貫穿基板Η， 並電性導通上表面lla與下表面llb之線路層⑴，並且在此 基板Η之上表面lla與下表面Ilb形成有—圖案化之防焊層 a’此防焊層12於絲^之上表面lla與下表snb分別形 成^複數個防焊層開孔丨21，丨22，並顯露出部分線路層11厂 接著，如圖1B所示，於基板Η之上表面113形成有一圖案化 之阻層丨3,此阻層13於對應於防焊層開孔12丨處形成有阻層 開孔13 1 ’並經由曝光及顯影顯露出防烊層開孔u丨内部分 之線路層1丨2。然後，如圖丨c所示，於基板丨丨上表面丨丨a顯 露於阻層開孔m内之線路層112表面，藉由電鑛導線⑴提 供電流傳導以進行電鍍’形成一金屬保護層丨4 a (例如先形成 鎳層，再形成金層），並且於基板n下表面Ha顯露於防焊層 開孔1 22内之線路層丨丨2表面，經由電鍍導通孔丨丨丨傳導電 流，以電鍍形成金屬保護層丨4b。繼之’如圖山所示，移= 此阻層13。接著’如圖1E所示，將此基板丨丨置於一驗性蝕 刻的裝置中，以鹼性蝕刻液去除在基板丨丨上表面顯露於 防焊層開孔121且未覆有金屬保護層14a之線路層丨12，而與 電鍍導線113形成斷路。在此，在基板丨丨上表面iu的金屬 保護層14a其下之線路層U2，係作為打線焊墊"A用。其 中’打線焊塾1 14係可經由打線而與晶片冑極電性連接。 然而，前述在去除顯露於防焊層開孔且未覆有金屬保 護層之線路層日夺’因使用驗性钱刻液的關係，而產生側姓 的現象，進而蝕刻掉位於金屬保護層下方一部份的打線焊 墊。在此，一般在製作此段封裝基板的製程中，係不使用 6 1337398 =刻液’其主要⑽於酸性㈣液會對金屬保護層 =成又飯作用，而鹼性㈣液則不會侵歸屬保護層。但 疋使用驗杜钱刻液的方法仍會因線路層側姓’使得金屬 保護層突出於打線谭势，甚至造成金屬保護層崩解，無法 完全形成於打緩,11；拙_ Μ主二 受影響。’的表面，致使封裝基板的電性品質大 10 15 20 卜 奴右以蝕刻方式進行線路圖案化製程時，均 :用：性蝕刻液，而在後續形成打線焊墊上之金屬保護層 版而餘刻去除在基板上表面顯露於防焊層開孔且未覆有 金屬保4層之線路層，此時，若使用鹼性蝕刻液，必須另 刻裝置，不但造成成本的浪費，而且亦複雜化了 封1¾•基板的製程6 【發明内容】 2於習知之缺點，本發明係提供一種封裝基板結 I 基板、一圖案化之防垾層以及-金屬保護層。 土板具有-上表面、_下表面、複數電料通孔與一圖案 化之線路層’此圖案化之線路層係形成於基板之上表面盘 下表面’電錄導通孔係貫穿於基板之上表面與下表面，^ 電性導通上表面與下表面之線路屏 峪層S案化之防焊層係覆 成二=上：下表面’且位於基板之上表面之防焊層形 成有複數個防焊層開孔，並顯露出部分之線路層， 電性連接H電性連接Μ與該電鍍導通孔電性 連接。金屬保護層係形成於該第一電性連接墊之部分表 7 1337398 面，且該第-電性連接墊之末端係外露於該金屬保護層。 本發明的封裝基板結構中，復包括基板下表面之防焊 層形成有複數個防焊層開孔，並顯露出部分之線路層以作 為弟二電性連接塾，且第二電性連接塾與電鑛導通孔電性 ^ °此外’第二電性連接誓表面亦復可形成有金屬保護 本發明之金屬保護層的材料係為金、鎳、鈀、銀、錫、 錄繞 '鉻/鈦、鎳/金、鈀/金、鎳/鈀/金、所組群組其中之 10 15 20 者奴k地金屬保護層的材料可為錄/金（先 形成金層）。 行曰丹 本發明之線路層中，其使用之材㈣可為銅、鋅 '終、 鈇、鋼/絡合金及錫/紐合金所組群組其中之一者 為鋼。 认丨土匕_! 依據上述本發明之封裝基板結構例如可由下述但 ㈣此之步驟製作封裝基板：首先，提供一基板，其具有 表面T ^ ^、複數電料通孔以及—圖案化之線 路層，此圖案化線路層係形成於基板之上表面與下表面， 上表面之線路層係電性導通至美 導通孔1料線，電鍵 =孔係貝穿於基板之上表面與下表面’並電性導通上表 7下表面之線路層。接著，於基板之上表面及下表面形 圖案化之防焊層，且防焊層於基板之上表面 數個防焊層開孔，並噸 有複 卫.‘、貝路出邛刀線路層。然後，於基板之 ^形成-圖案化之第一阻層，該第—阻層於對應於防 層開孔處形成有第—開孔’並覆蓋住防焊層開孔内一部 8 1337398 =之線路層。繼之’於顯·露於第_開孔内之線路層表面， :由電料線提供電流傳導以進行電銀，形成—金屬保護 曰^，後’移除I阻層。接著，於基板上表面及下表面 七成弟二阻層’並於上表面進行圖案化製程，於對應於基 板上表面之防焊層開礼處形成有—第二開礼，#第二開孔 係顯露防焊層開孔内之線路層，@不顯露金屬保護層。隨 之：移除顯露於第二開孔内之線路層，以與該電鍍導線形 成斷路’且於防焊層開孔内未被移除之線路層係作為第一 電性連接墊。最後，移除第二阻層。 10 本發明之製作方法令，復包括此防焊層於基板之下表 面形成有複數個防焊層開孔，並顯露出線路層，以作為第 -電性連接③。此外’冑可包括於此等第二電性連接塾表 面電鍍形成金屬保護層。 15 本發明之製作方法中，第-阻層及第二阻層的材料係 可分別為乾膜或液態光阻。 此外’本發明之製作方法中，移除顯露於第二開孔内 之線路層較佳係以蝕刻之方式移除。 在本發明所述之基板較佳係為已完成前段線路製程之 兩層板或多層電路板之其中—種。 20 本發明的封裝基板結構較佳係可為一打線式封裝基 板。因此，本發明所述之第—電性連接塾較㈣打線焊塾， 係:經由-打線而與晶片電性連接。第二電性連接塾較佳 為焊球塾’係可經由-焊料球而與外部電子裝置（例如 電路板）電性連接。 9 因此’本發明的萝' 保護第—電性連接㈣效果+’係使用兩次阻層以達到 因為使用兩次阻層的方/叮亚且本發明的封裝基板上’ 第一電性連接墊t " 了使侍金屬保護層完全形成於 發明ηίί而不致導致金屬保護層崩解。故，本 ㈣可維持封裝基板電性品質，提高產品的良率。 【實施方式】 :乂下係藉由特定的具體實施例說明本發明之實施方 4¾此技#之人士可由本說明書所揭示之内容輕易地 10 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不恃離本發明之精神下進行各 種修飾與變更。 本發明之實施例中該些圖式均為簡化之示意圖。惟該 15 2圖式僅顯示與本發明有關之元件，其所顯示之元件非為 灵際貫苑B寸之態樣，其實際實施時之元件數目、形狀等比 • 例為一選擇性之設計，且其元件佈局型態可能更複雜。 貫施例 請參考圖2A至2F與圖3A至3F，其中圖2A至2F係為製作 2〇 本發明封裝基板流程剖視圖，圖3A至3F係為製作本發明封 裝基板之打線焊墊上視圖。 首先’如圖2A及3A所示，提供一基板21，其例如可使 用已完成前段線路製程之兩層板、或多層電路板之其中一 種。在此基板21上具有一上表面21a、一下表面21b、複數 10 1337398 J 電鍍導通孔2 Π以及一圖案化之線路層2 1 2。在此，圖案化 線路層212係形成於基板之上表面21a與下表面21b，上表面 • 2 1 a之線路層2丨2係電性導通至基板2 1周緣之電鍍導線 213，電鑛導通孔2Π係貫穿於基板21之上表面2U與下表面 5 21b，並電性導通上表面21a與下表面21b之線路層2丨2。此 外，在基板21之上表面2U及下表面21b形成一圖案化之防 丈f·層22，此防烊層22於基板21之上表面2丨a形成有防焊層開 孔2 2 1 ’並顯滅出部分線路層212。同時，防焊層2 2於基板 • 215之下表面21a亦形成有防焊層開孔222，並顯露出部分線 10 路層212以作為焊球墊2丨4。 於此，在基板21上表面21a與下表面2沁的線路層212使 用的材料係為銅、鎳、鉻、鈦、銅/鉻合金及錫/鉛合金所組 群組其中之一者。在本實施例中係使用銅。電鍍導通孔211 的週緣亦使用與線路層2丨2相同的材料並電性連接基板21 15上表面2丨3與下表面21b的線路層212。此外，電鍍導線213 亦使用與線路層212相同之材料。 # 接著，如圖2B及3B所示，於基板2丨之上表面21a形成一 圖案化之第一阻層23，此第一阻層23於對應於防焊層開礼 221處以曝光以及顯影形成有第一開孔231，並覆蓋住防焊 20層開孔221内一部分之線路層212。其中，此第一阻層23使 用的材料例如為乾膜或液態光阻。 然後，如圖2C及3C所示，於顯露於第一開孔231内之線 路層212表面’藉由電料線213傳導電流，以電錢方式形 成-金属保護層24a。同時，在基心下表面加顯露於防 11 1337398 J 焊層開孔222内之焊球墊214表面，藉由電鑛導通孔2丨1電性 導通上表面21 a與下表面21b的線路層212,以電鍍的方式形 成金屬保護層24b。在此，金屬保護層24b使用的材料為金、 錄、鈀、銀、錫、鎳/!巴、鉻/鈦、鎳/金、鈀/金、錄/纪/金、 5所。且群組其中之一者。在本實施例中係使用鎳/金（先形成鎳 層，再形成金層）。 繼之，如圖2D及3D所示，於基板21上表面2丨3移除此第 一阻層22。 § 然後，如圖2E及3E所示，於基板21上表面2丨3及下表面 10 2丨b形成第二阻層25，並於上表面2丨3進行圖案化製程，於 對應於基板2 1上表面之防焊層開孔22丨處形成有一第二開 孔25 1，該第二開礼25丨係顯露防焊層開孔22丨内之線路層 2 1 2，而不顯露金屬保護層24a，24b。在此’第二阻層25覆葚 住金屬保護層24a，24b，係主要用以保護金屬保護層 13 24a，24b，使其不被後續製程中之蝕刻液侵蝕傷害。 接著，如圖2F及3F所示，利用餘刻液，尤指酸性姓刻 φ 液移除顯露於第二開孔25 1内之線路層212，以與電鍍導線 21 3形成斷路，且於防焊層開孔22丨内未被移除之線路層2 u 係作為打線焊墊215用，並接著移除第二阻層25。因此，完 20成本發明之封裝基板。此步驟之轴刻液係可沿用一般以敍 刻方式進行線路圖案化製程時，使用之酸性蝕刻液，但本 發明亦可另外設置鹼性蝕刻裝置，使用鹼性蝕刻液’而藉 由第二阻層保護金屬保護層，進行蝕刻製程。本發明若排 除設置蝕刻裝置的顧慮，無論使用酸性或鹼性蝕刻液，均 12 1337398 可達成相同效果，10 15 20 The technology related to the electronics industry is rapidly improving. As the electronic products are light and small, the manufacturers of circuit boards or semiconductor chip package substrates are also facing many key points of the system. Wherein, an electrical connection port extending from the conductive line is formed on the surface of the circuit board or the substrate to serve as an electronic signal or a power source for transmission, and is usually electrically connected to the circuit board or the substrate. The surface is covered with a nickel/gold layer (the nickel layer is formed first, and then the gold layer is formed as the electrical connection between the elements). The electrical connection is, for example, the wiring material of the semiconductor chip package, ie (4) The surface of the body is covered with a layer of nickel '/gold. When the gold wire is packaged, the wire pads of the gold wire and the substrate are made of metal gold, which is beneficial to the two to complete the electrical coupling structure. In other words, the package substrate structure of the wire bonding method is electrically connected to the wafer by wire bonding pads on the package substrate. The manufacturing process of the package substrate in the wire bonding pad is as shown in FIG. 1E. As shown in FIG. 1A, a substrate n is provided, which can be patterned by circuit patterning, formed with a plated via hole η and a patterned circuit layer η2, and the circuit layer U2 is located on the substrate. Upper surface 113 and the lower surface 11b, the circuit layer 112 of the upper surface Ha is electrically connected to the plating wire n 3 of the periphery of the base 1 1337398 10 15 20 plate 1; (4) the through hole π丨 penetrates the substrate Η, and electrically conducts the upper surface The circuit layer (1) of the lower surface 11b and the lower surface 11b are formed with a patterned solder resist layer a' on the upper surface 11b and the lower surface 11b. The solder resist layer 12 is on the upper surface 11a of the wire and the following table snb Forming a plurality of solder mask opening openings 21, 22, respectively, and revealing a portion of the wiring layer 11. Next, as shown in FIG. 1B, a patterned resist layer 3 is formed on the upper surface 113 of the substrate. The resist layer 13 is formed with a resist opening 13 1 ' corresponding to the solder resist opening 12 并 and exposes the wiring layer 1 丨 2 of the inner portion of the tamper-proof opening u through exposure and development. As shown in 丨c, the upper surface 丨丨a of the substrate is exposed on the surface of the circuit layer 112 in the opening m of the resist layer, and current conduction is provided by the electric ore wire (1) for electroplating to form a metal protective layer 丨4a ( For example, a nickel layer is formed first, and then a gold layer is formed), and a line on the lower surface Ha of the substrate n is exposed in the opening of the solder resist layer 1 22 Layer 2 surface, conducting current through the plated via hole to form a metal protective layer 丨4b by electroplating. Following 'as shown in Fig. Mountain, shift = the resist layer 13. Then, as shown in Fig. 1E, The substrate is placed in a device for verifying etching, and the circuit layer 丨12 exposed on the upper surface of the substrate and exposed to the solder mask opening 121 and not covered with the metal protective layer 14a is removed by an alkaline etching solution. The electroplated wire 113 forms an open circuit. Here, the circuit layer U2 under the metal protective layer 14a on the upper surface iu of the substrate is used as a wire bonding pad. The wire bonding wire 14 can be connected by wire bonding. Electrically connected to the wafer. However, in the above-mentioned removal of the circuit layer exposed to the opening of the solder resist layer and not covered with the metal protective layer, the phenomenon of the side surname is generated due to the use of the test capital engraving, and the etching is performed under the metal protective layer. A part of the wire bonding pad. Here, generally, in the process of fabricating the package substrate, 6 1337398 = engraving is not used. The main (10) acid (four) liquid will act on the metal protective layer = and the alkaline (four) liquid will not invade. Attributable to the protective layer. However, the method of using the Dudu money engraving method will still cause the metal protective layer to protrude from the line and the metal layer to disintegrate and even form a slowdown in the metal layer. 11; 拙 _ Μ 二 2 Affected. The surface of the package causes the electrical quality of the package substrate to be large. 10 15 20 When the circuit is patterned by etching, the etching process is performed by using a etchant liquid and subsequently forming a metal protective layer on the wire bonding pad. The circuit layer on the upper surface of the substrate is exposed on the surface of the solder resist layer and is not covered with the metal layer. In this case, if an alkaline etching solution is used, the device must be separately installed, which not only causes waste of cost, but also complicates Process for sealing a substrate 1 [Disclosed] 2 In a conventional disadvantage, the present invention provides a package substrate I substrate, a patterned anti-corrugated layer, and a metal protective layer. The earth plate has an upper surface, a lower surface, a plurality of electric material through holes and a patterned circuit layer. The patterned circuit layer is formed on the lower surface of the upper surface of the substrate. The electrical recording via hole penetrates through the substrate. The upper surface and the lower surface, the conductive layer of the upper surface and the lower surface of the circuit layer is electrically covered with a solder mask layer of the upper surface and the lower surface and the solder resist layer on the upper surface of the substrate is formed with a plurality of solder layers The solder resist layer is opened, and a part of the circuit layer is exposed, and the electrical connection H is electrically connected to the plating via. A metal protective layer is formed on a surface of the first electrical connection pad, the surface of the first electrical connection pad, and the end of the first electrical connection pad is exposed to the metal protection layer. In the package substrate structure of the present invention, the solder resist layer including the lower surface of the substrate is formed with a plurality of solder mask opening, and a part of the circuit layer is exposed to serve as a second electrical connection, and the second electrical connection is The electrical conductivity of the conductive hole of the electric mine is further improved. The second electrical connection is also formed by metal. The material of the metal protective layer of the present invention is gold, nickel, palladium, silver, tin, and coiled 'chrome/ Titanium, nickel/gold, palladium/gold, nickel/palladium/gold, and the material of the 10 15 20 metal protective layer of the group can be recorded/gold (formed gold layer first).曰 曰 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本According to the above-described package substrate structure of the present invention, for example, the package substrate can be fabricated by the following steps: (4) First, a substrate having a surface T ^ ^, a plurality of dielectric vias, and a patterned pattern is provided. a circuit layer, the patterned circuit layer is formed on the upper surface and the lower surface of the substrate, and the circuit layer on the upper surface is electrically connected to the through-hole 1 material line, and the electric key is inserted on the upper surface and the lower surface of the substrate 'And electrically conduct the circuit layer on the lower surface of Table 7. Then, the solder mask layer is patterned on the upper surface and the lower surface of the substrate, and the solder resist layer is opened on the surface of the substrate by a plurality of solder mask layers, and the utility model has a resurrection. . Then, in the first resist layer formed and patterned on the substrate, the first resist layer is formed with a first opening corresponding to the opening of the protective layer and covers a portion of the opening of the solder resist layer 8 1337398 = The circuit layer. Following the surface of the circuit layer in the _ opening, the current is conducted by the electric wire to perform electro-silver, forming a metal protection ,^, and then removing the I-resist layer. Then, on the upper surface and the lower surface of the substrate, a pattern of the second resist layer is formed on the upper surface, and a patterning process is formed on the upper surface of the substrate, and a second opening ceremony is formed on the opening of the solder resist layer corresponding to the upper surface of the substrate, #第二开The hole system reveals the circuit layer in the opening of the solder mask, @ does not reveal the metal protective layer. Subsequently, the circuit layer exposed in the second opening is removed to form a circuit breaker with the plated wire and the circuit layer not removed in the opening of the solder mask is used as the first electrical connection pad. Finally, the second resist layer is removed. According to the manufacturing method of the present invention, the solder resist layer is formed with a plurality of solder resist opening openings on the surface of the substrate, and the wiring layer is exposed to serve as the first electrical connection 3. In addition, the second electrical connection may be included to form a metal protective layer. In the manufacturing method of the present invention, the materials of the first resist layer and the second resist layer may be dry films or liquid photoresists, respectively. Further, in the manufacturing method of the present invention, the removal of the wiring layer exposed in the second opening is preferably removed by etching. Preferably, the substrate of the present invention is one of a two-layer board or a multi-layer circuit board which has completed the front-end line process. 20 The package substrate structure of the present invention is preferably a wire-wound package substrate. Therefore, the first electrical connection according to the present invention is electrically connected to the wafer via the --wire bonding wire. The second electrical connection, preferably solder ball, is electrically connected to an external electronic device (e.g., a circuit board) via a solder ball. 9 Therefore, the 'inventive of the present invention' protects the first electrical connection (four) effect + 'the use of two resist layers to achieve the first electrical connection on the package substrate of the present invention because of the use of two barrier layers. Pad t " The metal protective layer is completely formed in the invention ηίί without causing the metal protective layer to disintegrate. Therefore, this (4) can maintain the electrical quality of the package substrate and improve the yield of the product. [Embodiment] The following describes the other advantages and effects of the present invention by those skilled in the art from a specific embodiment. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention. The drawings in the embodiments of the present invention are simplified schematic diagrams. However, the figure 15 2 only shows the components related to the present invention, and the components shown therein are not in the form of the spirit of the B-inch, and the number and shape of the components in the actual implementation are as an option. Design, and its component layout type may be more complicated. 2A to 2F and Figs. 3A to 3F, wherein Figs. 2A to 2F are cross-sectional views showing a process for fabricating a package substrate of the present invention, and Figs. 3A to 3F are top views of a wire bonding pad for fabricating the package substrate of the present invention. First, as shown in Figs. 2A and 3A, a substrate 21 is provided which can be used, for example, of a two-layer board which has completed the front-end line process, or one of a plurality of circuit boards. The substrate 21 has an upper surface 21a, a lower surface 21b, a plurality of 10 1337398 J electroplated vias 2 Π, and a patterned wiring layer 2 1 2 . Here, the patterned circuit layer 212 is formed on the upper surface 21a and the lower surface 21b of the substrate, and the circuit layer 2丨2 on the upper surface of the substrate is electrically connected to the plating wire 213 of the periphery of the substrate 2, and the electric ore is turned on. The hole 2 is formed through the upper surface 2U and the lower surface 51b of the substrate 21, and electrically connects the circuit layer 2丨2 of the upper surface 21a and the lower surface 21b. In addition, a patterned anti-foil layer 22 is formed on the upper surface 2U and the lower surface 21b of the substrate 21. The anti-corrosion layer 22 is formed with a solder resist opening 2 2 1 ' on the upper surface 2丨a of the substrate 21. A portion of the circuit layer 212 is also extinguished. At the same time, the solder resist layer 2 2 is also formed with a solder resist opening 222 on the lower surface 21a of the substrate 215, and a portion of the wiring layer 212 is exposed as the solder ball pad 2丨4. Here, the material used for the wiring layer 212 on the upper surface 21a and the lower surface 2 of the substrate 21 is one of a group of copper, nickel, chromium, titanium, copper/chromium alloy and tin/lead alloy. Copper is used in this embodiment. The periphery of the plating via 211 also uses the same material as the wiring layer 2丨2 and electrically connects the wiring layer 212 of the upper surface 2丨3 and the lower surface 21b of the substrate 21 15 . Further, the plating wire 213 is also made of the same material as the wiring layer 212. # Next, as shown in FIG. 2B and FIG. 3B, a patterned first resist layer 23 is formed on the upper surface 21a of the substrate 2, and the first resist layer 23 is formed by exposure and development corresponding to the solder mask opening 221 There is a first opening 231 and covers a portion of the circuit layer 212 of the solder resist 20 layer opening 221 . The material used for the first resist layer 23 is, for example, a dry film or a liquid photoresist. Then, as shown in Figs. 2C and 3C, the surface of the line layer 212 exposed in the first opening 231 is conducted by the electric wire 213 to form a metal protective layer 24a by electricity. At the same time, the surface of the solder ball pad 214 exposed in the opening 222 of the 11 1337398 J solder layer is exposed on the lower surface of the base core, and the circuit layer of the upper surface 21 a and the lower surface 21 b is electrically connected through the electric conduction via 2 丨 1 . 212, forming a metal protective layer 24b by electroplating. Here, the material used for the metal protective layer 24b is gold, ruthenium, palladium, silver, tin, nickel/! bar, chromium/titanium, nickel/gold, palladium/gold, ruthenium/gold, and five. And one of the groups. In this embodiment, nickel/gold is used (a nickel layer is formed first, and a gold layer is formed). Subsequently, as shown in Figs. 2D and 3D, the first resist layer 22 is removed on the upper surface 2丨3 of the substrate 21. Then, as shown in FIGS. 2E and 3E, a second resist layer 25 is formed on the upper surface 2丨3 and the lower surface 10 2丨b of the substrate 21, and a patterning process is performed on the upper surface 2丨3 to correspond to the substrate 2 A second opening 25 is formed in the upper surface of the solder resist layer opening 22, and the second opening 25 is exposed to the circuit layer 2 1 2 in the solder resist opening 22 without revealing metal protection. Layers 24a, 24b. Here, the second resist layer 25 covers the metal protective layers 24a, 24b mainly for protecting the metal protective layers 13 24a, 24b from being attacked by the etching liquid in the subsequent process. Next, as shown in FIG. 2F and FIG. 3F, the circuit layer 212 exposed in the second opening 25 1 is removed by using a residual liquid, especially an acid surname φ liquid, to form an open circuit with the plating wire 21 3 , and is prevented. The circuit layer 2 u which has not been removed in the solder layer opening 22 is used as the bonding pad 215, and then the second resist layer 25 is removed. Therefore, the package substrate of the invention is completed. The axial engraving liquid of this step may use an acidic etching liquid which is generally used in the line patterning process, but the present invention may additionally provide an alkaline etching device, using an alkaline etching solution and using the second etching solution. The resist layer protects the metal protective layer and performs an etching process. In the present invention, if the etching device is disposed, the same effect can be achieved by using 12 1337398 regardless of whether an acidic or alkaline etching solution is used.
據此，本發明可提供一種不限於上述製作方法之封裝 基板如圖2F所示，包括一基板21、一圖案化之防焊層22 以及一金屬保護層24a。基板2丨具有一上表面2丨a、一下表 面21b、複數電鍍導通孔2丨1與—圖案化之線路層2丨2’圖案 化之、.東路層2 1 2係形成於基板u之上表面2丨a與下表面 2丨b，電鍍導通孔2U係貫穿於基板u之上表面2u與下表面 並Uf生‘通上表面2丨3與下表面之線路層Η)。圖 案化之防4層22係覆蓋於基板2】之上表面2丨a與下表面 21b，且位於基板2丨之上表面2U之防焊層形成有複數個 層開孔22卜並顯露出部分之線路層212，以作為打線 知墊2 15。打線焊墊2 1 5係與電鑛導通孔2 u電性連接。金屬 保護層24a#形餘打線料215之料表面，I該打線焊 墊2】5之末端係外露於該金屬保護層2 4 a。 15 在此’本貫施例中的基板的上表面係可利用打線辉塾 ，由-打線而可與W電性連接，而基板下表面係可利用 知球墊”’呈由其表面形成焊料球而可與印刷電路板電性連 接。因此，本發明係提供—打線式之封裝基板。 20 知上所述，本發明的封裝基板及其製作方法係解決了 習知技術中，僅經由使用―次阻層，並且使用鹼性溶液而 造成金屬保護層崩解以及成本浪費與製程複雜的缺點。本 發明制料次的阻層，並且直接在製㈣產線中使用敍 刻液，尤指酸性㈣液，而不用另外設置驗性_的裂置， 可以以現有的設備及空間人力，即可完成姓刻製程：不僅 13 即負成本，也簡化了原物料與製程的繁雜。 此外，本發明若排除前述另外設置鹼性蝕刻裝置之顧 :’亦可使用鹼性蝕㈣’而藉由第二阻層保護金屬保護 :進订鼓刻製程。本發明無論使用酸性或驗性姓刻液， Θ可達成相同效果。 上述實施例僅係為了方便說明而舉例而已’本發明所 主張之權利範圍自應以巾請專利範_述為準， 於上述實施例。 10 【圖式簡單說明】 圖1A至π係習知之打線式封裝基板製作流程到視圖。 圓2Α至2F係本發明一較佳實施例之封裝基板製作流程 剖試圖。 圖3Α至3F係本發明一較佳實施例之封裝基板製作流程 15 上視圖。 121，122,221，222防焊層開孔 【主要元件符號說明】11，21 基板 1 1 b，2 1 b下表面 1 1 2，2 1 2線路層 12,22 防焊層 131 阻層開孔 1 la，21a上表面 111,211電鍍導通孔 113,213電鍍導線 13 阻層 114,215打線焊墊 214 焊球墊 14a，14b，24a，24b金屬保護層 14 1337398 23 第 一阻層 ' 231 第一開孔 25 第 二阻層 251 第二開孔Accordingly, the present invention can provide a package substrate not limited to the above manufacturing method, as shown in FIG. 2F, comprising a substrate 21, a patterned solder resist layer 22, and a metal protective layer 24a. The substrate 2 has an upper surface 2丨a, a lower surface 21b, a plurality of plated vias 2丨1 and a patterned circuit layer 2丨2′ patterned. The east layer 2 1 2 is formed on the substrate u The surface 2丨a and the lower surface 2丨b, the plated via 2U penetrates through the upper surface 2u and the lower surface of the substrate u and Uf generates the upper layer 2丨3 and the wiring layer of the lower surface. The patterned anti-layer 4 layer 22 covers the upper surface 2丨a and the lower surface 21b of the substrate 2, and the solder resist layer on the upper surface 2U of the substrate 2 is formed with a plurality of layer openings 22 and reveals a portion The circuit layer 212 is used as a wire bonding pad 2 15 . The wire bonding pad 2 1 5 is electrically connected to the electric ore via 2 u. The metal protective layer 24a# is formed on the surface of the material 215, and the end of the wire bonding pad 2 is exposed to the metal protective layer 24a. 15 The upper surface of the substrate in the present embodiment can be electrically connected to W by wire bonding, and the lower surface of the substrate can be formed by soldering the surface of the substrate. The ball can be electrically connected to the printed circuit board. Therefore, the present invention provides a wire-wound package substrate. 20 As described above, the package substrate of the present invention and the method of fabricating the same solve the prior art, only by using The secondary resist layer, and the use of an alkaline solution causes the disintegration of the metal protective layer and the cost waste and the complicated process. The present invention has a secondary resist layer and directly uses the engraving liquid in the production line (IV), especially The acidic (four) liquid, without the additional setting of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The invention excludes the above-mentioned additional arrangement of the alkaline etching device: 'Alkaline etching (4)' can also be used to protect the metal by the second resist layer: the drilling process is advanced. The present invention uses an acidic or an experimental surrogate , Θ The above embodiments are merely exemplified for convenience of explanation. The scope of the claims of the present invention is based on the above-mentioned embodiments. 10 [Simple description of the drawings] FIG. 1A to The fabrication process of the packaged substrate of the π-type is known. The process of making a package substrate according to a preferred embodiment of the present invention is shown in FIG. 3A to 3F. 15 Upper view 121,122,221,222 solder mask opening [Main component symbol description] 11,21 substrate 1 1 b,2 1 b lower surface 1 1 2,2 1 2 wiring layer 12,22 solder resist layer 131 resistance Layer opening 1 la, 21a upper surface 111, 211 plating via 113, 213 plating wire 13 resist layer 114, 215 wire bonding pad 214 solder ball pad 14a, 14b, 24a, 24b metal protective layer 14 1337398 23 first resist layer '231 first opening 25 second resist layer 251 second opening
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