1379393 . 九、發明說明： - 【發明所屬之技術領域】 ， *發明係關於—種半導體裝置之製法，尤指-種細線 路間距之封裝基板之製法。 【先前技術】 為滿足半導體封裝件高積集度（Integrati〇n)及微型 化的封裝要求下，遂發展出整合多數主、被動元件及線路 之多層電路板，以於有限的空間下，藉由層間連接技術 籲（Interlayer connection)擴大電路板上可利用的佈線空 •間，以配合高密度線路之積體電路需求。 請參閱第1A至1H圖，係為習知封裝基板之製法。如 第1A圖所示’提供一例如為銅箱基板（c〇pper c_ laminated，CCL)之核心板，該核心板10具有兩相對 表面10a’於該表面10a上具有第一金屬層Ua;如第ΐβ 圖所示，於該核心板10及第一金屬層⑴中形成有通孔 (through—hole) 100，再於該通孔100之孔壁上及第一 •金屬層11a上形成有導電層12;如第1C圖所示，於該導 電層12上形成有第二金屬層m，並於該通孔中形 成導電通孔11c ;如第1D圖所示，接著於該通孔⑽中 形成有導電或不導電之塞孔材料13;如第1E圖所示，於 該第-金屬層Ua上及導電通孔llc上形成有阻層14, 並於該阻層U中形成有開口區140，以露出部份之第二 金屬層lib;如第1F圖所示，餘刻移除該開口區⑷中 之第二金屬層11b、導電層12及第一金屬層lia，以形成 110783 5 13.79393 ’第一線路層11;如第1G圖所示，移除該阻層】4，以露出 w該第一線路層11 ’且該第一線路層Π凸出於該表面l〇a; .如第1Η圖所示，接著，於該核心板i 〇及第一線路層i i 上形成增層結構15,該增層結構15係包括至少一介電層 151、形成於該介電層151上之第二線路層152、及形成 於該介電層151中之導電盲孔153,且該導電盲孔153電 性連接該第一及第二線路層u，152,又該增層結構15具 有電性接觸墊154,且於該增層結構15及電性接觸墊154 •上形成有防焊層16,該防焊層16中形成有複數開孔160, -以對應露出各該電性接觸墊154,而該電性接觸墊154係 -供後續電性連接焊錫材料（s〇lder material )，以電性連 接至半導體晶片。 然，習知封裝基板結構因佈設線路時，該第一線路層 11係以蝕刻製程形成，而凸設於核心板10之表面l〇a: 蝕刻法製成之線路不僅無法有效控制線路形狀，且其線寬 及線距較大’導致線路佈線密度降低，而無法達到細線路 間距之目的。 _因此，如何提出一種封裝基板之製法，以避免習知技 術之缺失’實以成為目前業界聽克服之課題。 【發明内容】 ,θ釔於上述習知技術之種種缺失，本發明之主要目的在 於提供-種細線路間距之封裝基板之製法。 本發明之又—目 之封裝基板之製法。 的在於提供一種提高線路佈線密度 110783 6 13.79393 丄？述及其它目的’本發明揭露一種封裝基板之製 括.提供一具有兩相對表面之核心介電層；提供 二個由P金屬層及第-線路層所組成之線路層結構，且 將該線路層結構之第—線路層麗合於該核心介電層相對 ::表=移除該第一金屬層，使該第-線路層嵌埋於 :核：=並與該核心介電層表面齊平;以及於該 層及兩相對之第—線路層中形成導 導電通孔電性連接該核心介電層兩表面之第-線路層。 則述之製法中，該線路層結構之製法係可包括:提供 屬相對之二表面’於該表面上具有輔助金 =金=層上具有離型膜，且該離型膜上具有 金'層;於該第-金屬層上形成阻層，並形成複數 開口區，以露出部份之第-金屬層;於該開口區中之第 金第—線路層；移除触層；以及移除該核 :板、輔助金屬層及離型膜’以分離形成二個由該第一金 屬層及該第-線路層所組成之線路層結構。 心介二導電::二製法係'可包括:於該核 介電層上'第 該導電層上形成第二金屬層，並於心 電；道㈣δ"第一金屬層及其所覆蓋之導 =錢遠導電通孔外露且齊平於該核心介電層之表 且該 前述之製法中，該核心介電層係可為樹脂材質， 110783 第線路層可具有複㈣， 係可包括打料或電性㈣墊。/、m連接塾 本需一線路層具有電性連接塾為基 第-線路可包括於該核心介電層及該 孔，以對庫露出該防辟層中形成有複數開 1您路出部份電性連接墊。 此外，依前述之製法，以該第一線 ㈣基本需求，亦可包括於該核心介電層‘；第二性連接 上形成有增層結構，係可具有至少-介；線路層 電層上之第二線路声、及人^層 '形成於該介 其中，該第_線二 電層中之導電盲孔， 路層之電性連接塾，該增声 j連接该弟-線 墊，且於該具有複數電性接觸 孔，以對，有防焊層，該防桿層具有複數開 丁您路出g亥電性接觸墊。 因此’本發明封裝基板及其製法，係於核 2之：型膜上形成第—線路層，而可有效控制線二兩 夢由雜線寬及線距，以提供高密度佈線之細線路，再 二I膜以分離核心板與線路層結構，而形成 …構，再分別將二線路層結構壓合於 ，路層 對表面上，接著移除該線路層結構之第一全屬==相 線路層嵌埋於核心介電層中，並使第一線路層屬之= =介電層表面齊平，俾以構成細線路間距 >、核 【實施方式】 以下稭由特定的具體實施例說明本發明之實施方 Π07ί 8 1379393 式’熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 請參閱第2A至2L圖’係提供—種封裝基板之製法之 剖面示意圖。 如第2A圖所示，首先，提供一核心板2〇，其相對二 表面具有辅助金屬層21a，於該輔助金屬層21a上具有離 型膜（release film) 21d，且於該離型膜2η上具有 一金屬層21b。 如第2B圖所示，於該第一金屬層21b上形成阻層 22,並形成複數開口區220,以露出部份之第一金屬^ 2以所述之第-金屬層21b^要作為後述電錢金屬所; 之電流傳導路徑，於本實施例中，該第一金屬層2ib係為 銅（Cu);該阻層22係為例如乾膜或液態光阻等光阻層 (Ph0t0resist)’其利用印刷、旋塗或貼合等方式形成^ 該第-金屬層21b上，再藉由曝光、顯影等方式加以圖案 化_使該阻層22形成開口區220。 如第2C圖所示，藉由該第一金屬層21b作為電流傳 導路徑’以於該開口區220中之第一金屬層21b上形成第 一線路層23,該第一線路層23係以電鍍方式製成，而產 生較細之線寬及線距以提供細線路，“有效控制線路形 狀以提高佈線密度；所述之第一線路層23之材料係翻 (Cu)、金（Au)及高鉛（High Lead)之高熔點金屬其中— 者；惟’依實際操作之經驗’由於銅為成熟之電鍍材料且 成本較低’因此’以電鍍銅較佳，但非以此為限。 110783 9 1379393 如第2D圖所示，接著，移除該阻層22 ,以形成由兮 奏金屬層21b及第一線路層23所組成之線路層結構2。 如第2E圖所示，再將該第一金屬層2lb自該離型膜 21d上分離，以使該第一金屬層21b及形成於該第一金屬 層21b上之第一線路層23脫離由該核心板2〇、輔助金屬 層21a及離型膜21d所組成之整體，以形成出由該第一金 屬層21 b及第一線路層23構成之二個線路層結構2。 如第2F圖所示，將該線路層結構2之第一線路層23 籲結合於核心介電層25相對兩表面25a上。 如第2G圖所示，接著，移除該第一金屬層2ib，以 露出該第一線路層23’使該第一線路層23嵌埋於該核心 介電層25中，並與該核心介電層25表面25a齊平，因該 第一線路層23為細線路，相較於習知技術之線路，於核 心介電層25中之第一線路層23為較小的線寬及線距。 如第2H圖所示，再於該核心介電層25及其表面25& 之第一線路層23形成有貫穿之通孔（thr〇ugh_h〇le)25〇。 • 如第21圖所示，於該核心介電層25上、第一線路層 23上及通孔250之孔壁上形成有導電層26。 如第2J圖所示，接著，於該導電層26上電鍍形成有 第二金屬層21c，並於該通孔25〇中之導電層26上形成 實心之導電通孔251。於本實施例中，該導電通孔251由 金屬銅直接填滿通孔250而形成，當然，於其他實施例 中，亦可先於通孔250中之導電層26上形成一層電鍍金 屬銅，再以塞孔材質填滿通孔25〇而形成；然，有關導電 10 110783 1379393 且其非本發 通孔251之製法種類繁多，惟乃業界所周知 明之技術特徵，故不再贅述。 如第2K圖所示，之後移除該核心介電層μ 25a上之第二金屬層21c及其所覆蓋之導電 ：：: 電通孔251外露且其外露表面與該核心介電；巧： 258齊平，且該第一線路声23且右；^#+ 、 以電性連接導電通：有複數電性連接塾231 23上如二:圖:：，再於該核心介電…^ 23上形成防绛層27，且該防焊層打具有複數 270,27卜以露出部份電性連㈣23卜其係包括可供食 打線封裝之金線（圖式中未表示）接著之打線墊（=、 231a，或供與半導體裝置或元件（圖式中未表示）電性連 接之電性接觸墊（Conductive pad) 231b。 於另-實施例中’亦可如第2L，圖所示，於該核心介 電層25及第-線路層23上形成增層結構⑼，係具有至 少-一允隻層28卜設於锌介電層281上之第二線路層282、 及設於該介電層281中之導電盲孔283;其中，該第二線 路層282係藉由導電盲孔283電性連接該第—線路層^ 之電性連接墊231，該增層結構28最外表之第二線路層 282具有複數電性接觸墊（c〇nductive 284，且於 增層結構28上覆蓋防焊層27，該防焊層27具有複數開 孔270，以對應露出該電性接觸墊284。 依上述製法可知，本發明係先於核心板2〇相對兩表 面之離型膜2Id上形成具有第一線路層23及第一金屬層 11 110783 1379393 21b之線路層結構2,接著藉由核心板2〇上的離型膜21d 以移除核心板20’而分離成二個線路層結構2，再將二線 ，層結構2分別壓合於—核心介電層以之兩相對的表面 上，且移除第-金屬層21b，以便於同時完成封裝基 板相對兩表面之線路製程；«後，於該線路層結構2上形 成防焊層27或增層結構28。 因此，本發明封裝基板之製法，係於核心板相對兩表 面形成二線路層結構’且該線路層結構中之第—線路層係 以電錢法形成’而有效控制線路形狀，並縮小線寬及線 距’以提供高密度佈線之細線路，再移除心板，且將二 線路層結構分別壓合於一核心介電層之兩相對表面上，以 使該第-線路層嵌埋於該核心介電層中，並使該第一線路 層之表面與該核心'介電層表面齊平，俾以構成細線路間距 之基板。 上述實施例係用以例示性說明本發明之原理及其功 鲁—效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 【圖式簡單說明】 第1A至1H圖係為習知封襞基板之製法示意圖；以及 第2A至2L圖係為本發明之封裝基板之製法之剖面示 意圖；其中第2L，圖係為第2L圖之另一實施例。 【主要元件符號說明】 110783 12 1379393 10, 20 核心板 10a,25a 表面 100,250 通孔 11, 23 第一線路層 11a, 21b 第一金屬層 lib,21c 第二金屬層 11c,251 導電通孔 12, 26 導電層 13 基孔材料 14, 22 阻層 140,220 開口區 15, 28 增層結構 151,281 介電層 152,282 第二線路層 153, 283 導電盲孔 154, 231b, 284 電性接觸墊 16, 27 防焊層 160, 270, 271 開孔 2 線路層結構 21a 輔助金屬層 21d 離型膜 231 電性連接墊 231a 打線墊 25 核心介電層 13 110783 ( Β1379393. IX. Description of the invention: - [Technical field to which the invention pertains], * The invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a package substrate having a fine line pitch. [Prior Art] In order to meet the high integration of semiconductor packages and miniaturized packaging requirements, a multi-layer circuit board integrating most of the main and passive components and lines has been developed to borrow in a limited space. The interlayer connection is used to expand the wiring space available on the board to meet the integrated circuit requirements of high-density lines. Please refer to Figures 1A to 1H for the fabrication of a conventional package substrate. As shown in FIG. 1A, a core plate, such as a copper box substrate (CCL), having two opposite surfaces 10a' having a first metal layer Ua on the surface 10a; A through hole is formed in the core plate 10 and the first metal layer (1), and a conductive layer is formed on the hole wall of the through hole 100 and the first metal layer 11a. a layer 12; as shown in FIG. 1C, a second metal layer m is formed on the conductive layer 12, and a conductive via 11c is formed in the via hole; as shown in FIG. 1D, in the via hole (10) Forming a conductive or non-conductive plug material 13; as shown in FIG. 1E, a resist layer 14 is formed on the first metal layer Ua and the conductive via 11c, and an open region is formed in the resist layer U. 140, to expose a portion of the second metal layer lib; as shown in FIG. 1F, the second metal layer 11b, the conductive layer 12 and the first metal layer lia in the open region (4) are removed to form 110783 5 13.79393 'The first circuit layer 11; as shown in FIG. 1G, the resist layer is removed 4' to expose the first circuit layer 11' and the first circuit layer is protruded a surface layer ;a; as shown in FIG. 1 , next, a build-up structure 15 is formed on the core board i 〇 and the first circuit layer ii, the build-up structure 15 includes at least one dielectric layer 151 formed on a second circuit layer 152 on the dielectric layer 151, and a conductive via 153 formed in the dielectric layer 151, and the conductive via 153 is electrically connected to the first and second circuit layers u, 152, and The build-up structure 15 has an electrical contact pad 154, and a solder resist layer 16 is formed on the build-up structure 15 and the electrical contact pad 154. The solder resist layer 16 is formed with a plurality of openings 160, to correspond to Each of the electrical contact pads 154 is exposed, and the electrical contact pads 154 are for subsequent electrical connection of a solder material to electrically connect to the semiconductor wafer. However, when the conventional package substrate structure is routed, the first circuit layer 11 is formed by an etching process, and is protruded from the surface of the core plate 10; a: the circuit made by the etching method can not effectively control the shape of the line. Moreover, the line width and the line spacing are large, which results in a decrease in the wiring density of the line, and the purpose of the fine line spacing cannot be achieved. _ Therefore, how to propose a method of packaging a substrate to avoid the lack of the prior art has become a subject that the industry has overcome. SUMMARY OF THE INVENTION The present invention is directed to providing a method for fabricating a package substrate having a fine line pitch. A further method of making the package substrate of the present invention. It is to provide an increase in line wiring density 110783 6 13.79393 丄? For other purposes, the present invention discloses a package substrate. A core dielectric layer having two opposite surfaces is provided; two circuit layer structures composed of a P metal layer and a first circuit layer are provided, and the circuit is provided. The first layer of the layer structure is fused to the core dielectric layer:: Table = the first metal layer is removed, the first circuit layer is embedded in: core: = and is flush with the surface of the core dielectric layer And forming a first-line layer electrically connected to both surfaces of the core dielectric layer in the layer and the two opposite first-line layers. In the method of describing the method, the method for manufacturing the circuit layer structure may include: providing a genus opposite surface having an auxiliary gold on the surface = gold = having a release film on the layer, and having a gold layer on the release film Forming a resist layer on the first metal layer, and forming a plurality of open regions to expose a portion of the first metal layer; a gold first layer in the open region; removing the contact layer; and removing the The core: the plate, the auxiliary metal layer and the release film are separated to form two circuit layer structures composed of the first metal layer and the first circuit layer. The second dielectric system: the two-system system can include: forming a second metal layer on the first conductive layer on the nuclear dielectric layer, and forming the second metal layer on the electrocardiogram; the circuit (4) δ" the first metal layer and the covered layer thereof = Qianyuan conductive via is exposed and flush with the surface of the core dielectric layer. In the foregoing method, the core dielectric layer may be made of a resin material, and the 110783 first circuit layer may have a complex (four), which may include a material Or electrical (four) pad. /, m connection 需 requires a circuit layer to have an electrical connection 第 based - the line can be included in the core dielectric layer and the hole, to form a plurality of open layers Part of the electrical connection pad. In addition, according to the foregoing method, the basic requirements of the first line (four) may also be included in the core dielectric layer '; the second connection may be formed with a build-up structure, which may have at least a dielectric layer; The second line sound, and the person's layer 'is formed in the medium, the conductive blind hole in the second electric layer of the first line, the electrical connection of the road layer is 塾, the sound enhancement j is connected to the brother-line pad, and The plurality of electrical contact holes have a plurality of electrical contact holes, and the solder resist layer has a plurality of openings to open the electrical contact pads. Therefore, the package substrate of the present invention and the method for manufacturing the same are formed on the core 2: forming a first circuit layer on the film, and can effectively control the line width and line spacing of the line two dreams to provide a fine line of high-density wiring. The second I film separates the core plate and the circuit layer structure to form a structure, and then presses the two circuit layer structures respectively, the road layer is on the surface, and then removes the first full genus of the circuit layer structure == phase The circuit layer is embedded in the core dielectric layer, and the first circuit layer belongs to == the surface of the dielectric layer is flush, and the surface of the dielectric layer is formed to form a fine line pitch>, and the core is implemented by a specific embodiment. Illustrative Embodiments of the Invention ί07ί 8 1379393 The person skilled in the art can readily appreciate other advantages and utilities of the present invention from the disclosure of the present specification. Please refer to FIGS. 2A to 2L for a schematic cross-sectional view showing a method of manufacturing a package substrate. As shown in FIG. 2A, first, a core plate 2 is provided, which has an auxiliary metal layer 21a on the opposite surfaces, a release film 21d on the auxiliary metal layer 21a, and a release film 21d on the auxiliary metal layer 21a. There is a metal layer 21b thereon. As shown in FIG. 2B, a resist layer 22 is formed on the first metal layer 21b, and a plurality of open regions 220 are formed to expose a portion of the first metal 2, and the first metal layer 21b is to be described later. In the present embodiment, the first metal layer 2ib is copper (Cu); the resist layer 22 is a photoresist layer such as a dry film or a liquid photoresist (Ph0t0resist) The first metal layer 21b is formed by printing, spin coating or lamination, and patterned by exposure, development, etc., so that the resist layer 22 forms the open region 220. As shown in FIG. 2C, the first metal layer 21b is used as a current conduction path to form a first wiring layer 23 on the first metal layer 21b in the opening region 220. The first wiring layer 23 is plated. The method is made to produce a thinner line width and line spacing to provide a fine line, "effectively controlling the shape of the line to increase the wiring density; the material of the first circuit layer 23 is turned over (Cu), gold (Au) and High-lead high-melting-point metal among them—but 'experience in practical experience' because copper is a mature electroplating material and the cost is lower, so it is better to use electroplated copper, but not limited to this. 9 1379393, as shown in FIG. 2D, next, the resist layer 22 is removed to form a wiring layer structure 2 composed of the ensemble metal layer 21b and the first wiring layer 23. As shown in FIG. 2E, The first metal layer 2lb is separated from the release film 21d such that the first metal layer 21b and the first circuit layer 23 formed on the first metal layer 21b are separated from the core plate 2 and the auxiliary metal layer 21a. And the integral part of the release film 21d to form the first metal layer 21 b and the first line The two circuit layer structures 2 are formed. As shown in Fig. 2F, the first circuit layer 23 of the circuit layer structure 2 is bonded to the opposite surfaces 25a of the core dielectric layer 25. As shown in Fig. 2G, Then, the first metal layer 2ib is removed to expose the first circuit layer 23' to embed the first circuit layer 23 in the core dielectric layer 25, and is flush with the surface 25a of the core dielectric layer 25. Since the first circuit layer 23 is a thin line, the first circuit layer 23 in the core dielectric layer 25 has a smaller line width and line spacing than the conventional circuit. As shown in FIG. 2H And a through via hole 25〇 is formed in the core dielectric layer 25 and the surface layer 23 of the surface 25& and the core dielectric layer is as shown in FIG. A conductive layer 26 is formed on the upper circuit layer 23 and the hole wall of the through hole 250. As shown in FIG. 2J, a second metal layer 21c is formed on the conductive layer 26, and A solid conductive via 251 is formed on the conductive layer 26 in the via 25 。. In the embodiment, the conductive via 251 is formed by directly filling the via 250 with metal copper. In other embodiments, a layer of plated metal copper may be formed on the conductive layer 26 in the through hole 250, and the through hole 25 is filled with a plug hole material; however, the conductive 10 110783 1379393 and The method for manufacturing the through-hole 251 is not limited, but is not described in detail in the industry. As shown in FIG. 2K, the second metal layer 21c on the core dielectric layer μ 25a is removed. And the conductive layer covered by the::: the electrical via 251 is exposed and its exposed surface is dielectric with the core; QC: 258 is flush, and the first line sounds 23 and right; ^#+, electrically connects the conductive: There is a plurality of electrical connections 塾231 23 as shown in FIG. 2: and then a tamper-evident layer 27 is formed on the core dielectric ... 23, and the solder resist layer has a plurality of 270, 27 to expose partial electrical properties. The connection (4) 23 includes the gold wire (not shown in the figure) for the package of the wire and the wire pad (=, 231a, or the electrical connection for electrical connection with the semiconductor device or component (not shown). Conductive pad 231b. In another embodiment, as shown in FIG. 2L, a build-up structure (9) is formed on the core dielectric layer 25 and the first circuit layer 23, and has at least one layer 28 disposed on the zinc layer. a second circuit layer 282 on the dielectric layer 281 and a conductive via 283 disposed in the dielectric layer 281; wherein the second circuit layer 282 is electrically connected to the first circuit layer via the conductive via 283 The electrical connection pad 231, the second circuit layer 282 of the outermost layer of the build-up structure 28 has a plurality of electrical contact pads (c〇nductive 284, and the build-up structure 28 is covered with a solder resist layer 27, the solder resist layer 27 has a plurality of openings 270 to correspondingly expose the electrical contact pads 284. According to the above method, the present invention is formed on the release film 2Id opposite to the opposite surfaces of the core plate 2, having the first circuit layer 23 and the first The wiring layer structure 2 of the metal layer 11 110783 1379393 21b is then separated into two circuit layer structures 2 by removing the core board 20' by the release film 21d on the core board 2, and then the second line, the layer structure 2 Pressing on the opposite surfaces of the core dielectric layer respectively, and removing the first metal layer 21b, so as to complete at the same time a soldering process 27 or a build-up structure 28 is formed on the circuit layer structure 2. Therefore, the method of manufacturing the package substrate is to form two circuit layers on opposite sides of the core board. The structure 'and the first line layer in the circuit layer structure is formed by the electric money method' to effectively control the shape of the line, and the line width and the line spacing are reduced to provide a fine line of high-density wiring, and then the core board is removed, and The two circuit layer structures are respectively pressed onto the opposite surfaces of a core dielectric layer such that the first circuit layer is embedded in the core dielectric layer, and the surface of the first circuit layer and the core are The surface of the dielectric layer is flush with the surface of the substrate to form a fine line spacing. The above embodiments are used to exemplify the principles of the present invention and its advantages, and are not intended to limit the present invention. The above embodiments may be modified without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as described in the scope of the patent application described below. [Simple description of the drawings] Figures 1A to 1H FIG. 2A to 2L are schematic cross-sectional views showing a method of manufacturing a package substrate of the present invention; wherein the second embodiment is a second embodiment of the second embodiment. Description] 110783 12 1379393 10, 20 core board 10a, 25a surface 100, 250 through hole 11, 23 first circuit layer 11a, 21b first metal layer lib, 21c second metal layer 11c, 251 conductive via 12, 26 conductive layer 13 Base material 14, 22 resist layer 140, 220 open area 15, 28 build-up structure 151, 281 dielectric layer 152, 282 second circuit layer 153, 283 conductive blind hole 154, 231b, 284 electrical contact pad 16, 27 solder resist layer 160, 270 , 271 opening 2 circuit layer structure 21a auxiliary metal layer 21d release film 231 electrical connection pad 231a wire pad 25 core dielectric layer 13 110783 ( Β