200950039 凡、货η月說明： 【發明所屬之技術領域】 本發明係關於一種半導體裝置之製法，尤指一種細線 路間距之封裝基板之製法。 ' 【先前技術】 - ^滿足半導體封裝件高積集度⑽咖）及微型 化的封裝要求下，遂發展出整合多數主、被動元件及線路 之多層電路板，以於有限的空間下，藉由層間連接技術 ❹（IrUerlayer connectlon)擴大電路板上可利用的佈線空 間’以配合南密度線路之積體電路需求。 請參㈣U至，係為習知封裝基板之製法。如 第1A圖所示，提供一例如為銅箱基板（Copper coated laminated, CCL)之核心；1 n> , 主& ιλ 板10，邊核心板l〇具有兩相對 表面心’於該表面10a上具有第一金屬層山：如第π 圖所示，於該核心板10及第—金屬们&中形成有通孔 (through_hole) 100 ’再於該通孔1〇0之孔壁上及第一 ©金屬層Ua上形成有導電層12;如第ic圖所示，於該導 電層12上形成有第二金屬声n 屬層llb，並於該通孔100中形 成導電通孔11c ;如第]D HI仏-, _ ^ 弟丨D圖所不，接著於該通孔1〇〇中 形成有導電或不導電之塞孔材 二云错人叶ld，如第1E圖所示’於 该第一金屬層11a上及導雷視 导包通孔11c上形成有阻層14， 並於該阻層14中形成有開口 ,M . llu ，開口 Q 140 ’以露出部份之第二 金屬層lib;如第1F圖所； 咕 囫所不，蝕刻移除該開口區140中 之第二金屬層lib、導電声^ ^ τ 电層12及第一金屬層11a，以形成 110783 5 200950039 矛一綠格層11 ;如箆- 該第-線路層11，且，第二不’移除該阻層14，以露出 如第圖所示，接著:、，表路層11凸出於該表面 - 接者，於該核心板10及第一線路層u :成料結構15，該增層結構15係包括 -151、形成於該介電層⑸上之第二線路層152、^= 於該介電層151中之導電盲孔153， 【 性連接該第一及篦··始Α π %苜孔I W私 右恭卜 ”層11，152，又該增層結構15且 觸塾154’且於該增層結構15及電性 5、 焊層16,該防谭層16中形成有複數開孔⑽， 對應路出各該電性接觸塾154，而該電性 供後續電性連接烊錫材柢Γ 54係 接至半導體晶片 科（soldermaterial)，以電性連 然”裝基板結構因佈設線路時，該第—線路声 ㈣成，而凸設於核心板H)之表面1〇/ 蝕刻法製成之線路不僅無法有效控制線路形狀，且 ❹=:導致線路佈線密度降低，而無法達到:線: 術之：Γ上何提出—種封裝基板之製法，以避免習知技 η 、 貫以成為目前業界亟待克服之課題。 【發明内容】 鑑於上述習知技術之種種缺失，本發明之主要 於提供一種細線路間距之封裝基板之製法。 本％月之又-目的在於提供—種提高線路 之封裝基板之製法。 天在度 110783 6 200950039 兩達上述及其它目的，本 法，係包括··提供一罝右兩揭路—禮封裳基板之製 1 、 八有兩相對表面之妨、、人$ „ —二個由第-金屬層及第一線路声二Ή層，·提供 將該線路層結構之第—線路人、▲路層結構，且 之兩表面上；移除該第― :於―心介電層相對 核心介命μ層表面齊平，·以及於該 核Μ书層及兩相對之第一線路層中 ❹ 導電！孔電性連接該核心介電層兩表面之第：:路層， 則述之製法中’該線路層結構曰 -核心板，係具有相對 =广供 ^ 辅助金屬層上具有離型臈，且該 4苐-金屬層；於該第一金屬 開口區，以露出部份之第且層亚形成稷數 ^ m Ά 矛1屬層，於该開口區中之第一 金屬層上形成該第一線路層； 心板、^ 移除該阻層，以及移除該核 屬h 及離型膜，以分離形成二個由該第一金 θ *亥第一線路層所組成之線路層結構。 * 心介6亥導電通孔之製法係可包括:於該核 人二：層及兩相對之第一線路層中形成通孔；於該核心200950039 Description of the invention: [Technical Field] The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a package substrate having a fine line pitch. [Previous technology] - To meet the high integration of semiconductor packages (10) coffee and miniaturized packaging requirements, 遂 developed a multi-layer circuit board that integrates most of the main and passive components and lines to borrow in a limited space. The wiring space available on the board is expanded by the IrUerlayer connectlon to match the integrated circuit requirements of the south density line. Please refer to (4) U to, which is the method of manufacturing the package substrate. As shown in FIG. 1A, a core such as a copper-coated substrate (CCL) is provided; 1 n>, a main & ι λ plate 10 having two opposing surface cores ' on the surface 10a a first metal layer mountain: as shown in FIG. π, a through hole (100) is formed in the core plate 10 and the metal and the hole, and then on the hole wall of the through hole a conductive layer 12 is formed on the first metal layer Ua; as shown in the ic diagram, a second metal acoustic n-layer 11b is formed on the conductive layer 12, and a conductive via 11c is formed in the via 100; For example, the first D HI 仏 -, _ ^ 丨 丨 D 图 图 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , A resist layer 14 is formed on the first metal layer 11a and the lightning guide package through hole 11c, and an opening is formed in the resist layer 14, M. llu, and the opening Q 140' is exposed to the second portion. The metal layer lib; as shown in FIG. 1F; etch, remove the second metal layer lib, the conductive acoustic layer 12, and the first metal layer 11a in the open region 140 to form 1 10783 5 200950039 Spear-green layer 11; such as 箆- the first-line layer 11, and the second does not 'remove the resist layer 14 to expose as shown in the figure, then:,, the surface layer 11 convex For the surface-connector, the core board 10 and the first circuit layer u: a material structure 15, the build-up structure 15 includes -151, a second circuit layer 152 formed on the dielectric layer (5), ^= The conductive blind hole 153 in the dielectric layer 151, [sexually connected to the first and first Α π π π I I I I ” ” ” ” ” ” ” ” ” ” ” ” ” 11 11 11 11 11 11 11 11 In the layered structure 15 and the electrical layer 5, the solder layer 16, the anti-tank layer 16 is formed with a plurality of openings (10) corresponding to the electrical contacts 154, and the electrical is provided for subsequent electricity. The connection between the tin and the tin material 柢Γ 54 is connected to the semiconductor wafer family (the solder material), and the substrate structure is electrically connected. The first line sounds (4) and protrudes on the surface of the core board H). The circuit made by 1〇/etching method can not only effectively control the shape of the line, and ❹=: The line wiring density is reduced, but it cannot be achieved: Line: Technique: What is the name? Method of loading a substrate, [eta] in order to avoid conventional technology, so as to be consistent need to overcome the problems the industry. SUMMARY OF THE INVENTION In view of the above various deficiencies of the prior art, the present invention is directed to a method of fabricating a package substrate having a fine line pitch. This month and again - the purpose is to provide a method for improving the package substrate of the line. Days in the 110783 6 200950039 Two of the above and other purposes, this law, including · provide a right two roads - the system of the ceremonial slabs 1, eight with two opposite surfaces, people $ „ - two The first-metal layer and the first-line acoustic two-layer layer, the first line person and the ▲ road layer structure of the circuit layer structure are provided on both surfaces; the first part is removed: The layer is flush with the surface of the core layer, and is electrically conductive in the core layer and the two opposite first circuit layers. The hole is electrically connected to the surface of the core dielectric layer:: the road layer, In the method of preparation, the circuit layer structure 核心-core plate has a relative = wide supply ^ the auxiliary metal layer has a release 臈, and the 4 苐-metal layer; in the first metal opening region, to expose the portion And forming a first layer of the first metal layer in the open region; the core plate, removing the resist layer, and removing the core And a release film for separating and forming two circuit layer structures composed of the first gold θ * hai first circuit layer. The method for manufacturing a 6-well conductive via may include: forming a via hole in the core two: layer and two opposite first circuit layers;
St第一線路層上及通孔之孔壁上形成導電層；於 心二金屬層，並於該通孔中之導電層上形 =導電通孔；以及移除該第二金屬層及其所覆蓋之； 二曰，並使該導電通孔外露且齊平於該核心介電層之表 珂 述之製法中’該核心介電層係可為樹脂材質，且該 110783 7 200950039 木-，咏吩層可具有複數電性連接墊，其 係可包括打線墊或電性接觸墊。 〃 4性連接墊 依上述製法’若以該第一绩败层 •本需求’該封裝基板之製法復可 ==接塾為基 _第-線路層上形成防焊層，且該防焊層c及該 孔，以對應露出部份電性連接墊。 少成有複數開 此外，依前述之製法，以該第一線路声且 墊為基本需求，亦可包括於該核心介電層^該：f連接 ❹電層上H鮮I有至介電層、形成於該介 =，該，路層係可藉由導電盲孔電性J該= Θ之$性連接墊，該增層結構表面並具有複數電 墊’且於該增層結構上設有觸 孔，以對應露出該電性接觸塾。防卜層具有複數開 本發明封裝基板及其製法，係於核 表面之離型膜上形成第—線路層，而以目對兩 ©狀’並缩小绐办η ώ 有效&制線路形 葬“線距，以提供高密度佈線之細線路，再 ^ 型膜以分離核心板與線路層結構，而形成- f再刀別將二線路層結構歷合於一核心介電層之兩相 線路層山：接著移除該線路層結構之第一金屬層，使第- 心介電：表里：Γ介電層中’並使第一線路層之表面與核 I电層表面齊平，俾以構成細線路間距之基板。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 Π0783 8 200950039 ν此技藝之人士可由本說明書所揭示之内容輕易地 暸解本發明之其他優點及功效。 請參閱f 2Ai 2L®，係提供—種封襄基板之之 剖面示意圖。 之 /如第2A圖所示，首先，提供—核心板別，其相對二 表面具有輔助金屬層21a，於該輔助金屬層21a上且有離 型膜（release film) 21d，且於該離型膜2ld上具 一金屬層21 b。 如第2B圖所示，於該第—金屬層批上形成阻声 22,並形成複數開口區220,以露出部份之第一金屬^ 2以所述之第-金屬層21b主要作為後述電鍍金屬所; 之電流傳導路徑，於本實施例中，該第一金屬層2ib係為 銅（Cu);該阻層22係為例如乾膜或液態光阻等光阻層 (Photoresist)，其利用印刷、旋塗或貼合等方式形成^ 該第-金屬層21b上，再藉由曝光、顯影等方式加二圖案 化，使該阻層22形成開口區220。 ' © 如第2C圖所示’藉由該第—金屬層m作為電流傳 導路徑，以於該開口區220中之第一金屬層21b上形成第 一線路層2 3，該第一線路層2 3係以電鍍方式势成， 生較細之線寬及線距以提供細線路，進而有效控制線路形 狀以提高佈線密度；所述之第一線路層23之材料係為鋼 (Cu)、金（Au)及高鉛（High Lead)之高熔點金屬其中— 者；惟，依實際操作之經驗，由於銅為成熟之電鍍材料且 成本較低，因此’以電鍍銅較佳，但非以此為限。 110783 9 200950039 划乐2D圖所不’接著，移除該阻層22，以形成由該 第一金屬層21b及第一線路層23所組成之線路層結構2。 » 如第2E圖所示’再將該第一金屬層21b自該離型膜 21d上分離，以使該第一金屬層2ib及形成於該第一金屬 層21b上之第一線路層23脫離由該核心板20、輔助金屬 _層21a及離型膜21d所組成之整體，以形成出由該第一金 屬層21b及第一線路層23構成之二個線路層結構2。 如第2F圖所示，將該線路層結構2之第一線路層23 ❹結合於核心介電層25相對兩表面25a上。 如第2G圖所示，接著，移除該第一金屬層21b，以 露出該第一線路層23,使該第一線路層23嵌埋於該核心 介電層25中，並與該核心介電層25表面25a齊平，因該 第一線路層23為細線路，相較於習知技術之線路，於核 之第一線路層2 3為較小的線寬及線距。Forming a conductive layer on the first circuit layer of the St and the hole wall of the through hole; forming a metal layer on the core and forming a conductive via hole on the conductive layer in the through hole; and removing the second metal layer and the Covering the second layer and exposing the conductive via hole to the surface of the core dielectric layer, the core dielectric layer may be a resin material, and the 110783 7 200950039 wood-, 咏The lining layer can have a plurality of electrical connection pads, which can include wire pads or electrical contact pads. 〃 4-type connection pad according to the above-mentioned method 'If the first performance layer/this requirement' is adopted, the package substrate can be replaced by a method of forming a solder mask, and the solder resist layer is formed on the first-circuit layer. And the hole to correspondingly expose a portion of the electrical connection pad. In addition, according to the above-mentioned method, the first line sound and the pad are basic requirements, and may also be included in the core dielectric layer: the f-connected electric layer is H-I-to-dielectric layer Formed in the dielectric layer, wherein the road layer can be electrically conductive via a conductive connection, the surface of the build-up structure has a plurality of pads and is provided on the build-up structure Touch the hole to correspondingly expose the electrical contact 塾. The anti-pick layer has a plurality of encapsulating substrates of the present invention and a method for preparing the same, and the first circuit layer is formed on the release film of the nuclear surface, and the two are in the shape of 'the same shape' and reduce the number of η ώ effective & "Line spacing, to provide a fine line of high-density wiring, and then to form a film to separate the core board and the circuit layer structure, and form a two-phase circuit that combines the two circuit layer structure with a core dielectric layer. Layer mountain: then remove the first metal layer of the circuit layer structure, so that the first core dielectric: in the surface: the dielectric layer in the ' and the surface of the first circuit layer and the surface of the nuclear I electrical layer, 俾The following is a description of the embodiments of the present invention by way of specific embodiments. 078. See f 2Ai 2L® for a cross-sectional view of a sealed substrate. As shown in Figure 2A, first, a core plate is provided, the opposite surfaces having an auxiliary metal layer 21a. Auxiliary metal layer 21a and There is a release film 21d, and a metal layer 21b is formed on the release film 2ld. As shown in FIG. 2B, a sound blocking 22 is formed on the first metal layer batch, and a plurality of open regions are formed. 220, in order to expose a portion of the first metal 2, wherein the first metal layer 21b is mainly used as a current conduction path of a plating metal to be described later; in the embodiment, the first metal layer 2ib is copper (Cu) The resist layer 22 is, for example, a photoresist layer such as a dry film or a liquid photoresist, which is formed on the first metal layer 21b by printing, spin coating or lamination, and then exposed and developed. The two layers are patterned to form the resistive layer 22 to form the open region 220. ' © as shown in FIG. 2C', the first metal in the open region 220 is formed by the first metal layer m as a current conducting path. Forming a first circuit layer 23 on the layer 21b, the first circuit layer 23 is formed by electroplating, and a thin line width and a line spacing are formed to provide a fine line, thereby effectively controlling the line shape to increase the wiring density; The material of the first circuit layer 23 is a high melting point metal of steel (Cu), gold (Au) and high lead (High Lead). However, according to the experience of actual operation, since copper is a mature electroplating material and the cost is low, it is better to use electroplated copper, but not limited to this. 110783 9 200950039 The resist layer 22 is removed to form a wiring layer structure 2 composed of the first metal layer 21b and the first wiring layer 23. » As shown in FIG. 2E, the first metal layer 21b is further separated therefrom. The film 21d is separated such that the first metal layer 2ib and the first wiring layer 23 formed on the first metal layer 21b are separated from the core plate 20, the auxiliary metal layer 21a, and the release film 21d. Overall, two wiring layer structures 2 composed of the first metal layer 21b and the first wiring layer 23 are formed. As shown in Fig. 2F, the first wiring layer 23 of the wiring layer structure 2 is bonded to the opposite surfaces 25a of the core dielectric layer 25. As shown in FIG. 2G, the first metal layer 21b is removed to expose the first circuit layer 23, and the first circuit layer 23 is embedded in the core dielectric layer 25, and is integrated with the core layer. The surface 25a of the electrical layer 25 is flush, since the first circuit layer 23 is a thin line, and the first circuit layer 23 of the core has a smaller line width and line spacing than the conventional circuit.
中’亦可先於通孔250中之導電層 屬銅’再以塞孔材質填滿通孔25〇 心介電層25中之第一 如第2H圖所示， 之第一線路層23形成 干’該導電通孔251由 ’當然’於其他實施例 26上形成一層電鍍金 而形成；然，有關導電 110783 10 200950039 遇札〇i之製法種類繁多，惟乃業界所 .明之技術特徵，故不再贅述。 D知，且其非本發 ϋ心所示，之後移除該核 ❿上之第二金屬層2ic及其所覆c上下表面 電通孔251外露n ± 導包層26’使該導 仏背平，且該第—線路層 电層!之表面 以電性連接導電通孔251。 有I數电性連接塾231 u上如示，再於該核心介電層25及第—線路層 〇27〇tm出層，27,且該防焊層27具有複數開孔 路出。(M分電性連接墊231，复係包括^ =封裝之金線(圖式中未表示)接著之打線整二 =:與半導體裝置或元件(圖式中未表示二) 電性接觸墊（Conductive pad) 231b。 電層4可如第2L’圖所示，於該核心介 層25及第-線路層23上形成增層結構28，係具有至 >、一介電層281、設於·^介雷爲9δ1 L ^ 丨電層281上之第二線路層282、 ©及_介電層281中之導電盲孔283;其中該第二線 路層282係藉由導電盲孔283電性連接該第-線路層23 之電性連接墊231，該増層結構28最外表之第二線路層 2犯具有複數電性接觸墊（c〇nductive pad) 284，且於 、層結構28上覆蓋防焊層27，該防焊層27具有複數開 孔270,以對應露出該電性接觸墊284。 依上述製法可知’本發明係先於核心板2〇相對兩表 面之離型膜21d上形成具有第一線路層23及第一金屬層 11 110783 200950039 △上U <綠路層結構2，粮荃茲 以移除核心板20，而八:：板2°上的離型膜別 • „ a U而刀離成二個線路層結構2,再將-娩 ，路層結構2分別麗合於一構2再將-線 25a上，且移㈣層25之兩相對的表面 板相㈣^ b ’以便於同時完成封裝基 ' ，又囬之線路製程；最後，於該線路層結構2上形 ,成防焊層27或增層結構28。 。構2上^ 面形Γ此綠本發明封裝基板之製法’係於核心板相對兩表 = -，、泉路層結構，且該線路層結構中之第 < Μ隸龍路形狀，並料線寬及線 以提供问岔度佈線之細線路，再移除核心板，且將二 層結構分別壓合於—核心介電層之兩相對表面上，以 芦第線路層嵌埋於該核心介電層中，並使該第一線路 曰之表面與該核心介電層表面齊平’俾以構成細線距 之基板。 ^ 上述實施例係用以例示性說明本發明之原理及其功 政，而非用於限制本發明。任何熟習此項技藝之人士均可 ©在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 【圖式簡單說明】 第1Α至1Η圖係為習知封裝基板之製法示意圖；以及 第2 Α至2L圖係為本發明之封裝基板之製法之剖面示 意圖；其中第2L，圖係為第2L圖之另一實施例。 【主要元件符號說明】 12 110783 200950039 i υ, ζυ 核心板 1 Oa,25a 表面 100,250 通孔 11, 23 第一線路層 11a, 21b 第一金屬層 lib,21c 第二金屬層 11c,251 導電通孔 12, 26 導電層 13 基孔材料 14, 22 阻層 140,220 開口區 15, 28 增層結構 151,281 介電層 152,282 第二線路層 153,283 導電盲孔 154,231b,284 電性接觸墊 16, 27 防焊層 160,270,271 開孔 2 線路層結構 21a 輔助金屬層 21d 離型膜 231 電性連接墊 231a 打線墊 25 核心介電層 13 110783The middle layer 'before the conductive layer in the via hole 250 is copper' and fills the via hole 25 with the plug hole material. The first dielectric layer 25 is formed as shown in FIG. 2H, and the first circuit layer 23 is formed. The conductive via 251 is formed by forming a layer of electroplated gold on the other embodiment 26; however, the conductive 110783 10 200950039 has a wide variety of methods, but it is a technical feature of the industry. No longer. D knows, and it is not shown in the present invention, after removing the second metal layer 2ic on the core and its covered upper and lower surface electrical vias 251 exposed n ± guide layer 26' to make the guide back And the surface of the first circuit layer is electrically connected to the conductive via 251. There is an I-number electrical connection 塾 231 u as shown, and then the core dielectric layer 25 and the first circuit layer 〇 27 〇 tm, 27, and the solder resist layer 27 has a plurality of open-holes. (M-component connection pad 231, the system includes ^ = packaged gold wire (not shown in the figure) and then the wire is doubled =: with a semiconductor device or component (not shown in the figure) electrical contact pad ( Conductive pad) 231b. The electric layer 4 can form a build-up structure 28 on the core via 25 and the first-line layer 23 as shown in FIG. 2L', having a layer of > to a dielectric layer 281. ^介雷 is the second line layer 282 on the 9δ1 L ^ germanium layer 281, and the conductive via 283 in the dielectric layer 281; wherein the second circuit layer 282 is electrically conductive via the conductive via 283 An electrical connection pad 231 is connected to the first circuit layer 23, and the second circuit layer 2 of the outermost layer of the germanium structure 28 is provided with a plurality of electrical contact pads 284, and is covered on the layer structure 28. The solder resist layer 27 has a plurality of openings 270 for correspondingly exposing the electrical contact pads 284. According to the above manufacturing method, the present invention is formed on the release film 21d of the opposite sides of the core plate 2 Having the first circuit layer 23 and the first metal layer 11 110783 200950039 △ upper U < green road layer structure 2, grain 荃 to remove the core board 20, and eight:: Release film on 2° • „ a U and the knife is separated into two circuit layer structures 2, and then the delivery, the road structure 2 is respectively combined with a structure 2 and then - line 25a, and moved (four) layer 25 of the opposite surface plate phase (four) ^ b 'to facilitate the completion of the package base ', and back to the line process; finally, the line layer structure 2 is formed into a solder resist layer 27 or a build-up structure 28 . 2上^面形ΓThis green method of manufacturing the package substrate of the present invention is based on the core plate relative to the two tables = -, the spring road layer structure, and the line layer structure of the first < Μ Lilong road shape, and the material line The width and the line are provided to provide a thin line of the wiring, and then the core board is removed, and the two-layer structure is respectively pressed onto the opposite surfaces of the core dielectric layer, and the Ludi circuit layer is embedded in the core layer. In the electrical layer, the surface of the first wiring layer is flush with the surface of the core dielectric layer to form a substrate with a fine line pitch. The above embodiments are used to exemplarily illustrate the principles and principles of the present invention. Rather than limiting the invention, any person skilled in the art can, without departing from the spirit and scope of the invention. The above embodiments are modified. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described later. [Simplified description of the drawings] Figures 1 to 1 are schematic diagrams of a conventional package substrate; and 2L is a schematic cross-sectional view showing the manufacturing method of the package substrate of the present invention; wherein 2L is another embodiment of the 2nd L. [Major component symbol description] 12 110783 200950039 i υ, 核心 Core board 1 Oa, 25a Surface 100, 250 through hole 11, 23 first circuit layer 11a, 21b first metal layer lib, 21c second metal layer 11c, 251 conductive via 12, 26 conductive layer 13 base material 14, 22 resist layer 140, 220 open region 15, 28 build-up structure 151, 281 dielectric layer 152, 282 second circuit layer 153, 283 conductive blind hole 154, 231b, 284 electrical contact pad 16, 27 solder mask 160, 270, 271 opening 2 circuit layer structure 21a auxiliary metal layer 21d release film 231 electrical connection Pad 231a wire pad 25 core dielectric layer 13 110783