JP4579258B2 - Bga型パッケージ - Google Patents
Bga型パッケージ Download PDFInfo
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- JP4579258B2 JP4579258B2 JP2007009173A JP2007009173A JP4579258B2 JP 4579258 B2 JP4579258 B2 JP 4579258B2 JP 2007009173 A JP2007009173 A JP 2007009173A JP 2007009173 A JP2007009173 A JP 2007009173A JP 4579258 B2 JP4579258 B2 JP 4579258B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本発明のもう一つの目的は一種のBGA型パッケージ構造を提供し、このBGA型パッケージ構造は、基板上に孔の近くに障碍物を設置することによって基板の下表面にモルド封止剤の溢れるのを確実に阻止することができる。
上述のBGA型パッケージ構造において、その第1封止体は長立方体になっても良い。
上述のBGA型パッケージ構造において、孔は基板上のセンターラインに位置されることができる。
上述のBGA型パッケージ構造において、小口の両側辺は略垂直の端面又は一部が傾斜した略垂直の端面に形成されていても良い。
上述のBGA型パッケージ構造において、小口の両側辺は鋭角状又は曲面状に形成されていても良い。
また、図5に示すように、基板310上の孔313の近くに小口316が形成され、小口316の径は孔313の平均口径よりも狭くなって、孔313の周りに流れるモルド封止剤340の速度を緩めることが可能となり、即ち、第2封止体342の形成を遅らせることによって上下鋳型の圧力差を生じてモルド封止剤340の溢れを防止することができる(説明は後にする)。第一実施例では、小口316の両側辺317は「 > < 」形状すなわち鋭角状の端部、又は「 ) ( 」形状すなわち曲面状の端部として形成されていも良い。
以上、本発明をその好適な実施例に基づいて説明したが、本発明の保護範囲は後付の特許申請範囲で限定されて、この保護範囲に基準して、本発明の精神と範囲内に触れるどんな変更や修正は本発明の保護範囲に属する。
Claims (12)
- 上表面、下表面、及び上表面と下表面とを板厚方向に通じる孔を有する基板と、
基板の上表面に配置され、孔の位置に対応して設けられる複数のボンディングパッドを有するチップと、
孔を通り複数のボンディングパッドを基板に電気的に接続する複数のボンディングワイヤと、
基板の上表面に形成されてチップを密封する第1封止体と、孔と基板の下表面の一部とに跨って設けられ、複数のボンディングワイヤを密封する第2封止体とを有するモルド封止体と、
基板の下表面に形成される複数の半田ボールと、を備え、
基板は、孔を形成する基板の一方の内壁と他方の内壁との間の距離が孔の他の部分よりも狭い小口を孔の一部に有し、この小口は、孔を流れるモルド封止体の速度を遅らせることが可能であること
を特徴とするBGA型パッケージ構造。 - 前記孔に沿って略直方体状に形成された前記第2封止体の長手方向の両端はそれぞれ第1封止体に連結され、第2封止体と第1封止体とが一体になっていることを特徴とする請求項1に記載のBGA型パッケージ構造。
- 前記第1封止体は略直方体状であることを特徴とする請求項1に記載のBGA型パッケージ構造。
- 前記孔は基板上のセンターラインに位置していることを特徴とする請求項1に記載のBGA型パッケージ構造。
- 前記小口を形成する基板の内壁は、上表面および下表面に略垂直、又は上表面および下表面に対して傾斜した面を一部に含み上表面および下表面に略垂直に形成されていることを特徴とする請求項1に記載のBGA型パッケージ構造。
- 前記小口を形成する基板の内壁は、前記孔の延びる方向に鋭角状又は曲面状に形成されていることを特徴とする請求項1に記載のBGA型パッケージ構造。
- 上表面、下表面、及び上表面と下表面とを板厚方向に通じる孔を有する基板と、
基板の上表面に配置され、孔の位置に対応して設けられる複数のボンディングパッドを有するチップと、
孔を通り複数のボンディングパッドを基板に電気的に接続する複数のボンディングワイヤと、
基板の上表面に形成されてチップを密封する第1封止体と、孔と基板の下表面の一部とに跨って設けられ、複数のボンディングワイヤを密封する第2封止体とを有するモルド封止体と、
基板の下表面に形成される複数の半田ボールと、
基板の上表面と孔とに跨って設けられる障碍物と、を備え、
障碍物は、孔を形成する基板の一方の内壁と他方の内壁との間の距離が孔の他の部分よりも狭い小口を孔の一部に形成し、この小口は、孔を流れるモルド封止体の速度を遅らせることが可能であること
を特徴とするBGA型パッケージ構造。 - 障碍物は、基板の上表面とチップとを接着するダイアタッチ層の一部であることを特徴とする請求項7に記載のBGA型パッケージ構造。
- 前記ダイアタッチ層を介してチップを基板に接着させることを特徴とする請求項8に記載のBGA型パッケージ構造。
- 直方体状の前記第2封止体の長手方向の両端はそれぞれ第1封止体に連結され、第2封止体と第1封止体とが一体になっていることを特徴とする請求項7に記載のBGA型パッケージ構造。
- 前記第1封止体は直方体状であることを特徴とする請求項7に記載のBGA型パッケージ構造。
- 前記孔は基板上のセンターラインに位置していることを特徴とする請求項7に記載のBGA型パッケージ構造。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007009173A JP4579258B2 (ja) | 2007-01-18 | 2007-01-18 | Bga型パッケージ |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007009173A JP4579258B2 (ja) | 2007-01-18 | 2007-01-18 | Bga型パッケージ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008177345A JP2008177345A (ja) | 2008-07-31 |
JP4579258B2 true JP4579258B2 (ja) | 2010-11-10 |
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JP2007009173A Expired - Fee Related JP4579258B2 (ja) | 2007-01-18 | 2007-01-18 | Bga型パッケージ |
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JP (1) | JP4579258B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20110092045A (ko) | 2010-02-08 | 2011-08-17 | 삼성전자주식회사 | 휨 및 보이드를 억제하는 몰디드 언더필 플립칩 패키지 |
WO2014022675A1 (en) * | 2012-08-02 | 2014-02-06 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
JP2014116513A (ja) * | 2012-12-11 | 2014-06-26 | Denso Corp | 電子装置 |
KR102084542B1 (ko) * | 2013-08-14 | 2020-03-04 | 삼성전자주식회사 | 반도체 패키지 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001053094A (ja) * | 1999-08-10 | 2001-02-23 | Towa Corp | 樹脂封止方法及び装置 |
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- 2007-01-18 JP JP2007009173A patent/JP4579258B2/ja not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2001053094A (ja) * | 1999-08-10 | 2001-02-23 | Towa Corp | 樹脂封止方法及び装置 |
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