CN111128975A - 集成电路封装件及其形成方法 - Google Patents

集成电路封装件及其形成方法 Download PDF

Info

Publication number
CN111128975A
CN111128975A CN201910386985.9A CN201910386985A CN111128975A CN 111128975 A CN111128975 A CN 111128975A CN 201910386985 A CN201910386985 A CN 201910386985A CN 111128975 A CN111128975 A CN 111128975A
Authority
CN
China
Prior art keywords
integrated circuit
connector
die
wafer
encapsulant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910386985.9A
Other languages
English (en)
Inventor
余振华
吴志伟
施应庆
卢思维
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to CN202310391095.3A priority Critical patent/CN116344521A/zh
Publication of CN111128975A publication Critical patent/CN111128975A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05681—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/1312—Antimony [Sb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

提供了集成电路封装件及其形成方法。方法包括：在晶圆上方堆叠多个集成电路管芯以形成管芯堆叠件。在所述管芯堆叠件上实施接合工艺。所述接合工艺将所述管芯堆叠件的相邻集成电路管芯彼此机械连接和电连接。在所述晶圆上方形成挡块结构。所述挡块结构环绕所述管芯堆叠件。在所述晶圆上方以及在所述管芯堆叠件和所述挡块结构之间形成第一密封剂。所述第一密封剂填充所述管芯堆叠件的相邻集成电路管芯之间的间隙。在所述晶圆上方形成第二密封剂。所述第二密封剂环绕所述管芯堆叠件、所述第一密封剂和所述挡块结构。

Description

集成电路封装件及其形成方法
技术领域
本发明的实施例一般地涉及半导体技术领域，更具体地，涉及集成电路封装件及其形成方法。
背景技术
半导体器件用于各种电子应用中，例如，个人计算机、手机、数字相机、和其他电子装置。通常通过以下步骤来制造半导体器件：在半导体衬底上方顺序地沉积绝缘材料层或介电材料层、导电材料层和半导体材料层；并且使用光刻图案化各个材料层以在其上形成电路部件或元件。通常在单个半导体晶圆上制造几十个或几百个集成电路。通过沿着划线锯切集成电路来切割独立管芯。然后在多芯片模块中或在其他类型的封装中单独地封装独立管芯。
由于各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断改进，半导体工业已经经历了快速增长。在大多数情况下，集成密度的这种改进来自于最小部件尺寸的重复减小(例如，将半导体工艺节点缩小至20nm以下的节点)，从而允许将更多部件集成在给定区域中。近年来，随着对于小型化、更高速度和更大带宽以及更低的功耗和延迟的要求不断增长，对于半导体管芯的更小的、更具有创造性的封装技术的需要也不断增长。
随着半导体技术进一步改进，已经出现了诸如三维集成电路(3DIC)的堆叠的半导体器件作为有效替代物，以进一步减小半导体器件的物理尺寸。在堆叠的半导体器件中，在不同的半导体晶圆上制造诸如逻辑的有源电路、存储器电路、处理器电路等。两个或更多个半导体晶圆可以安装或堆叠在彼此的顶部上，以进一步减小半导体器件的形状系数。叠层封装件(POP)器件是对管芯进行封装，然后与另一封装管芯或多个管芯封装在一起的一种类型的3DIC。封装件上芯片(COP)器件是对管芯进行封装，然后与另一管芯或多个管芯封装在一起的另一种类型的3DIC。
发明内容
根据本发明的一方面，提供了一种用于形成封装件的方法，包括：在晶圆上堆叠多个集成电路管芯以形成管芯堆叠件；在所述管芯堆叠件上实施接合工艺，所述接合工艺将所述管芯堆叠件的相邻集成电路管芯彼此机械连接和电连接；在所述晶圆上方形成挡块结构，所述挡块结构环绕所述管芯堆叠件；在所述晶圆上方以及在所述管芯堆叠件和所述挡块结构之间形成第一密封剂，所述第一密封剂填充所述管芯堆叠件的相邻集成电路管芯之间的间隙；以及在所述晶圆上方形成第二密封剂，所述第二密封剂环绕所述管芯堆叠件、所述第一密封剂和所述挡块结构。
根据本发明的另一方面，提供了一种用于形成封装件的方法，包括：在晶圆上放置第一集成电路管芯，所述晶圆包括位于所述晶圆的第一侧上的第一连接器，所述第一集成电路管芯包括位于所述第一集成电路管芯的第一侧上的第二连接器和位于所述第一集成电路管芯的第二侧上的第三连接器，所述第一集成电路管芯的第一侧与所述第一集成电路管芯的第二侧相对，所述第一连接器与所述第二连接器接触；将第二集成电路管芯放置在所述第一集成电路管芯上，所述第二集成电路管芯包括位于所述第二集成电路管芯的第一侧上的第四连接器和位于所述第二集成电路管芯的第二侧上的第五连接器，所述第二集成电路管芯的第二侧与所述第二集成电路管芯的第一侧相对，所述第三连接器与所述第四连接器接触；在所述第一集成电路管芯和所述第二集成电路管芯上实施接合工艺，所述接合工艺将所述第一连接器和所述第二连接器接合以形成第一连接器接点，所述接合工艺将所述第三连接器和所述第四连接器接合以形成第二连接器接点；所述晶圆上方形成挡块结构，所述挡块结构环绕所述第一集成电路管芯和所述第二集成电路管芯；在所述晶圆上方以及在所述第一连接器接点和所述第二连接器接点周围形成第一密封剂；以及在所述晶圆上方形成第二密封剂，所述第二密封剂围绕所述第一集成电路管芯、所述第二集成电路管芯、所述第一密封剂和所述挡块结构。
根据本发明的又一方面，提供了一种封装件，包括：衬底；挡块结构，位于所述衬底上方，所述挡块结构是环形结构；管芯堆叠件，位于所述衬底上方并且位于所述挡块结构的开口内，所述管芯堆叠件包括多个集成电路管芯和所述多个集成电路管芯中的相邻集成电路管芯之间的连接器接点；第一密封剂，沿着所述多个集成电路管芯的侧壁延伸，所述第一密封剂围绕所述连接器接点；以及第二密封剂，围绕所述管芯堆叠件、所述第一密封剂、和所述挡块结构。
附图说明
当结合附图进行阅读时，根据以下详细的描述来更好地理解本发明的各个方面。注意，根据工业的标准实践，各个部件没有按比例绘制。实际上，为了讨论的清楚，可以任意地增加或减小各个部件的尺寸。
图1至图4、图5A、图5B以及图6至图11示出了根据一些实施例的在制造集成电路封装件期间各个处理步骤的顶视图和截面图。
图12是根据一些实施例的形成集成电路封装件的方法的流程图。
具体实施方式
本发明提供了许多不同的用于实施本发明的不同特征的实施例或实例。以下描述部件或配置的具体实例以简化本发明。当然，这些仅仅是实例而不用于限制。例如，在以下的描述中，在第二部件上方或之上形成第一部件可以包括第一部件和第二部件被形成为直接接触的实施例，并且也可以包括可以在第一部件和第二部件之间形成附件部件使得第一部件和第二部分没有直接接触的实施例。此外，本发明可以在各个实例中重复参考标号和/或字母。这些重复是为了简化和清楚，其本身并不表示所讨论的各个实施例和/或结构之间的关系。
此外，为了易于描述，可以使用空间相对术语(诸如“在…下方”、“在…之下”、“下部”、“上方”、“上部”等)以描述图中所示的一个元件或部件与另一个(一些)元件或部件的关系。除图中所示的定向之外，空间相对术语还包括使用或操作中设备的不同定向。装置可以以其他方式定向(旋转90度或处于其他定向)，本文所使用的空间相对描述符可因此进行类似的解释。
结合具体上下文的实施例描述多个实施例，即，集成电路封装件及其形成方法。然而，其他实施例也可以应用于处于组合封装中、处理衬底中、中介层等中的其他电连接部件(包括但不限于叠层封装件组件、管芯与管芯组件、晶圆与晶圆组件、管芯与衬底组件)；或者应用于安装输入部件、板、管芯或用于任何类型的集成电路或电部件的连接封装或安装组合的其他部件。本文中所述的各种实施例允许通过以下步骤来形成集成电路封装件：将集成电路管芯布置在管芯堆叠件中并且使用应用于管芯堆叠件的单个接合工艺将管芯堆叠件的相邻集成电路管芯彼此结合，而在接合工艺期间没有将附加的外力施加在管芯堆叠件上。本文中所述的各种实施例进一步允许在相邻集成电路管芯之间的间隙中形成密封剂材料，而在密封剂材料没有形成空隙，并且允许改进密封剂材料的间隙填充性能。本文中所述的各种实施例进一步允许在形成集成电路封装件期间减小晶圆翘曲。
图1至图4、图5A、图5B以及图6至图11示出了根据一些实施例制造集成电路(IC)封装件(例如图10中所示的IC封装件1001)期间的各种工艺步骤的顶视图和截面图。参考图1，工艺从将晶圆105结合至载体101开始，以开始形成晶圆级管芯结构100。在一些实施例中，使用粘合层103将晶圆105附接至载体101。在一些实施例中，载体101可以包括硅、石英、陶瓷、玻璃、它们的组合等并且提供用于随后在晶圆105上执行的操作的机械支撑。在一些实施例中，粘合层103可以包括光热转换(LTHC)材料、UV粘合层、聚合物层、它们的组合等，并且可以使用旋涂工艺、印刷工艺、层压工艺、它们的组合等来形成该粘合层。在粘合层103由材料形成的一些实施例中，在粘合层103暴露于光时，该粘合层部分地或完全丢失其粘合强度，并且在完成晶圆级管芯结构100的形成之后，可以从晶圆级管芯结构100的背侧容易地去除载体101。
在一些实施例中，晶圆105包括衬底(未单独地示出)、衬底上的一个或多个有源器件和/或无源器件(未单独地示出)以及一个或多个有源器件和/或无源器件和衬底上方的互连结构(未单独地示出)。在一些实施例中，衬底可以由硅形成，但是衬底也可以由其他的III族元素、IV族元素和/或V族元素形成，诸如，硅、锗、镓、砷和它们的组合。衬底也可以具有绝缘体上硅(SOI)的形式。SOI衬底可以包括形成在绝缘体层(例如，掩模氧化物等)上方的半导体材料层(例如，硅、锗等)，其中，该绝缘体层形成在硅衬底上。另外，可以使用的其他衬底包括多层衬底、梯度衬底、混合定向衬底、它们的任何组合等。
在一些实施例中，晶圆105进一步包括形成在衬底上的一种或多种有源器件和/或无源器件(未单独地示出)。一种或多种有源器件和/或无源器件可以包括各种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)器件，诸如，晶体管、电容器、电阻器、二极管、光电二极管、熔丝等。
在一些实施例中，晶圆105进一步包括形成在衬底和一种或多种有源器件和/或无源器件上方的互连结构(未单独地示出)。互连结构可以包括多个介电层(诸如层间介电(ILD)层/金属间介电层(IMD))和介电层内的互连件(诸如导线和通孔)。例如，介电层可以通过本领域中已知的任何合适的方法(诸如，旋涂方法、化学汽相沉积(CVD)、等离子体增强的CVD(PECVD)、它们的组合等)由低k介电材料形成，诸如磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、它们的化合物、它们的复合物、它们的组合等。在一些实施例中，例如，可以使用镶嵌工艺、双镶嵌工艺、它们的组合等在介电层中形成互连件。在一些实施例中，互连件可以包括铜、铜合金、银、金、钨、钽、铝、它们的组合等。在一些实施例中，互连件可以提供形成在衬底上的一种或多种有源器件和/或无源器件之间的电连接。
在一些实施例中，晶圆105进一步包括从晶圆105的第一表面105A朝向晶圆105的第二表面105B延伸的通孔(TV)111。在一些实施例中，可以通过以下步骤来形成TV 111：在晶圆105中形成开口并且将该开口填充有适当的导电材料。在一些实施例中，可以使用适当的光刻方法和蚀刻方法来形成开口。在一些实施例中，开口使用物理汽相沉积(PVD)、原子层沉积(ALD)、电化学镀、化学镀或它们的组合等填充有铜、铜合金、银、金、钨、钽、铝、它们的组合等。在一些实施例中，在将开口填充适当的导电材料之前，可以在开口中形成衬里层和/或粘合层/阻挡层。在一些实施例中，可以对TV 111的导电材料实施平坦化工艺，以去除导电材料的多余部分。平坦化工艺可以包括化学机械抛光(CMP)工艺、研磨工艺、蚀刻工艺、它们的组合等。
在一些实施例中，晶圆105进一步包括形成在晶圆105的第一表面105A上的连接器107和形成在晶圆105的第二表面105B上的连接器109。在一些实施例中，每个连接器107都包括导电柱凸块107A和位于导电柱凸块107A上的焊料元件107B。在一些实施例中，导电柱凸块107A可以包括导电材料，诸如铜、钨、铝、银、金、它们的组合等。在一些实施例中，焊料元件107B可以包括诸如PbSn成分的基于铅的焊料；包括InSb、锡、银和铜(“SAC”)成分的无铅焊料以及其他共晶材料，该共晶材料具有共同的熔点并且在电应用中形成导电焊料连接。对于无铅焊料，作为示例，可以使用改变成分的SAC焊料，例如，SAC 105(98.5％的Sn、1.0％的Ag、0.5％的Cu)、SAC 305和SAC 405。无铅焊料还包括：SnCu化合物而没使用银(Ag)；和SnAg化合物而没有使用铜(Cu)。
在一些实施例中，形成导电柱凸块107A的方法可以包括：在第一表面105A上方形成导电晶种层，在导电晶种层上方形成牺牲材料(诸如，光刻胶材料)，图案化牺牲材料以在牺牲材料中形成开口，使用电化学镀工艺、非电镀工艺、ALD、PVD、它们的组合等在开口中沉积导电材料，去除牺牲层并且去除导电晶种层的暴露部分。在一些实施例中，在去除牺牲层之前，使用蒸发、电化学镀工艺、非电镀工艺、印刷、焊料转移、它们的组合等在开口中的导电柱凸块107A的导电材料上方形成焊料材料。在一些实施例中，可以对焊料元件107B实施回流工艺以将焊料材料成形为期望的凸块形状。在其他实施例中，连接器107可以是焊球、可控坍塌芯片连接(C4)凸块、球栅阵列(BGA)球、微凸块、化学镀镍-化学镀钯-浸金技术(ENEPIG)所形成的凸块、它们的组合等。
在一些实施例中，连接器109可以类似于连接器107，并且可以使用与连接器107类似的材料和方法形成该连接器109，并且本文中没有重复该描述。在一些实施例中，每个连接器109都包括导电柱凸块109A和位于导电柱凸块109A上方的焊料元件109B。在一些实施例中，使用与导电柱凸块类似的材料和方法来形成导电柱凸块109A，并且本文中没有重复该描述。在一些实施例中，可以使用与焊料元件107B类似的材料和方法来形成焊料元件109B，并且本文中没有重复该描述。在一些实施例中，在形成焊料元件109B之后，没有实施回流工艺。
在一些实施例中，晶圆105可以是中间晶圆。在这样的实施例中，晶圆可以不包括位于衬底上的一个或多个有源器件和/或无源器件。在其他实施例中，晶圆105可以是IC晶圆。在这样的实施例中，晶圆105包括衬底上的一个或多个有源器件和/或无源器件。
参考图2，IC管芯201A放置在晶圆105上以开始在晶圆105上形成管芯堆叠件(诸如在图4中所示的管芯堆叠件401)。IC管芯201A可以包括逻辑管芯、存储器管芯、CPU、GPU、xPU、MEMS管芯、SoC管芯等。在一些实施例中，每个IC管芯201A都可以包括衬底(未独立地示出)、位于衬底上的一个或多个有源器件和/或无源器件(未独立地示出)以及位于衬底和一个或多个有源器件和/或无源器件上方的互连结构(未独立地示出)。在一些实施例中，可以使用与上文中参考图1所述的晶圆105的衬底类似的材料和方法来形成IC管芯201A的衬底，并且本文中没有重复该描述。在一些实施例中，使用与上文中参考图1所述的晶圆105的一个或多个有源器件和/或无源器件类似的材料和方法来形成IC管芯201A的一个或多个有源器件和/或无源器件，并且本文中没有重复描述。在一些实施例中，可以使用与上文中参考图1所述的晶圆105的互连结构类似的材料和方法来形成IC管芯201A的互连结构，并且本文中没有重复描述。在一些实施例中，IC管芯201A可以具有在大约20μm和大约50μm之间的厚度。
在一些实施例中，多个IC管芯201A中的每个进一步包括：通孔(TV)203A，从IC管芯201A的下表面朝向IC管芯201A的上表面延伸；连接器205A，位于IC管芯201A的下表面上；以及连接器207A，位于IC管芯201A的上表面上。在一些实施例中，可以使用与上文中参考图1所述的TV 111类似的材料和方法来形成TV 203A，并且本文中没有重复该描述。在一些实施例中，连接器205A和207A可以类似于上文中参考图1所述的连接器107，并且可以使用与上文中参考图1所述的连接器107类似的材料和方法来形成连接器205A和207A，并且本文中没重复该描述。在一些实施例中，多个连接器205A中的每个都可以包括导电柱凸块205A1和位于导电柱凸块205A1上方的焊料元件205A2。在一些实施例中，可以使用与上文中参考图1所述的导电柱凸块107A类似的材料和方法来形成导电柱凸块205A1，并且本文中没有重复该描述。在一些实施例中，可以使用与上文中参考图1所述的焊料元件107B类似的材料和方法来形成焊料元件205A2，并且本文中没有重复该描述。
在一些实施例中，每个连接器207A都可以包括导电柱凸块207A1和位于导电柱凸块207A1上方的焊料元件207A2。在一些实施例中，可以使用与上文中参考图1所述的导电柱凸块107A类似的材料和方法来形成导电柱凸块207A1并且本文中没有重复该描述。在一些实施例中，可以使用与上文中参考图1所述的焊料元件107B类似的材料和方法来形成焊料元件207A2并且本文中没有重复该描述。在一些实施例中，在形成焊料元件205A2和207A2之后，没有实施回流工艺。
此外，参考图2，在一些实施例中，可以使用拾取和放置装置将多个IC管芯201A放置在晶圆105上。在其他实施例中，可以手动地或使用任何其他合适的方法将多个IC管芯201A放置在晶圆105上。在一些实施例中，在将多个IC管芯201A放置在晶圆105之前，将多个IC管芯201A浸入助焊剂材料209中。在一些实施例中，助焊剂材料209将多个IC管芯201A预接合至晶圆105。在一些实施例中，多个IC管芯201A可以相对于晶圆105的连接器109对准，使得多个IC管芯201A的连接器205A放置在晶圆105的连接器109上。在一些实施例中，在将多个IC管芯201A放置在晶圆105上期间或在将多个IC管芯201A放置在晶圆105上之后，但是在附加的多个IC管芯放置在多个IC管芯201A上之前，没有附加的外力(诸如，与由于多个IC管芯201A的重量而产生的重力不同的力)施加至多个IC管芯201A。在一些实施例中，在将多个IC管芯201A放置在晶圆105上期间或者在将多个IC管芯201A放置在晶圆105上之后，但是在将附加的多个IC管芯放置在多个IC管芯201A上之前，没有实施附加工艺步骤以将多个IC管芯201A的连接器205A预接合或接合至晶圆105的连接器109。
参考图3，多个IC管芯201B至201G和301放置在相应的多个IC管芯201A上方以在晶圆105上形成预接合的管芯堆叠件305。在一些实施例中，多个IC管芯201X(其中，X＝B、C、...、G)可以类似于上文中参考图2所述的多个IC管芯201A并且本文中没有重复该描述。在一些实施例中，多个IC管芯201X(其中，X＝B、C、...、G)中的每个进一步包括通孔(TV)203X(其中，X＝B、C、...、G)，从多个IC管芯201X(其中，X＝B、C、...、G)的下表面朝向多个IC管芯201X(其中，X＝B、C、...、G)的上表面延伸；连接器205X(其中，X＝B、C、...、G)位于多个IC管芯201X(其中，X＝B、C、...、G)的下表面上；和连接器207X(其中，X＝B、C、...、G)位于多个IC管芯201X(其中，X＝B、C、...、G)的上表面上。每个连接器205X(其中，X＝B、C、...、G)都包括导电柱凸块205X1(其中，X＝B、C、...、G)和位于导电柱凸块205X1(其中，X＝B、C、...、G)上方的焊料元件205X2(其中，X＝B、C、...、G)。在一些实施例中，可以使用与上文中参考图1所述的导电柱凸块107A类似的材料和方法来形成导电柱凸块205X1(其中，X＝B、C、...、G)并且本文中没有重复该描述。在一些实施例中，可以使用与上文中参考图1所述的焊料元件107B类似的材料和方法来形成焊料元件205X2(其中，X＝B、C、...、G)并且本文中没有重复该描述。每个连接器207X(其中，X＝B、C、...、G)都包括导电柱凸块207X1(其中，X＝B、C、...、G)和位于导电柱凸块207X1(其中，X＝B、C、...、G)上方的焊料元件207X2(其中，X＝B、C、...、G)。在一些实施例中，可以使用与上文中参考图1所述的导电柱凸块107A类似的材料和方法来形成导电柱凸块207X1(其中，X＝B、C、...、G)，并且本文中没有重复该描述。在一些实施例中，可以使用与上文中参考图1所述的焊料元件107B类似的材料和方法来形成焊料元207X2(其中，X＝B、C、...、G)，并且本文中没有重复该描述。在一些实施例中，在形成焊料元件205X2(其中，X＝B、C、...、G)和207X2(其中，X＝B、C、...、G)之后，没有实施回流工艺。在一些实施例中，多个IC管芯201X(其中，X＝A、B、C、...、G)可以具有相同的厚度。在其他实施例中，多个IC管芯201X(其中，X＝A、B、C、...、G)可以具有不同的厚度。
在一些实施例中，多个IC管芯301可以类似于多个IC管芯201X(其中，X＝A、B、C、...、G)并且本文中没有重复该描述。在一些实施例中，多个IC管芯301的厚度大于多个IC管芯201X(其中，X＝A、B、C、...、G)中的每个的厚度。在一些实施例中，多个IC管芯301中的每个进一步包括位于多个IC管芯301的下表面上的连接器303。每个连接器303都包括导电柱凸块3031和位于导电柱凸块3031上方的焊料元件3032。在一些实施例中，可以使用与上文中参考图1所述的导电柱凸块107A类似的材料和方法来形成导电柱凸块3031，并且本文中没有重复该描述。在一些实施例中，可以使用与上文中参考图1所述的焊料元件107B类似的材料和方法来形成焊料元件3032，并且本文中没有重复该描述。在一些实施例中，在形成焊料元件3032之后，没有在预接合的管芯堆叠件305上实施回流工艺。
进一步参考图3，使用与上文中参考图2所述的将多个IC管芯201A放置在晶圆105上的方法类似的方法，在相应的多个IC管芯201A上方堆叠多个IC管芯201X(其中，X＝B、C、...、G)和301并且本文中没有重复该描述。在一些实施例中，在将多个IC管芯201X(其中，X＝B、C、...、G)和301放置在以前的多个IC管芯上方以形成预接合的管芯堆叠件305之前，多个IC管芯201X(其中，X＝B、C、...、G)和301浸入助焊剂材料209中。在一些实施例中，助焊剂材料209将预接合的管芯堆叠件305中的相邻IC管芯(诸如，IC管芯201A和201B、IC管芯201B和201C、IC管芯201C和201D、IC管芯201D和201E、IC管芯201E和201F、IC管芯201F和201G、以及IC管芯201G和301)预接合以形成预接合的管芯堆叠件305。在一些实施例中，在形成预接合的管芯堆叠件305期间，没有附加的外力(诸如，与由于IC管芯的重量所产生的重力不同的力)施加至多个IC管芯(其中，X＝B、C、...、G)和301。在一些实施例中，在形成预接合的管芯堆叠件305期间，没有实施附加的工艺步骤以将连接器207A预接合或接合至连接器205B、将连接器207B预接合或接合至连接器205C、将连接器207C预接合或接合至连接器205D、将连接器207D预接合或接合至连接器205E、将连接器207E预接合或接合至连接器205F、将连接器207F预接合或接合至连接器205G、以及将连接器207G预接合或接合至连接器303。
参考图4，在预接合的管芯堆叠件305(参见图3)上实施单个接合工艺，以形成接合的管芯堆叠件401。单个接合工艺将每个连接器109(参见图3)接合至多个连接器205A(参见图3)中的相应一个，以形成连接器接点403A，每个连接器207A(参见图3)接合至多个连接器205B(参见图3)中的相应一个以形成连接器接点403B，每个连接器207B(参见图3)接合至多个连接器205C(参见图3)中的相应一个以形成连接器接点403C，每个连接器207C(参见图3)接合至多个连接器205D(参见图3)中的相应一个以形成连接器接点403D，每个连接器207D(参见图3)接合至多个连接器205E(参见图3)中的相应一个以形成连接器接点403E，每个连接器207E(参见图3)接合至多个连接器205F(参见图3)中的相应一个以形成连接器接点403F，每个连接器207F(参见图3)接合至多个连接器205G(参见图3)中的相应一个以形成连接器接点403G，每个连接器207G(参见图3)接合至多个连接器303(参见图3)中的相应一个以形成连接器接点403H。对于每个接合的管芯堆叠件401，单个接合工艺将多个IC管芯201A至201G和301彼此机械连接和电连接。
在一些实施例中，单个接合工艺是焊料回流工艺。焊料回流工艺使连接器109(参见图3)的焊料元件1092和连接器205A(参见图3)的焊料元件205A2回流为相应的连接器接点403A的焊料接点401A，将连接器207A(参见图3)的焊料元件207A2和连接器205B(参见图3)的焊料元件205B2回流为相应的连接器接点403B的焊料接点401B，将连接器207B(参见图3)的焊料元件207B2和连接器205C(参见图3)焊料元件205C2回流为相应的连接器接点403C的焊料接点401C，将连接器207C(参见图3)的焊料元件207C2和连接器205D(参见图3)的焊料元件205D2回流为连接器接点403D的焊料接点401D，将连接器207D(参见图3)的焊料元件207D2和连接器205E(参见图3)的焊料元件205E2回流为相应的连接器接点403E的焊料接点401E，将连接器207E(参见图3)的焊料元件207E2和连接器205F(参见图3)的焊料元件205F2回流为相应的连接器接点403F的焊料接点401F，将连接器207F(参见图3)的焊料元件207F2和连接器205G(参见图3)的焊料元件205G2回流为相应的连接器接点403G的焊料接点401G，以及将连接器207G(参见图3)焊料元件207G2和连接器303(参见图3)的焊料元件3032回流为相应的连接器接点403H的焊料接点401H。在一些实施例中，在实施单个接合工艺期间，没有附加的外力(诸如与由于多个IC管芯201A至201G和301的重量所产生的重力不同的力)施加至预接合的管芯堆叠件305(参见图3)。在其他实施例中，单个接合工艺是热压接合工艺等。在一些实施例中，在形成连接器接点403A至403H之后，使用适当的去除工艺去除助焊剂材料209(参见图3)。
图5A和图5B示出了在接合的管芯堆叠件401周围形成挡块结构501。图5A示出了顶视图。图5B示出了沿着图5A所述的线AA的截面图。图5A和图5B示出了附接至晶圆105并且通过晶圆105的划线503彼此切割的接合的管芯堆叠件401。在一些实施例中，挡块结构501是环绕相应的接合的管芯堆叠件401的环形结构。在一些实施例中，挡块结构501位于通过划线503切割的晶圆105的多个区域内。在一些实施例中，挡块结构501与划线503不重叠。在一些实施例中，每个挡块结构501可以包括金属材料、聚合物材料、介电材料、绝缘材料或它们的组合等。在一些实施例中，挡块结构501的材料形成在晶圆105的暴露部分上方，随后进行图案化以形成挡块结构501。在一些实施例中，图案化工艺可以包括适当的光刻和蚀刻工艺。在其他实施例中，可以使用印刷工艺、层压工艺、分配工艺或它们的组合等形成挡块结构501。在一些实施例中，挡块结构501在图5B所示的截面图中具有高度H1和宽度W1。在一些实施例中，挡块结构501的高度H1小于接合的管芯堆叠件401的高度H2。在一些实施例中，高度H1在大约20μm和大约1000μm之间。在一些实施例中，高度H2在大约50μm和大约1000μm之间。在一些实施例中，宽度W1在大约50μm和大约1000μm之间。在一些实施例中，H1/H2的比率在大约0.1和大约2之间。在一些实施例中，H1/W1的比率在大约0.1和大约10之间。
在图5A所示的实施例中，每个挡块结构501的平面图形状为矩形环形状。在一些实施例中，矩形环形状的外周长具有在大约5mm和大约50mm之间的第一宽度W2以及在大约5mm和大约50mm之间的第二宽度W3。在一些实施例中，W2/W3的比率在大约0.1和大约10之间。在一些实施例中，矩形环形状和多个管芯堆叠件401中的相应一个之前的距离D1在大约50μm和大约2000μm之间。在其他实施例中，每个挡块结构501的平面图形状可以是如图6所示的正方形环形状601、圆环形状603、椭圆环形状605等。在一些实施例中，可以基于接合的管芯堆叠件401的平面图形状调节挡块结构501的平面图形状。
参考图7，在接合的管芯堆叠件401周围形成挡块结构501之后，底部填充物701形成在挡块结构501的开口中以及管芯堆叠件401周围。在一些实施例中，底部填充物701进一步形成在接合的管芯堆叠件401的多个IC管芯201A至201G和301中的相邻IC管芯之间的间隙中以及多个IC管芯201A和晶圆105之间的间隙中。底部填充物701环绕并保护连接器接点403A至403H。在一些实施例中，液态底部填充物材料通过毛细管作用进行分配并且固化以形成底部填充物701。在一些实施例中，底部填充物701包括环氧基树脂与分配在其中的填充剂。填充剂可以包括纤维、颗粒、其他合适的要素、它们的组合等。在一些实施例中，通过形成挡块结构501，控制底部填充物701的横向扩散，从而改善了底部填充物701的间隙填充性能。在一些实施例中，可以进一步改变底部填充物701的材料性能以改善底部填充物701的间隙填充性能。在一些实施例中，可以减小分布在底部填充物701的底部填充物材料中的填充剂的尺寸。在一些实施例中，可以选择底部填充物701的底部填充物材料以具有在大约40℃和大约200℃之间的玻璃转换温度Tg。在一些实施例中，可以选择底部填充物701的底部填充物材料以具有在大约5ppm/℃和大约50ppm/℃之间的热膨胀系数(CTE)。在一些实施例中，可以选择底部填充物701的底部填充物材料以具有在大约0.1GPa和大约20GPa之间的杨氏模量。在所示的实施例中，挡块结构501防止底部填充物701在晶圆105上方形成连续层，从而可以防止由于CTE失配而导致的晶圆105的翘曲，并且因此，可以降低或防止连接器接点403A至403H的连接故障。在一些实施例中，底部填充物701具有倾斜侧壁。
参考图8，在形成底部填充物701之后，密封剂801形成在晶圆105上方并且环绕管芯堆叠件401和挡块结构501。在一些实施例中，密封剂801可以包括模塑料，例如环氧基树脂、合成树脂、可模制聚合物、它们的组合等以及分散在其中的填充剂。可以在基本液态时施加模塑料，然后可以通过化学反应进行固化。填充剂可以包括绝缘纤维、绝缘颗粒、其他合适的要素、它们的组合等。在一些实施例中，可以使用与上文中参考图7所述的底部填充物701类似的材料和方法来形成密封剂801，并且本文中没有重复该描述。在一些实施例中，密封剂801和底部填充物701包括相同的材料。在一些实施例中，密封剂801和底部填充物701包括不同的材料。在一些实施例中，分布在密封剂801中的填充剂的尺寸和/或密度大于分布在底部填充物701中的填充剂的尺寸和/或密度。在其他实施例中，密封剂801可以是能够设置在管芯堆叠件401和挡块结构501周围和之间的用作凝胶或可塑性固体的紫外线(UV)或者热固化聚合物。在又一些实施例中，密封剂801可以包括介电材料，诸如氧化物。在一些实施例中，可以对密封剂801实施平坦化工艺以去除密封剂801的多余部分，使得密封剂801的最上表面与管芯堆叠件401的最上表面基本齐平。在一些实施例中，平坦化工艺还可以去除多个IC管芯301的上部并且减薄多个IC管芯301。在一些实施例中，平坦化工艺可以包括CMP工艺、蚀刻工艺、研磨、它们的组合等。
参考图9，在形成密封剂801之后，将载体101与晶圆级管芯结构100分离(de-bond，又称脱粘或去除)。在一些实施例中，在载体101与晶圆级管芯结构100分离之后，还去除粘合层103以暴露连接器107。在一些实施例中，可以使用适当的清洁工艺去除粘合层103。
参考图10，在将载体101与晶圆级管芯结构100分离之后，沿着划线503(参见图5A)切割晶圆级管芯结构100以形成独立的IC封装件1001。在一些实施例中，每个IC封装件1001包括接合的管芯堆叠件401和相应的挡块结构501。在一些实施例中，晶圆级管芯结构100可以通过例如锯切、激光烧蚀、蚀刻、它们的组合等切割为独立的IC封装件1001。
参考图11，在一些实施例中，IC封装件1001使用连接器107机械地或电附接至工件1101。在一些实施例中，可以实施回流工艺，以将IC封装件1001接合至工件1101。在一些实施例中，工件1101可以包括集成电路管芯、封装衬底、印刷电路板(PCB)、陶瓷衬底等。
图12是示出根据一些实施例的形成集成电路封装件的方法1200的流程图。方法从步骤1201开始，其中，如上文中参考图1所述的，晶圆(例如，图1中所示的晶圆105)附接至载体(例如，图1中所示的载体101)。在步骤1203中，如上文中参考图2和图3所述的，集成电路管芯(例如，图3中所示的多个IC管芯201A至201G和301)放置在晶圆上以形成管芯堆叠件(例如，图3中所示的管芯堆叠件305)。在步骤1205中，如参考图4所述的，在管芯堆叠件上实施单个接合工艺。在步骤1207中，如上文中参考图5A和图5B所述的，挡块结构(例如，图5A和图5B中所示的挡块结构501)形成在晶圆上方以及管芯堆叠件周围。在步骤1209中，如上文中参考图7所述的，第一密封剂(例如，图7中所示的底部填充物701)形成在挡块结构内以及管芯堆叠件周围。在步骤1211中，如上文中参考图8所述的，第二密封剂(例如，图8中所示的密封剂801)形成在晶圆上方以及挡块结构、管芯堆叠件、和第一密封剂周围。在步骤1213中，如上文中参考图9所述的，将载体与生成的结构(例如，图9中所示的晶圆级管芯结构100)分离。在步骤1215中，如上文中参考图10所述的，将生成的结构切割为独立的集成电路封装件(例如，图10中所示的IC封装件)。
根据实施例，方法包括：在晶圆上堆叠多个集成电路管芯以形成管芯堆叠件；在所述管芯堆叠件上实施接合工艺，所述接合工艺将所述管芯堆叠件的相邻集成电路管芯彼此机械连接和电连接；在所述晶圆上方形成挡块结构，所述挡块结构环绕所述管芯堆叠件；在所述晶圆上方以及所述管芯堆叠件和所述挡块结构之间形成第一密封剂，所述第一密封剂填充所述管芯堆叠件的相邻集成电路管芯之间的间隙；以及在所述晶圆上方形成第二密封剂，所述第二密封剂环绕所述管芯堆叠件、所述第一密封剂和所述挡块结构。在实施例中，方法进一步包括：在所述晶圆上堆叠所述多个集成电路管芯之前，将所述晶圆附接至载体。在实施例中，实施所述接合工艺包括实施焊料回流工艺。在实施例中，在所述晶圆上堆叠所述多个集成电路管芯包括：在将所述多个集成电路管芯中的每个放置在所述晶圆上之前，将所述多个集成电路管芯中的每个浸入助焊剂材料中。在实施例中，在所述管芯堆叠件上实施所述接合工艺包括在所述管芯堆叠件的相邻集成电路管芯之间形成多个连接器接点。在实施例中，所述挡块结构是环形结构。在实施例中，所述管芯堆叠件和所述第一密封剂设置在所述挡块结构的开口中。
在实施例中，方法进一步包括：在所述晶圆上堆叠所述多个集成电路管芯之前，将所述晶圆附接至载体。
在实施例中，实施所述接合工艺包括实施焊料回流工艺。
在实施例中，在所述晶圆上堆叠所述多个集成电路管芯包括：在将所述多个集成电路管芯中的每个放置在所述晶圆上之前，将所述多个集成电路管芯中的每个浸入助焊剂材料中。
在实施例中，在所述管芯堆叠件上实施所述接合工艺包括在所述管芯堆叠件的相邻集成电路管芯之间形成多个连接器接点。
在实施例中，所述挡块结构是环形结构。
在实施例中，所述管芯堆叠件和所述第一密封剂设置在所述挡块结构的开口中。
根据另一实施例，方法包括：在晶圆上放置第一集成电路管芯，所述晶圆包括位于所述晶圆的第一侧上的第一连接器，所述第一集成电路管芯包括位于所述第一集成电路管芯的第一侧上的第二连接器和位于所述第一集成电路管芯的第二侧上的第三连接器，所述第一集成电路管芯的第一侧与所述第一集成电路管芯的第二侧相对，所述第一连接器与所述第二连接器接触；将第二集成电路管芯放置在所述第一集成电路管芯上，所述第二集成电路管芯包括位于所述第二集成电路管芯的第一侧上的第四连接器和位于所述第二集成电路管芯的第二侧上的第五连接器，所述第二集成电路管芯的第二侧与所述第二集成电路管芯的第一侧相对，所述第三连接器与所述第四连接器接触；在所述第一集成电路管芯和所述第二集成电路管芯上实施接合工艺，所述接合工艺将所述第一连接器和所述第二连接器接合以形成第一连接器接点，所述接合工艺将所述第三连接器和所述第四连接器接合以形成第二连接器接点；所述晶圆上方形成挡块结构，所述挡块结构环绕所述第一集成电路管芯和所述第二集成电路管芯；在所述晶圆上方以及所述第一连接器接点和所述第二连接器接点周围形成第一密封剂；以及在所述晶圆上方形成第二密封剂，所述第二密封剂围绕所述第一集成电路管芯、所述第二集成电路管芯、所述第一密封剂和所述挡块结构。在实施例中，实施所述接合工艺包括在所述第一连接器、所述第二连接器、所述第三连接器和所述第四连接器上实施焊料回流工艺。在实施例中，所述接合工艺将所述第一连接器的每个的第一焊料层与所述第二连接器中的相应一个的第二焊料层合并以形成第一单个焊料层。在实施例中，所述接合工艺将所述第三连接器的每个的第三焊料层与所述第四连接器中的相应一个的第四焊料层合并以形成第二单个焊料层。在实施例中，方法进一步包括在将所述第一集成电路管芯放置在所述晶圆上之前，将所述第一集成电路管芯浸入助焊剂材料中。在实施例中，方法进一步包括在将所述第二集成电路管芯放置在所述晶圆上之前，将所述第二集成电路管芯浸入所述助焊剂材料中。在实施例中，所述挡块结构的第一侧壁与所述第一密封剂接触，其中，所述挡块结构的第二侧壁与所述第二密封剂接触，并且其中，所述挡块结构的第一侧壁与所述挡块结构的第二侧壁相对。
在实施例中，实施所述接合工艺包括在所述第一连接器、所述第二连接器、所述第三连接器和所述第四连接器上实施焊料回流工艺。
在实施例中，所述接合工艺将所述第一连接器的每个的第一焊料层与所述第二连接器中的相应一个的第二焊料层合并以形成第一单个焊料层。
在实施例中，所述接合工艺将所述第三连接器的每个的第三焊料层与所述第四连接器中的相应一个的第四焊料层合并以形成第二单个焊料层。
在实施例中，方法进一步包括在将所述第一集成电路管芯放置在所述晶圆上之前，将所述第一集成电路管芯浸入助焊剂材料中。
在实施例中，方法进一步包括在将所述第二集成电路管芯放置在所述晶圆上之前，将所述第二集成电路管芯浸入所述助焊剂材料中。
在实施例中，所述挡块结构的第一侧壁与所述第一密封剂接触，所述挡块结构的第二侧壁与所述第二密封剂接触，并且所述挡块结构的第一侧壁与所述挡块结构的第二侧壁相对。
根据又一实施例，封装件包括：衬底；挡块结构，位于所述衬底上方，所述挡块结构是环形结构；管芯堆叠件，位于所述衬底上方并且位于所述挡块结构的开口内，所述管芯堆叠件包括多个集成电路管芯和所述多个集成电路管芯中的相邻集成电路管芯之间的连接器接点；第一密封剂，沿着所述多个集成电路管芯的侧壁延伸，所述第一密封剂围绕所述连接器接点；以及第二密封剂，围绕所述管芯堆叠件、所述第一密封剂、和所述挡块结构。在实施例中，所述第一密封剂填充所述挡块结构的开口。在实施例中，所述挡块结构的第一侧壁与所述第一密封剂接触，其中，所述挡块结构的第二侧壁与所述第二密封剂接触，并且其中，所述挡块结构的第一侧壁与所述挡块结构的第二侧壁相对。在实施例中，所述第一密封剂具有倾斜侧壁。在实施例中，所述管芯堆叠件的最上表面与所述第二密封剂的最上表面齐平。在实施例中，所述第二密封剂的侧壁与所述衬底的侧壁共面。
在实施例中，所述第一密封剂填充所述挡块结构的开口。
在实施例中，所述挡块结构的第一侧壁与所述第一密封剂接触，所述挡块结构的第二侧壁与所述第二密封剂接触，并且所述挡块结构的第一侧壁与所述挡块结构的第二侧壁相对。
在实施例中，所述第一密封剂具有倾斜侧壁。
在实施例中，所述管芯堆叠件的最上表面与所述第二密封剂的最上表面齐平。
在实施例中，所述第二密封剂的侧壁与所述衬底的侧壁共面。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种用于形成封装件的方法，包括：
在晶圆上堆叠多个集成电路管芯以形成管芯堆叠件；
在所述管芯堆叠件上实施接合工艺，所述接合工艺将所述管芯堆叠件的相邻集成电路管芯彼此机械连接和电连接；
在所述晶圆上方形成挡块结构，所述挡块结构环绕所述管芯堆叠件；
在所述晶圆上方以及在所述管芯堆叠件和所述挡块结构之间形成第一密封剂，所述第一密封剂填充所述管芯堆叠件的相邻集成电路管芯之间的间隙；以及
在所述晶圆上方形成第二密封剂，所述第二密封剂环绕所述管芯堆叠件、所述第一密封剂和所述挡块结构。
2.根据权利要求1所述的方法，进一步包括：在所述晶圆上堆叠所述多个集成电路管芯之前，将所述晶圆附接至载体。
3.根据权利要求1所述的方法，其中，实施所述接合工艺包括实施焊料回流工艺。
4.根据权利要求1所述的方法，其中，在所述晶圆上堆叠所述多个集成电路管芯包括：在将所述多个集成电路管芯中的每个放置在所述晶圆上之前，将所述多个集成电路管芯中的每个浸入助焊剂材料中。
5.根据权利要求1所述的方法，其中，在所述管芯堆叠件上实施所述接合工艺包括在所述管芯堆叠件的相邻集成电路管芯之间形成多个连接器接点。
6.根据权利要求1所述的方法，其中，所述挡块结构是环形结构。
7.根据权利要求6所述的方法，其中，所述管芯堆叠件和所述第一密封剂设置在所述挡块结构的开口中。
8.一种用于形成封装件的方法，包括：
在晶圆上放置第一集成电路管芯，所述晶圆包括位于所述晶圆的第一侧上的第一连接器，所述第一集成电路管芯包括位于所述第一集成电路管芯的第一侧上的第二连接器和位于所述第一集成电路管芯的第二侧上的第三连接器，所述第一集成电路管芯的第一侧与所述第一集成电路管芯的第二侧相对，所述第一连接器与所述第二连接器接触；
将第二集成电路管芯放置在所述第一集成电路管芯上，所述第二集成电路管芯包括位于所述第二集成电路管芯的第一侧上的第四连接器和位于所述第二集成电路管芯的第二侧上的第五连接器，所述第二集成电路管芯的第二侧与所述第二集成电路管芯的第一侧相对，所述第三连接器与所述第四连接器接触；
在所述第一集成电路管芯和所述第二集成电路管芯上实施接合工艺，所述接合工艺将所述第一连接器和所述第二连接器接合以形成第一连接器接点，所述接合工艺将所述第三连接器和所述第四连接器接合以形成第二连接器接点；
所述晶圆上方形成挡块结构，所述挡块结构环绕所述第一集成电路管芯和所述第二集成电路管芯；
在所述晶圆上方以及在所述第一连接器接点和所述第二连接器接点周围形成第一密封剂；以及
在所述晶圆上方形成第二密封剂，所述第二密封剂围绕所述第一集成电路管芯、所述第二集成电路管芯、所述第一密封剂和所述挡块结构。
9.根据权利要求8所述的方法，其中，实施所述接合工艺包括在所述第一连接器、所述第二连接器、所述第三连接器和所述第四连接器上实施焊料回流工艺。
10.一种封装件，包括：
衬底；
挡块结构，位于所述衬底上方，所述挡块结构是环形结构；
管芯堆叠件，位于所述衬底上方并且位于所述挡块结构的开口内，所述管芯堆叠件包括多个集成电路管芯和所述多个集成电路管芯中的相邻集成电路管芯之间的连接器接点；
第一密封剂，沿着所述多个集成电路管芯的侧壁延伸，所述第一密封剂围绕所述连接器接点；以及
第二密封剂，围绕所述管芯堆叠件、所述第一密封剂、和所述挡块结构。
CN201910386985.9A 2018-10-31 2019-05-10 集成电路封装件及其形成方法 Pending CN111128975A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310391095.3A CN116344521A (zh) 2018-10-31 2019-05-10 集成电路封装件及其形成方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/176,008 2018-10-31
US16/176,008 US10529637B1 (en) 2018-10-31 2018-10-31 Integrated circuit package and method of forming same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN202310391095.3A Division CN116344521A (zh) 2018-10-31 2019-05-10 集成电路封装件及其形成方法

Publications (1)

Publication Number Publication Date
CN111128975A true CN111128975A (zh) 2020-05-08

Family

ID=69058679

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201910386985.9A Pending CN111128975A (zh) 2018-10-31 2019-05-10 集成电路封装件及其形成方法
CN202310391095.3A Pending CN116344521A (zh) 2018-10-31 2019-05-10 集成电路封装件及其形成方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN202310391095.3A Pending CN116344521A (zh) 2018-10-31 2019-05-10 集成电路封装件及其形成方法

Country Status (5)

Country Link
US (4) US10529637B1 (zh)
KR (3) KR20200050319A (zh)
CN (2) CN111128975A (zh)
DE (1) DE102018128200B4 (zh)
TW (1) TWI697090B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102583127B1 (ko) * 2018-10-30 2023-09-26 삼성전자주식회사 다이스택 구조물과 이를 구비하는 반도체 패키지
US11101240B2 (en) 2019-06-28 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation bonding film for semiconductor packages and methods of forming the same
KR20210059866A (ko) * 2019-11-15 2021-05-26 삼성전자주식회사 언더 필 물질 층을 포함하는 반도체 패키지 및 그 형성방법
TWI759698B (zh) * 2020-03-04 2022-04-01 矽品精密工業股份有限公司 電子封裝件及其承載結構
KR20210148743A (ko) 2020-06-01 2021-12-08 삼성전자주식회사 반도체 패키지
US20220093559A1 (en) * 2020-09-22 2022-03-24 Western Digital Technologies, Inc. Reducing keep-out-zone area for a semiconductor device
US11742302B2 (en) * 2020-10-23 2023-08-29 Wolfspeed, Inc. Electronic device packages with internal moisture barriers
CN112420615B (zh) * 2020-12-04 2022-02-08 南京大学 一种半导体结构制备方法及半导体器件
CN115602638A (zh) * 2021-07-09 2023-01-13 群创光电股份有限公司（Tw） 电子装置及其制造方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101899195A (zh) * 2009-06-01 2010-12-01 信越化学工业株式会社 坝料组合物及多层半导体装置的制造方法
KR20110000138A (ko) * 2009-06-26 2011-01-03 주식회사 하이닉스반도체 반도체 패키지 및 그 제조방법
CN102054795A (zh) * 2009-10-28 2011-05-11 三星电机株式会社 倒装芯片封装及其制造方法
CN102237281A (zh) * 2010-04-27 2011-11-09 新科金朋有限公司 半导体器件及其制造方法
CN102683330A (zh) * 2011-03-11 2012-09-19 株式会社东芝 半导体装置以及半导体装置的制造方法
CN103426849A (zh) * 2012-05-18 2013-12-04 台湾积体电路制造股份有限公司 三维芯片堆叠件及其形成方法
CN103779283A (zh) * 2012-10-19 2014-05-07 台湾积体电路制造股份有限公司 封装器件、封装器件的制造方法以及封装方法
TW201519404A (zh) * 2013-11-14 2015-05-16 Taiwan Semiconductor Mfg Co Ltd 三維積體電路結構及其製造方法
CN108074828A (zh) * 2016-11-14 2018-05-25 台湾积体电路制造股份有限公司 封装结构及其形成方法
CN108695263A (zh) * 2017-04-03 2018-10-23 爱思开海力士有限公司 半导体封装及其制造方法

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3706840A (en) * 1971-05-10 1972-12-19 Intersil Inc Semiconductor device packaging
JP2007194436A (ja) * 2006-01-19 2007-08-02 Elpida Memory Inc 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法
US7495321B2 (en) * 2006-07-24 2009-02-24 Stats Chippac, Ltd. Leaded stacked packages having elevated die paddle
US7683468B2 (en) 2006-12-21 2010-03-23 Tessera, Inc. Enabling uniformity of stacking process through bumpers
JP4438006B2 (ja) * 2007-03-30 2010-03-24 Ｏｋｉセミコンダクタ株式会社 半導体装置及び半導体装置の製造方法
JP5579402B2 (ja) * 2009-04-13 2014-08-27 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法並びに電子装置
JP2011071381A (ja) * 2009-09-28 2011-04-07 Toshiba Corp 積層型半導体装置およびその製造方法
JP5570799B2 (ja) * 2009-12-17 2014-08-13 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
US8169065B2 (en) 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
US8932910B2 (en) * 2010-05-20 2015-01-13 Ev Group E. Thallner Gmbh Method for producing chip stacks, and a carrier for carrying out the method
JP5638623B2 (ja) * 2010-11-25 2014-12-10 三菱電機株式会社 半導体装置および半導体装置の製造方法
KR101719636B1 (ko) * 2011-01-28 2017-04-05 삼성전자 주식회사 반도체 장치 및 그 제조 방법
JP2013016629A (ja) * 2011-07-04 2013-01-24 Mitsubishi Electric Corp 半導体モジュール
WO2013136382A1 (ja) * 2012-03-14 2013-09-19 パナソニック株式会社 半導体装置
KR101970667B1 (ko) * 2012-07-31 2019-04-19 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US9691746B2 (en) * 2014-07-14 2017-06-27 Micron Technology, Inc. Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
US9443744B2 (en) * 2014-07-14 2016-09-13 Micron Technology, Inc. Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods
WO2016039593A1 (ko) * 2014-09-12 2016-03-17 주식회사 세미콘라이트 반도체 발광소자의 제조 방법
US9397078B1 (en) * 2015-03-02 2016-07-19 Micron Technology, Inc. Semiconductor device assembly with underfill containment cavity
US11222868B2 (en) * 2016-07-06 2022-01-11 Micron Technology, Inc. Thermal transfer structures for semiconductor die assemblies
US10373888B2 (en) * 2016-12-30 2019-08-06 Intel Corporation Electronic package assembly with compact die placement
KR20180094667A (ko) 2017-02-16 2018-08-24 에스케이하이닉스 주식회사 제한된 언더필 필릿을 가지는 적층 패키지 및 제조 방법
US10784220B2 (en) 2017-03-30 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Plurality of semiconductor devices encapsulated by a molding material attached to a redistribution layer
US10879194B2 (en) * 2017-05-25 2020-12-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device package and method of manufacturing the same
US10157888B1 (en) * 2017-06-20 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out packages and methods of forming the same
US10170341B1 (en) * 2017-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Release film as isolation film in package
US10504824B1 (en) * 2018-09-21 2019-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US20200118991A1 (en) * 2018-10-15 2020-04-16 Intel Corporation Pre-patterned fine-pitch bond pad interposer

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101899195A (zh) * 2009-06-01 2010-12-01 信越化学工业株式会社 坝料组合物及多层半导体装置的制造方法
KR20110000138A (ko) * 2009-06-26 2011-01-03 주식회사 하이닉스반도체 반도체 패키지 및 그 제조방법
CN102054795A (zh) * 2009-10-28 2011-05-11 三星电机株式会社 倒装芯片封装及其制造方法
CN102237281A (zh) * 2010-04-27 2011-11-09 新科金朋有限公司 半导体器件及其制造方法
CN102683330A (zh) * 2011-03-11 2012-09-19 株式会社东芝 半导体装置以及半导体装置的制造方法
CN103426849A (zh) * 2012-05-18 2013-12-04 台湾积体电路制造股份有限公司 三维芯片堆叠件及其形成方法
CN103779283A (zh) * 2012-10-19 2014-05-07 台湾积体电路制造股份有限公司 封装器件、封装器件的制造方法以及封装方法
TW201519404A (zh) * 2013-11-14 2015-05-16 Taiwan Semiconductor Mfg Co Ltd 三維積體電路結構及其製造方法
CN108074828A (zh) * 2016-11-14 2018-05-25 台湾积体电路制造股份有限公司 封装结构及其形成方法
CN108695263A (zh) * 2017-04-03 2018-10-23 爱思开海力士有限公司 半导体封装及其制造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
樊会灵等: "《电子产品工艺》", 30 June 2010, 机械工业出版社 *
高宏伟等: "《电子制造装备技术》", 30 September 2015, 西安电子科技大学出版社 *

Also Published As

Publication number Publication date
KR20200050319A (ko) 2020-05-11
CN116344521A (zh) 2023-06-27
US11810831B2 (en) 2023-11-07
DE102018128200B4 (de) 2022-10-13
KR102582862B1 (ko) 2023-09-25
US20220359329A1 (en) 2022-11-10
KR20210086590A (ko) 2021-07-08
US10804178B2 (en) 2020-10-13
TW202018899A (zh) 2020-05-16
US10529637B1 (en) 2020-01-07
TWI697090B (zh) 2020-06-21
US20210028081A1 (en) 2021-01-28
DE102018128200A1 (de) 2020-04-30
KR20220151131A (ko) 2022-11-14
US11424173B2 (en) 2022-08-23
US20200135605A1 (en) 2020-04-30

Similar Documents

Publication Publication Date Title
US20220301889A1 (en) Integrated Circuit Packages and Methods of Forming Same
US10658347B2 (en) Semiconductor packages and methods of forming the same
KR102582862B1 (ko) 집적 회로 패키지 및 이를 형성하는 방법
US9728522B2 (en) Integrated circuit packages and methods of forming same
TWI587466B (zh) 方法與裝置
CN110610907B (zh) 半导体结构和形成半导体结构的方法
CN110112115B (zh) 集成电路封装件及其形成方法
US11443993B2 (en) Chip package structure with cavity in interposer
CN114695272A (zh) 集成电路封装件的形成方法
US11855006B2 (en) Memory device, package structure and fabricating method thereof
US11810830B2 (en) Chip package structure with cavity in interposer
CN115312399A (zh) 半导体装置封装及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20200508