TW202018899A - 封裝體及其形成方法 - Google Patents

封裝體及其形成方法 Download PDF

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TW202018899A
TW202018899A TW108102516A TW108102516A TW202018899A TW 202018899 A TW202018899 A TW 202018899A TW 108102516 A TW108102516 A TW 108102516A TW 108102516 A TW108102516 A TW 108102516A TW 202018899 A TW202018899 A TW 202018899A
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integrated circuit
die
wafer
circuit die
dam structure
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TW108102516A
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TWI697090B (zh
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余振華
吳志偉
盧思維
施應慶
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台灣積體電路製造股份有限公司
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Abstract

一種積體電路封裝體及其形成方法。一種方法包括：將多個積體電路晶粒堆疊於晶圓上以形成晶粒堆疊。對所述晶粒堆疊執行接合製程。所述接合製程將所述晶粒堆疊的多個相鄰的積體電路晶粒機械性及電性連接至彼此。在所述晶圓之上形成擋壩結構。所述擋壩結構環繞所述晶粒堆疊。在所述晶圓之上且在所述晶粒堆疊與所述擋壩結構之間形成第一包封體。所述第一包封體填充所述晶粒堆疊的所述多個相鄰的積體電路晶粒之間的多個間隙。在所述晶圓之上形成第二包封體。所述第二包封體環繞所述晶粒堆疊、所述第一包封體及所述擋壩結構。

Description

封裝體及其形成方法
半導體裝置用於例如個人電腦、手機、數位照相機以及其他電子設備等各種電子應用中。半導體裝置通常是藉由以下方式來製作：在半導體基底之上依序沈積絕緣材料層或介電材料層、導電材料層以及半導電材料層，並利用微影對各種材料層進行圖案化以在半導體基底上形成電路組件及元件。在單一半導體晶圓上，通常製造數十或數百個積體電路（integrated circuit）。藉由沿著切割道切割積體電路而將個別的晶粒單體化。接著將個別的晶粒單獨地封裝於多晶片（multi-chip）模組中或於其他類型的封裝體中。
由於各種電子組件（例如，電晶體、二極體、電阻器、電容器等）的積體密度的不斷提高，半導體產業經歷了快速成長。大部分而言，積體密度的增進是來自於最小特徵尺寸（feature size）的不斷減小（例如，半導體製程節點朝向小於20奈米的節點縮小），此容許更多組件能夠被整合至給定區域內。隨著近來對小型化、較高速度及較大頻寬以及較少的功耗及延遲的需求的增長，增加了對半導體晶粒的更小及更具創造性的封裝技術的需求。
隨著半導體技術進一步發展，堆疊式半導體裝置（例如，三維積體電路（three dimensional integrated circuit，3DIC）已成為一種有效的替代方案，以進一步減小半導體裝置的物理大小。在堆疊式半導體裝置中，主動電路（例如邏輯電路、記憶體電路、處理器電路等）被製作在不同的半導體晶圓上。二或更多個半導體晶圓可安裝或堆疊在彼此的頂部上，以進一步減小半導體裝置的形狀因數（form factor）。疊層封裝體（package-on-package，POP）裝置為三維積體電路的一種類型，其中晶粒被封裝，接著與另外的一或多個封裝晶粒一起被封裝。晶片封裝體（chip-on-package，COP）裝置為三維積體電路的另一種類型，其中晶粒被封裝，接著與另外的一或多個晶粒一起被封裝。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，在以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本揭露可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「位於…之下（beneath）」、「位於…下方（below）」、「下部的（lower）」、「位於…上方（above）」、「上部的（upper）」等空間相對性用語來闡述圖中所示一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可被另外定向（旋轉90度或處於其他定向）且本文中所用的空間相對性描述語可同樣相應地進行解釋。
將關於實施例在具體上下文中闡述實施例，即積體電路封裝體及其形成方法。然而，其他實施例亦可應用於其他電性連接的組件，包括但不限於疊層封裝體總成、晶粒至晶粒（die-to-die）總成、晶圓至晶圓（wafer-to-wafer）總成、晶粒至基底（die-to-substrate）總成、在組裝封裝體時、在處理基底、中介層或類似者時、或安裝輸入組件、板、晶粒或其他組件或者用於任何類型的積體電路或電性組件的連接封裝或安裝組合。本文所述的各種實施例容許藉由以下方式來形成積體電路封裝體：將積體電路晶粒排列成晶粒堆疊並使用應用於晶粒堆疊的單一接合製程（single bonding process）將晶粒堆疊的多個相鄰的積體電路晶粒彼此接合，而無需在接合製程期間對晶粒堆疊施加額外的外力。本文所述的各種實施例更容許在多個相鄰的積體電路晶粒之間的多個間隙中形成包封體材料而不在包封體材料中形成空隙，且容許提高包封體材料的間隙填充效能。本文所述的各種實施例更容許在積體電路封裝體的形成期間減少晶圓翹曲。
圖1至圖4、圖5A、圖5B以及圖6至圖11示出根據一些實施例的在積體電路（integrated circuit，IC）封裝體（像是例如圖10所示積體電路封裝體1001）的製作期間的各種處理步驟的俯視圖及剖視圖。參照圖1，所述製程始於將晶圓105接合至載體101以開始形成晶圓級晶粒結構100。在一些實施例中，使用黏合層103將晶圓105貼合至載體101。在一些實施例中，載體101可包含矽、石英、陶瓷、玻璃、其組合或類似者，且為對晶圓105執行的後續操作提供機械支撐。在一些實施例中，黏合層103可包含光熱轉換（light to heat conversion，LTHC）材料、紫外線（ultraviolet，UV）黏合劑、聚合物層、其組合或類似者，且可使用旋轉塗佈（spin-on coating）製程、印刷製程、疊層（lamination）製程、其組合或類似者來形成。在其中黏合層103是由LTHC材料形成的一些實施例中，黏合層103當暴露於光時會部分地或全部喪失其黏合強度，且在完成晶圓級晶粒結構100的形成後，可易於自晶圓級晶粒結構100的背側移除載體101。
在一些實施例中，晶圓105包括基底（圖中未單獨示出）、位於基底上的一或多個主動裝置及/或被動裝置（圖中未單獨示出）以及位於所述一或多個主動裝置及/或被動裝置以及基底之上的內連線結構（圖中未單獨示出）。在一些實施例中，基底可由矽形成，但基底亦可由其他III族、IV族及/或V族元素（例如，矽、鍺、鎵、砷及其組合）形成。基底亦可為絕緣體上矽（silicon-on-insulator，SOI）形式。SOI基底可包括在絕緣體層（例如，埋入式（buried oxide）氧化物及/或類似物）之上形成的半導體材料（例如，矽、鍺及/或類似材料）層，所述絕緣體層形成於矽基底上。另外，可使用的其他基底包括多層式基底（multi-layered substrate）、梯度基底（gradient substrate）、混合定向基底（hybrid orientation substrate）、其任何組合及/或類似基底。
在一些實施例中，晶圓105更包括形成於基底上的一或多個主動裝置及/或被動裝置（圖中未單獨示出）。所述一或多個主動裝置及/或被動裝置可包括各種n型金屬氧化物半導體（n-type metal-oxide semiconductor，NMOS）裝置及/或p型金屬氧化物半導體（p-type metal-oxide semiconductor，PMOS）裝置（例如，電晶體、電容器、電阻器、二極體、光二極體（photo-diode）、熔線（fuse）及/或類似裝置）。
在一些實施例中，晶圓105更包括形成於所述基底以及所述一或多個主動裝置及/或被動裝置之上的內連線結構（圖中未單獨示出）。內連線結構可包括多個介電層（例如層間介電（inter-layer dielectric，ILD）及/或金屬間介電（inter-metal dielectric）層（IMD））以及位於介電層內的內連線（例如導電線及通孔）。介電層可藉由此項技術中已知的任何合適的方法（例如旋轉塗佈方法、化學氣相沈積（chemical vapor deposition，CVD）、電漿增強型CVD（plasma enhanced CVD，PECVD）、其組合或類似者）而例如由低介電常數（low-K）介電材料（例如磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼磷矽酸鹽玻璃（borophosphosilicate glass，BPSG）、氟矽酸鹽玻璃（fluorinated silicate glass，FSG）、SiOxCy、旋轉塗佈玻璃（Spin-On-Glass）、旋轉塗佈聚合物（Spin-On-Polymers）、矽碳材料、其化合物、其複合物、其組合或類似者）來形成。在一些實施例中，可使用例如鑲嵌製程、雙鑲嵌製程、其組合或類似者在介電層中形成內連線。在一些實施例中，內連線可包含銅、銅合金、銀、金、鎢、鉭、鋁、其組合或類似者。在一些實施例中，內連線可提供在基底上形成的所述一或多個主動裝置及/或被動裝置之間的電性連接。
在一些實施例中，晶圓105更包括多個穿孔（through via，TV）111，穿孔111自晶圓105的第一表面105A朝向晶圓105的第二表面105B延伸。在一些實施例中，穿孔111可藉由在晶圓105中形成開口並使用合適的導電材料填充所述開口來形成。在一些實施例中，所述開口可利用合適的光微影方法及蝕刻方法來形成。在一些實施例中，開口可利用物理氣相沈積（physical vapor deposition，PVD）、原子層沈積（atomic layer deposition，ALD）、電化學鍍覆、無電鍍覆或其組合或類似者而使用銅、銅合金、銀、金、鎢、鉭、鋁、其組合或類似者來填充。在一些實施例中，在使用合適的導電材料填充開口之前，可在所述開口中形成襯墊層（liner layer）及/或黏合/障壁層。在一些實施例中，可對穿孔111的導電材料執行平坦化製程以移除導電材料的多餘部分。平坦化製程可包括化學機械研磨（chemical mechanical polishing，CMP）製程、研磨製程（grinding process）、蝕刻製程、其組合或類似者。
在一些實施例中，晶圓105更包括形成於晶圓105的第一表面105A上的多個連接件107以及形成於晶圓105的第二表面105B上的多個連接件109。在一些實施例中，多個連接件107中的每一者包括導電柱凸塊107A以及位於導電柱凸塊107A之上的焊料元件107B。在一些實施例中，導電柱凸塊107A可包含導電材料，例如銅、鎢、鋁、銀、金、其組合或類似者。在一些實施例中，焊料元件107B可包括鉛系焊料（例如PbSn組成物）、包含InSb、錫、銀及銅（tin、silver、copper，SAC）組成物的無鉛焊料以及具有共同的熔點且在電性應用中形成導電焊料連接的其他共晶材料。對於無鉛焊料而言，可使用由各種組成物形成的SAC焊料，例如SAC 105（Sn 98.5%、Ag 1.0%、Cu 0.5%）、SAC 305及SAC 405作為實例。無鉛焊料亦包括不使用銀（Ag）的SnCu化合物以及不使用銅（Cu）的SnAg化合物。
在一些實施例中，一種形成導電柱凸塊107A的方法可包括：在第一表面105A之上形成導電晶種層；在導電晶種層之上形成犧牲材料（例如光阻材料）；對犧牲材料進行圖案化以在犧牲層中形成開口；使用電化學鍍覆製程、無電鍍覆製程、ALD、PVD、其組合或類似製程在開口中沈積導電材料；移除犧牲層；以及移除導電晶種層的被暴露的部分。在一些實施例中，在移除犧牲層之前，使用蒸鍍、電化學鍍覆製程、無電鍍覆製程、印刷、焊料轉移、其組合或類似製程在開口中的導電柱凸塊107A的導電材料之上形成焊料材料以形成焊料元件107B。在一些實施例中，可對焊料元件107B執行回流製程以將焊料材料構形成期望的凸塊形狀。在其他實施例中，連接件107可為焊球、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、球柵陣列（ball grid array，BGA）球、微凸塊、無電鍍鎳鈀浸金術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）所形成的凸塊、其組合或類似者。
在一些實施例中，連接件109可相似於連接件107，且可使用與連接件107相似的材料及方法形成，並且本文中不再重複說明。在一些實施例中，多個連接件109中的每一者包括導電柱凸塊109A以及位於導電柱凸塊109A之上的焊料元件109B。在一些實施例中，導電柱凸塊109A可使用與導電柱凸塊107A相似的材料及方法形成，且本文中不再重複說明。在一些實施例中，焊料元件109B可使用與焊料元件107B相似的材料及方法形成，且本文中不再重複說明。在一些實施例中，在焊料元件109B形成之後不執行回流製程。
在某一實施例中，晶圓105可為中介物晶圓（interposer wafer）。在此類實施例中，晶圓105可不包括位於基底上的所述一或多個主動裝置及/或被動裝置。在其他實施例中，晶圓105可為積體電路晶圓。在此類實施例中，晶圓105包括位於基底上的所述一或多個主動裝置及/或被動裝置。
參照圖2，將積體電路晶粒201A放置於晶圓105上以開始在晶圓105上形成晶粒堆疊（例如圖4所示晶粒堆疊401）。積體電路晶粒201A可包括邏輯晶粒、記憶體晶粒、中央處理單元（central processing unit，CPU）、圖形處理單元（graphic processing unit，GPU）、賽靈思處理單元（Xilinx processing unit，XPU）、微機電系統（micro-electro-mechanical system，MEMS）晶粒、系統晶片（system-on-chip，SoC）晶粒或類似者。在某一實施例中，多個積體電路晶粒201A中的每一者可包括基底（圖中未單獨示出）、位於基底上的一或多個主動裝置及/或被動裝置（圖中未單獨示出）以及位於基底以及所述一或多個主動裝置及/或被動裝置之上的內連線結構（圖中未單獨示出）。在一些實施例中，積體電路晶粒201A的基底可使用與以上參照圖1闡述的晶圓105的基底相似的材料及方法形成，且本文中不再重複說明。在一些實施例中，積體電路晶粒201A的所述一或多個主動裝置及/或被動裝置可使用與以上參照圖1闡述的晶圓105的所述一或多個主動裝置及/或被動裝置相似的材料及方法形成，且本文中不再重複說明。在一些實施例中，積體電路晶粒201A的內連線結構可使用與以上參照圖1闡述的晶圓105的內連線結構相似的材料及方法形成，且本文中不再重複說明。在一些實施例中，積體電路晶粒201A可具有介於約20微米與約50微米之間的厚度。
在一些實施例中，多個積體電路晶粒201A中的每一者更包括：多個穿孔（TV）203A，自積體電路晶粒201A的下表面朝向積體電路晶粒201A的上表面延伸；多個連接件205A，位於積體電路晶粒201A的下表面上；以及多個連接件207A，位於積體電路晶粒201A的上表面上。在一些實施例中，穿孔203A可使用與以上參照圖1闡述的穿孔111相似的材料及方法形成，且本文中不再重複說明。在一些實施例中，連接件205A及連接件207A可相似於以上參照圖1闡述的連接件107並可使用與以上參照圖1闡述的連接件107相似的材料及方法形成，且本文中不再重複說明。在一些實施例中，多個連接件205A中的每一者可包括導電柱凸塊205A1 以及位於導電柱凸塊205A1 之上的焊料元件205A2 。在一些實施例中，導電柱凸塊205A1 可使用與以上參照圖1闡述的導電柱凸塊107A相似的材料及方法形成，且在本文中不再重複說明。在一些實施例中，焊料元件205A2 可使用與以上參照圖1闡述的焊料元件107B相似的材料及方法形成，且本文中不再重複說明。
在一些實施例中，多個連接件207A中的每一者可包括導電柱凸塊207A1 以及位於導電柱凸塊207A1 之上的焊料元件207A2 。在一些實施例中，導電柱凸塊207A1 可使用與以上參照圖1闡述的導電柱凸塊107A相似的材料及方法形成，且本文中不再重複說明。在一些實施例中，焊料元件207A2 可使用與以上參照圖1闡述的焊料元件107B相似的材料及方法形成，且本文中不再重複說明。在一些實施例中，在焊料元件205A2 及焊料元件207A2 形成之後不執行回流製程。
進一步參照圖2，在一些實施例中，可使用拾取及放置（pick-and-place）設備將積體電路晶粒201A放置於晶圓105上。在其他實施例中，可人工地或使用任何其他合適的方法將積體電路晶粒201A放置於晶圓105上。在一些實施例中，在將積體電路晶粒201A放置於晶圓105上之前將積體電路晶粒201A浸於助焊劑（flux）材料209中。在一些實施例中，助焊劑材料209將積體電路晶粒201A預接合（pre-bond）至晶圓105。在一些實施例中，可將積體電路晶粒201A與晶圓105的連接件109對準，以將積體電路晶粒201A的連接件205A放置於晶圓105的連接件109上。在一些實施例中，在將積體電路晶粒201A放置於晶圓105上的期間或在將積體電路晶粒201A放置於晶圓105上之後，但在將額外的積體電路晶粒放置於積體電路晶粒201A上之前，不對積體電路晶粒201A施加額外的外力（例如是與積體電路晶粒201A的重量所引起的重力不同的力）。在一些實施例中，在將積體電路晶粒201A放置於晶圓105上的期間或在將積體電路晶粒201A放置於晶圓105上之後，但在將額外的積體電路晶粒放置於積體電路晶粒201A上之前，不執行額外的製程步驟來將積體電路晶粒201A的連接件205A預接合或接合至晶圓105的連接件109。
參照圖3，將積體電路晶粒201B至201G以及積體電路晶粒301放置於各別的積體電路晶粒201A之上以在晶圓105上形成預接合的晶粒堆疊305。在一些實施例中，積體電路晶粒201X（其中X=B、C、...、G）可相似於以上參照圖2闡述的積體電路晶粒201A，且本文中不再重複說明。在一些實施例中，多個積體電路晶粒201X（其中X=B、C、...、G）中的每一者更包括：多個穿孔（TV）203X（其中X=B、C、...、G），自積體電路晶粒201X（其中X=B、C、...、G）的下表面朝向積體電路晶粒201X（其中X=B、C、...、G）的上表面延伸；多個連接件205X（其中X=B、C、...、G），位於積體電路晶粒201X（其中X=B、C、...、G）的下表面上；以及多個連接件207X（其中X=B、C、...、G），位於積體電路晶粒201X（其中X=B、C、...、G）的上表面上。多個連接件205X（其中X=B、C、...、G）中的每一者包括導電柱凸塊205X1 （其中X=B、C、...、G）以及位於導電柱凸塊205X1 （其中X=B、C、...、G）之上的焊料元件205X2 （其中X=B、C、...、G）。在一些實施例中，導電柱凸塊205X1 （其中X=B、C、...、G）可使用與以上參照圖1闡述的導電柱凸塊107A相似的材料及方法形成，且本文中不再重複說明。在一些實施例中，焊料元件205X2 （其中X=B、C、...、G）可使用與以上參照圖1闡述的焊料元件107B相似的材料及方法形成，且本文中不再重複說明。多個連接件207X（其中X=B、C、...、G）中的每一者包括導電柱凸塊207X1 （其中X=B、C、...、G）以及位於導電柱凸塊207X1 （其中X=B、C、...、G）之上的焊料元件207X2 （其中X=B、C、...、G）。在一些實施例中，導電柱凸塊207X1 （其中X=B、C、...、G）可使用與以上參照圖1闡述的導電柱凸塊107A相似的材料及方法形成，且本文中不再重複說明。在一些實施例中，焊料元件207X2 （其中X=B、C、...、G）可使用與以上參照圖1闡述的焊料元件107B相似的材料及方法形成，且本文中不再重複說明。在一些實施例中，在焊料元件205X2 （其中X=B、C、...、G）及焊料元件207X2 （其中X=B、C、...、G）形成之後不執行回流製程。在一些實施例中，積體電路晶粒201X（其中X=A、B、C、...、G）可具有相同的厚度。在其他實施例中，積體電路晶粒201X（其中X=A、B、C、...、G）可具有不同的厚度。
在一些實施例中，積體電路晶粒301可相似於積體電路晶粒201X（其中X=A、B、C、...、G），且本文中不再重複說明。在一些實施例中，積體電路晶粒301的厚度可大於多個積體電路晶粒201X（其中X=A、B、C、...、G）中的每一者的厚度。在一些實施例中，多個積體電路晶粒301中的每一者更包括位於積體電路晶粒301的下表面上的多個連接件303。多個連接件303中的每一者包括導電柱凸塊3031 以及位於導電柱凸塊3031 之上的焊料元件3032 。在一些實施例中，導電柱凸塊3031 可使用與以上參照圖1闡述的導電柱凸塊107A相似的材料及方法形成，且本文中不再重複說明。在一些實施例中，焊料元件3032 可使用與以上參照圖1闡述的焊料元件107B相似的材料及方法形成，且本文中不再重複說明。在一些實施例中，在焊料元件3032 形成之後不對預接合的晶粒堆疊305執行回流製程。
進一步參照圖3，將積體電路晶粒201X（其中X=B、C、...、G）及積體電路晶粒301堆疊於各別的積體電路晶粒201A之上所使用的方法相似於上述參照圖2所闡述的將積體電路晶粒201A放置於晶圓105上的方法，且本文中不再重複說明。在一些實施例中，在將積體電路晶粒201X（其中X=B、C、...、G）及積體電路晶粒301放置於前面的積體電路晶粒之上以形成預接合的晶粒堆疊305之前，將積體電路晶粒201X（其中X=B、C、...、G）及301浸於助焊劑材料209中。在一些實施例中，助焊劑材料209對預接合的晶粒堆疊305的多個相鄰的積體電路晶粒（例如，積體電路晶粒201A及201B、積體電路晶粒201B及201C、積體電路晶粒201C及201D、積體電路晶粒201D及201E、積體電路晶粒201E及201F、積體電路晶粒201F及201G以及積體電路晶粒201G及301）進行預接合以形成預接合的晶粒堆疊305。在某一實施例中，在預接合的晶粒堆疊305形成期間，不對積體電路晶粒201X（其中X=B、C、...、G）及積體電路晶粒301施加額外的外力（例如與積體電路晶粒的重量所引起的重力不同的力）。在一些實施例中，在預接合的晶粒堆疊305形成期間，不執行額外的製程步驟來將連接件207A預接合或接合至連接件205B、將連接件207B預接合或接合至連接件205C、將連接件207C預接合或接合至連接件205D、將連接件207D預接合或接合至連接件205E、將連接件207E預接合或接合至連接件205F、將連接件207F預接合或接合至連接件205G以及將連接件207G預接合或接合至連接件303。
參照圖4，對預接合的晶粒堆疊305（參照圖3）執行單一接合製程以形成接合的晶粒堆疊401。單一接合製程將多個連接件109（參見圖3）中的每一者接合至多個連接件205A（參見圖3）中的各別一者以形成多個連接件接頭403A、將多個連接件207A（參見圖3）中的每一者接合至多個連接件205B（參見圖3）中的各別一者以形成多個連接件接頭403B、將多個連接件207B（參見圖3）中的每一者接合至多個連接件205C（參見圖3）中的各別一者以形成多個連接件接頭403C、將多個連接件207C（參見圖3）中的每一者接合至多個連接件205D（參見圖3）中的各別一者以形成多個連接件接頭403D、將多個連接件207D（參見圖3）中的每一者接合至多個連接件205E（參見圖3）中的各別一者以形成多個連接件接頭403E、將多個連接件207E（參見圖3）中的每一者接合至多個連接件205F（參見圖3）中的各別一者以形成多個連接件接頭403F、將多個連接件207F（參見圖3）中的每一者接合至多個連接件205G（參見圖3）中的各別一者以形成多個連接件接頭403G、將多個連接件207G（參見圖3）中的每一者接合至多個連接件303（參見圖3）中的各別一者以形成多個連接件接頭403H。對於多個接合的晶粒堆疊401中的每一者，單一接合製程將積體電路晶粒201A至201G及301機械性及電性耦合至彼此。
在某一實施例中，單一接合製程是焊料回流製程。焊料回流製程使連接件109的焊料元件109B（參見圖3）及連接件205A的焊料元件205A2 （參見圖3）回流成各別連接件接頭403A的焊料接頭401A中、使連接件207A的焊料元件207A2 （參見圖3）及連接件205B的焊料元件205B2 （參見圖3）回流成各別連接件接頭403B的焊料接頭401B中、使連接件207B的焊料元件207B2 （參見圖3）及連接件205C的焊料元件205C2 （參見圖3）回流成各別連接件接頭403C的焊料接頭401C中、使連接件207C的焊料元件207C2 （參見圖3）及連接件205D的焊料元件205D2 （參見圖3）回流成各別連接件接頭403D的焊料接頭401D中、使連接件207D的焊料元件207D2 （參見圖3）及連接件205E的焊料元件205E2 （參見圖3）回流成各別連接件接頭403E的焊料接頭401E中、使連接件207E的焊料元件207E2 （參見圖3）及連接件205F的焊料元件205F2 （參見圖3）回流成各別連接件接頭403F的焊料接頭401F中、使連接件207F的焊料元件207F2 （參見圖3）及連接件205G的焊料元件205G2 （參見圖3）回流成各別連接件接頭403G的焊料接頭401G中、以及使連接件207G的焊料元件207G2 （參見圖3）及連接件303的焊料元件3032 （參見圖3）回流成各別連接件接頭403H的焊料接頭401H中。在某一實施例中，在執行單一接合製程期間，不對預接合的晶粒堆疊305（參見圖3）施加額外的外力（例如與積體電路晶粒201A至201G及301的重量所引起的重力不同的力）。在其他實施例中，單一接合製程是熱壓縮接合製程或類似者。在一些實施例中，在形成連接件接頭403A至403H之後，使用合適的移除製程移除助焊劑材料209（參見圖3）。
圖5A及圖5B示出在多個接合的晶粒堆疊401周圍形成多個擋壩（dam）結構501。圖5A示出俯視圖。圖5B示出沿圖5A所示的線AA的剖視圖。圖5A及圖5B示出貼合至晶圓105且藉由晶圓105的切割道503彼此分開的多個接合的晶粒堆疊401。在一些實施例中，多個擋壩結構501為環繞各別的接合的晶粒堆疊401的多個環形結構。在一些實施例中，擋壩結構501處於晶圓105中被切割道503分開的區域內。在一些實施例中，擋壩結構501不與切割道503交疊。在一些實施例中，多個擋壩結構501中的每一者可包含金屬材料、聚合物材料、介電材料、絕緣材料、其組合或類似者。在一些實施例中，在晶圓105的被暴露的部分之上形成擋壩結構501的材料，且隨後對所述材料進行圖案化以形成擋壩結構501。在一些實施例中，圖案化製程可包括合適的光微影及蝕刻製程。在其他實施例中，擋壩結構501可使用印刷製程、疊層製程、施配製程（dispensing process）、其組合或類似者形成。在一些實施例中，擋壩結構501在圖5B所示的橫截面中具有高度H1 及寬度W1 。在一些實施例中，擋壩結構501的高度H1 小於接合的晶粒堆疊401的高度H2 。在某一實施例中，高度H1 介於約20微米與約1000微米之間。在某一實施例中，高度H2 介於約50微米與約1000微米之間。在某一實施例中，寬度W1 介於約50微米與約1000微米之間。在某一實施例中，H1 /H2 的比率介於約0.1與約2之間。在某一實施例中，H1 /W1 的比率介於約0.1與約10之間。
在圖5A所示實施例中，擋壩結構501中的每一者的平面圖形狀為矩形環形狀。在一些實施例中，矩形環形狀的外周邊具有介於約5毫米與約50毫米之間的第一寬度W2 以及介於約5毫米與約50毫米之間的第二寬度W3 。在一些實施例中，W2 /W3 的比率介於約0.1與約10之間。在一些實施例中，多個矩形環形狀與多個晶粒堆疊401中的各別一者之間的距離T1 介於約50微米與約2000微米之間。在其他實施例中，如圖6所示，擋壩結構501中的每一者的平面圖形狀可為正方形環形狀601、圓形環形狀603、橢圓形環形狀605或類似者。在一些實施例中，擋壩結構501的平面圖形狀可基於接合的晶粒堆疊401的平面圖形狀來調整。
參照圖7，在接合的晶粒堆疊401周圍形成擋壩結構501之後，在擋壩結構501的開口中以及在晶粒堆疊401周圍形成底部填充膠701。在一些實施例中，底部填充膠701進一步形成於接合的晶粒堆疊401的積體電路晶粒201A至201G及301中的多個相鄰的積體電路晶粒之間的間隙中以及積體電路晶粒201A與晶圓105之間的間隙中。底部填充膠701環繞並保護連接件接頭403A至403H。在一些實施例中，藉由毛細作用對液體底部填充材料進行施配並對所述液體底部填充材料進行固化以形成底部填充膠701。在一些實施例中，底部填充膠701包括環氧系樹脂，其中分散有填料。填料可包括纖維、顆粒、其他合適的元素、其組合或類似者。在一些實施例中，藉由形成擋壩結構501，底部填充膠701的側向範圍可被控制，此會改善底部填充膠701的間隙填充性質。在一些實施例中，底部填充膠701的材料性質可進行進一步更改以改善底部填充膠701的間隙填充性質。在某一實施例中，分散於底部填充膠701的底部填充材料中的填料的尺寸可減小。在某一實施例中，可對底部填充膠701的底部填充材料進行選擇以具有介於約40℃與約200℃之間的玻璃轉變溫度（glass transition temperature，Tg ）。在某一實施例中，可對底部填充膠701的底部填充材料進行選擇以具有介於約5 ppm/℃與約50 ppm/℃之間的熱膨脹係數（coefficient of thermal expansion，CTE）。在某一實施例中，可對底部填充膠701的底部填充材料進行選擇以具有介於約0.1十億帕（GPa）與約20十億帕之間的楊氏模數（Young’s Modulus）。在所示的實施例中，擋壩結構501防止底部填充膠701在晶圓105之上形成連續的層，從而可防止晶圓105因CET的不匹配（mismatch）而翹曲，因此可減少或防止連接件接頭403A至403H的接合失敗。在一些實施例中，底部填充膠701具有傾斜的多個側壁。
參照圖8，在形成底部填充膠701之後，在晶圓105之上且環繞晶粒堆疊401及擋壩結構501形成包封體801。在一些實施例中，包封體801可包含模製化合物，例如環氧樹脂（epoxy）、樹脂、可模製聚合物、其組合或類似者，其中分散有填料。可在模製化合物實質上為液體時，施加所述模製化合物，且接著可藉由化學反應而將所述模製化合物固化。填料可包括絕緣纖維、絕緣顆粒、其他合適的元素、其組合或類似者。在一些實施例中，包封體801可使用與以上參照圖7闡述的底部填充膠701相似的材料及方法形成，且本文中不再重複說明。在一些實施例中，包封體801及底部填充膠701包含相同的材料。在一些實施例中，包封體801及底部填充膠701包含不同的材料。在一些實施例中，分散於包封體801中的填料的尺寸及/或密度大於分散於底部填充膠701中的填料的尺寸及/或密度。在其他實施例中，包封體801可以是作為凝膠或可塑固體的紫外線（UV）固化聚合物或熱固化聚合物，所述凝膠或可塑固體能夠被設置在晶粒堆疊401及擋壩結構501周圍以及晶粒堆疊401與擋壩結構501之間。在另一些實施例中，包封體801可例如包含介電材料，例如氧化物。在一些實施例中，可對包封體801執行平坦化製程以移除包封體801的多餘部分，以使包封體801的最頂部表面與晶粒堆疊401的最頂部表面實質上齊平。在一些實施例中，平坦化製程亦可移除積體電路晶粒301的上部分且使積體電路晶粒301薄化。在一些實施例中，平坦化製程可包括CMP製程、蝕刻製程、研磨、其組合或類似者。
參照圖9，在形成包封體801之後，將載體101自晶圓級晶粒結構100剝離。在一些實施例中，在將載體101自晶圓級晶粒結構100剝離之後，亦移除黏合層103以暴露出連接件107。在一些實施例中，可使用合適的清潔製程移除黏合層103。
參照圖10，在將載體101自晶圓級晶粒結構100剝離之後，沿切割道503（參見圖5A）將晶圓級晶粒結構100單體化以形成個別的積體電路封裝體1001。在一些實施例中，多個積體電路封裝體1001中的每一者包括接合的晶粒堆疊401及對應的擋壩結構501。在一些實施例中，可例如藉由鋸切（sawing）、雷射燒蝕（laser ablation）、蝕刻、其組合或類似製程將晶圓級晶粒結構100單體化成個別的積體電路封裝體1001。
參照圖11，在一些實施例中，使用連接件107將積體電路封裝體1001機械性及電性貼合至工件1101。在一些實施例中，可執行回流製程以將積體電路封裝體1001接合至工件1101。在一些實施例中，工件1101可包括積體電路晶粒、封裝基底、印刷電路板（printed circuit board，PCB）、陶瓷基底或類似者。
圖12是示出根據一些實施例的一種形成積體電路封裝體的方法1200的流程圖。所述方法始於步驟1201，在步驟1201中，將晶圓（像是例如圖1所示的晶圓105）貼合至載體（像是例如圖1所示的載體101），如以上參照圖1所述。在步驟1203中，將多個積體電路晶粒（像是例如圖3所示的積體電路晶粒201A至201G及301）放置於晶圓上以形成晶粒堆疊（像是例如圖3所示的晶粒堆疊305），如以上參照圖2及圖3所述。在步驟1205中，對晶粒堆疊執行單一接合製程，如以上參照圖4所述。在步驟1207中，在晶圓之上在晶粒堆疊周圍形成擋壩結構（像是例如圖5所示的擋壩結構501），如以上參照圖5A及圖5B所述。在步驟1209中，在擋壩結構內以及在晶粒堆疊周圍形成第一包封體（像是例如圖7所示的底部填充膠701），如以上參照圖7所述。在步驟1211中，在晶圓之上且在擋壩結構、晶粒堆疊及第一包封體周圍形成第二包封體（像是例如圖8所示的包封體801），如以上參照圖8所述。在步驟1213中，將載體自所得結構（像是例如圖9所示的晶圓級晶粒結構100）剝離，如以上參照圖9所述。在步驟1215中，將所得結構單體化成個別的積體電路封裝體（像是例如圖10所示的積體電路封裝體），如以上參照圖10所述。
根據實施例，一種形成封裝體的方法，包括：將多個積體電路晶粒堆疊於晶圓上以形成晶粒堆疊；對所述晶粒堆疊執行接合製程，所述接合製程將所述晶粒堆疊的多個相鄰的積體電路晶粒機械性及電性連接至彼此；在所述晶圓之上形成擋壩結構，所述擋壩結構環繞所述晶粒堆疊；在所述晶圓之上且在所述晶粒堆疊與所述擋壩結構之間形成第一包封體，所述第一包封體填充所述晶粒堆疊的所述多個相鄰的積體電路晶粒之間的多個間隙；以及在所述晶圓之上形成第二包封體，所述第二包封體環繞所述晶粒堆疊、所述第一包封體及所述擋壩結構。在實施例中，所述方法更包括：在將所述多個積體電路晶粒堆疊於所述晶圓上之前，將所述晶圓貼合至載體。在實施例中，執行所述接合製程包括執行焊料回流製程。在實施例中，將所述多個積體電路晶粒堆疊於所述晶圓上包括：在將所述多個積體電路晶粒中的每一者放置於所述晶圓上之前，將所述多個積體電路晶粒中的每一者浸於助焊劑材料中。在實施例中，對所述晶粒堆疊執行所述接合製程包括：在所述晶粒堆疊的所述多個相鄰的積體電路晶粒之間形成多個連接件接頭。在實施例中，所述擋壩結構為環形結構。在實施例中，所述晶粒堆疊及所述第一包封體設置於所述擋壩結構的開口中。
根據另一實施例，一種形成封裝體的方法，包括：將第一積體電路晶粒放置於晶圓上，所述晶圓包括位於所述晶圓的第一側上的多個第一連接件，所述第一積體電路晶粒包括位於所述第一積體電路晶粒的第一側上的多個第二連接件及位於所述第一積體電路晶粒的第二側上的多個第三連接件，所述第一積體電路晶粒的所述第一側與所述第一積體電路晶粒的所述第二側相對，所述多個第一連接件接觸所述多個第二連接件；將第二積體電路晶粒放置於所述第一積體電路晶粒上，所述第二積體電路晶粒包括位於所述第二積體電路晶粒的第一側上的多個第四連接件及位於所述第二積體電路晶粒的第二側上的多個第五連接件，所述第二積體電路晶粒的所述第一側與所述第二積體電路晶粒的所述第二側相對，所述多個第三連接件接觸所述多個第四連接件；對所述第一積體電路晶粒及所述第二積體電路晶粒執行接合製程，所述接合製程對所述多個第一連接件與所述多個第二連接件進行接合以形成多個第一連接件接頭，所述接合製程對所述多個第三連接件與所述多個第四連接件進行接合以形成多個第二連接件接頭；在所述晶圓之上形成擋壩結構，所述擋壩結構環繞所述第一積體電路晶粒及所述第二積體電路晶粒；在所述晶圓之上且在所述多個第一連接件接頭與所述多個第二連接件接頭周圍形成第一包封體；以及在所述晶圓之上形成第二包封體，所述第二包封體環繞所述第一積體電路晶粒、所述第二積體電路晶粒、所述第一包封體及所述擋壩結構。在實施例中，執行所述接合製程包括：對所述多個第一連接件、所述多個第二連接件、所述多個第三連接件及所述多個第四連接件執行焊料回流製程。在實施例中，所述接合製程將所述多個第一連接件中的每一者的第一焊料層與所述多個第二連接件中的各別一者的第二焊料層合併以形成第一單一焊料層。在實施例中，所述接合製程將所述多個第三連接件中的每一者的第三焊料層與所述多個第四連接件中的各別一者的第四焊料層合併以形成第二單一焊料層。在實施例中，所述方法更包括：在將所述第一積體電路晶粒放置於所述晶圓上之前，將所述第一積體電路晶粒浸於助焊劑材料中。在實施例中，所述方法更包括：在將所述第二積體電路晶粒放置於所述晶圓上之前，將所述第二積體電路晶粒浸於所述助焊劑材料中。在實施例中，所述擋壩結構的第一側壁接觸所述第一包封體，所述擋壩結構的第二側壁接觸所述第二包封體，且所述擋壩結構的所述第一側壁與所述擋壩結構的所述第二側壁相對。
根據又一實施例，一種封裝體包括：基底；擋壩結構，位於所述基底之上，所述擋壩結構為環形結構；晶粒堆疊，位於所述基底之上且位於所述擋壩結構的開口內，所述晶粒堆疊包括多個積體電路晶粒及位於所述多個積體電路晶粒中的多個相鄰的積體電路晶粒之間的多個連接件接頭；第一包封體，沿所述多個積體電路晶粒的多個側壁延伸，所述第一包封體環繞所述多個連接件接頭；以及第二包封體，環繞所述晶粒堆疊、所述第一包封體及所述擋壩結構。在實施例中，所述第一包封體填充所述擋壩結構的所述開口。在實施例中，所述擋壩結構的第一側壁接觸所述第一包封體，所述擋壩結構的第二側壁接觸所述第二包封體，且所述擋壩結構的所述第一側壁與所述擋壩結構的所述第二側壁相對。在實施例中，所述第一包封體具有傾斜的多個側壁。在實施例中，所述晶粒堆疊的最頂部表面與所述第二包封體的最頂部表面齊平。在實施例中，所述第二包封體的側壁與所述基底的側壁共面。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應知，其可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本揭露的精神及範圍，而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替及變更。
100:晶圓級晶粒結構 101:載體 103:黏合層 105:晶片 105A:第一表面 105B:第二表面 107、109、205A、205B、205C、205D、205E、205F、205G、207A、207B、207C、207D、207E、207F、207G、303:連接件 107A、109A、205A1、205B1、205C1、205D1、205E1、205F1、205G1、207A1、207B1、207C1、207D1、207E1、207F1、207G1、3031:導電柱凸塊 107B、109B、205A2、205B2、205C2、205D2、205E2、205F2、205G2、207A2、207B2、207C2、207D2、207E2、207F2、207G2、3032:焊料元件 111、203A、203B、203C、203D、203E、203F、203G:穿孔 201A、201B、201C、201D、201E、201F、201G、301:積體電路晶粒 209:助焊劑材料 305:預接合的晶粒堆疊 401:晶粒堆疊 401A、401B、401C、401D、401E、401F、401G、401H:焊料接頭 403A、403B、403C、403D、403E、403F、403G、403H:連接件接頭 501:擋壩結構 503:切割道 601:正方形環形狀 603:圓形環形狀 605:橢圓形環形狀 701:底部填充膠 801:包封體 1001:積體電路封裝體 1101:工件 1200:方法 1201、1203、1205、1207、1209、1211、1213、1215:步驟 AA:線 D1:距離 H1、H2:高度 W1:寬度 W2:第一寬度 W3:第二寬度
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1至圖4、圖5A、圖5B以及圖6至圖11示出根據一些實施例的在積體電路封裝體的製作期間的各種處理步驟的俯視圖及剖視圖。 圖12示出根據一些實施例的一種形成積體電路封裝體的方法的流程圖。
100:晶圓級晶粒結構
101:載體
103:黏合層
105:晶片
107:連接件
107A:導電柱凸塊
107B:焊料元件
301:積體電路晶粒
401:晶粒堆疊
501:擋壩結構
701:底部填充膠
801:包封體

Claims (20)

  1. 一種形成封裝體的方法，包括： 將多個積體電路晶粒堆疊於晶圓上以形成晶粒堆疊； 對所述晶粒堆疊執行接合製程，所述接合製程將所述晶粒堆疊的多個相鄰的積體電路晶粒機械性及電性連接至彼此； 在所述晶圓之上形成擋壩結構，所述擋壩結構環繞所述晶粒堆疊； 在所述晶圓之上且在所述晶粒堆疊與所述擋壩結構之間形成第一包封體，所述第一包封體填充所述晶粒堆疊的所述多個相鄰的積體電路晶粒之間的多個間隙；以及 在所述晶圓之上形成第二包封體，所述第二包封體環繞所述晶粒堆疊、所述第一包封體及所述擋壩結構。
  2. 如申請專利範圍第1項所述的方法，更包括：在將所述多個積體電路晶粒堆疊於所述晶圓上之前，將所述晶圓貼合至載體。
  3. 如申請專利範圍第1項所述的方法，其中執行所述接合製程包括執行焊料回流製程。
  4. 如申請專利範圍第1項所述的方法，其中將所述多個積體電路晶粒堆疊於所述晶圓上包括：在將所述多個積體電路晶粒中的每一者放置於所述晶圓上之前，將所述多個積體電路晶粒中的每一者浸於助焊劑材料中。
  5. 如申請專利範圍第1項所述的方法，其中對所述晶粒堆疊執行所述接合製程包括：在所述晶粒堆疊的所述多個相鄰的積體電路晶粒之間形成多個連接件接頭。
  6. 如申請專利範圍第1項所述的方法，其中所述擋壩結構為環形結構。
  7. 如申請專利範圍第6項所述的方法，其中所述晶粒堆疊及所述第一包封體設置於所述擋壩結構的開口中。
  8. 一種形成封裝體的方法，包括： 將第一積體電路晶粒放置於晶圓上，所述晶圓包括位於所述晶圓的第一側上的多個第一連接件，所述第一積體電路晶粒包括位於所述第一積體電路晶粒的第一側上的多個第二連接件及位於所述第一積體電路晶粒的第二側上的多個第三連接件，所述第一積體電路晶粒的所述第一側與所述第一積體電路晶粒的所述第二側相對，所述多個第一連接件接觸所述多個第二連接件； 將第二積體電路晶粒放置於所述第一積體電路晶粒上，所述第二積體電路晶粒包括位於所述第二積體電路晶粒的第一側上的多個第四連接件及位於所述第二積體電路晶粒的第二側上的多個第五連接件，所述第二積體電路晶粒的所述第一側與所述第二積體電路晶粒的所述第二側相對，所述多個第三連接件接觸所述多個第四連接件； 對所述第一積體電路晶粒及所述第二積體電路晶粒執行接合製程，所述接合製程對所述多個第一連接件與所述多個第二連接件進行接合以形成多個第一連接件接頭，所述接合製程對所述多個第三連接件與所述多個第四連接件進行接合以形成多個第二連接件接頭； 在所述晶圓之上形成擋壩結構，所述擋壩結構環繞所述第一積體電路晶粒及所述第二積體電路晶粒； 在所述晶圓之上且在所述多個第一連接件接頭與所述多個第二連接件接頭周圍形成第一包封體；以及 在所述晶圓之上形成第二包封體，所述第二包封體環繞所述第一積體電路晶粒、所述第二積體電路晶粒、所述第一包封體及所述擋壩結構。
  9. 如申請專利範圍第8項所述的方法，其中執行所述接合製程包括：對所述多個第一連接件、所述多個第二連接件、所述多個第三連接件及所述多個第四連接件執行焊料回流製程。
  10. 如申請專利範圍第8項所述的方法，其中所述接合製程將所述多個第一連接件中的每一者的第一焊料層與所述多個第二連接件中的各別一者的第二焊料層合併以形成第一單一焊料層。
  11. 如申請專利範圍第10項所述的方法，其中所述接合製程將所述多個第三連接件中的每一者的第三焊料層與所述多個第四連接件中的各別一者的第四焊料層合併以形成第二單一焊料層。
  12. 如申請專利範圍第8項所述的方法，更包括：在將所述第一積體電路晶粒放置於所述晶圓上之前，將所述第一積體電路晶粒浸於助焊劑材料中。
  13. 如申請專利範圍第12項所述的方法，更包括：在將所述第二積體電路晶粒放置於所述晶圓上之前，將所述第二積體電路晶粒浸於所述助焊劑材料中。
  14. 如申請專利範圍第8項所述的方法，其中所述擋壩結構的第一側壁接觸所述第一包封體，其中所述擋壩結構的第二側壁接觸所述第二包封體，且其中所述擋壩結構的所述第一側壁與所述擋壩結構的所述第二側壁相對。
  15. 一種封裝體，包括： 基底； 擋壩結構，位於所述基底之上，所述擋壩結構為環形結構； 晶粒堆疊，位於所述基底之上且位於所述擋壩結構的開口內，所述晶粒堆疊包括多個積體電路晶粒及位於所述多個積體電路晶粒中的多個相鄰的積體電路晶粒之間的多個連接件接頭； 第一包封體，沿所述多個積體電路晶粒的多個側壁延伸，所述第一包封體環繞所述多個連接件接頭；以及 第二包封體，環繞所述晶粒堆疊、所述第一包封體及所述擋壩結構。
  16. 如申請專利範圍第15項所述的封裝體，其中所述第一包封體填充所述擋壩結構的所述開口。
  17. 如申請專利範圍第15項所述的封裝體，其中所述擋壩結構的第一側壁接觸所述第一包封體，其中所述擋壩結構的第二側壁接觸所述第二包封體，且其中所述擋壩結構的所述第一側壁與所述擋壩結構的所述第二側壁相對。
  18. 如申請專利範圍第15項所述的封裝體，其中所述第一包封體具有傾斜的多個側壁。
  19. 如申請專利範圍第15項所述的封裝體，其中所述晶粒堆疊的最頂部表面與所述第二包封體的最頂部表面齊平。
  20. 如申請專利範圍第15項所述的封裝體，其中所述第二包封體的側壁與所述基底的側壁共面。
TW108102516A 2018-10-31 2019-01-23 封裝體及其形成方法 TWI697090B (zh)

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