JP5125309B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5125309B2 JP5125309B2 JP2007213489A JP2007213489A JP5125309B2 JP 5125309 B2 JP5125309 B2 JP 5125309B2 JP 2007213489 A JP2007213489 A JP 2007213489A JP 2007213489 A JP2007213489 A JP 2007213489A JP 5125309 B2 JP5125309 B2 JP 5125309B2
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- Prior art keywords
- semiconductor element
- underfill resin
- substrate
- inorganic filler
- resin
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
図1は、本発明の第1実施形態に係るフリップチップ実装構造体としての半導体装置100の概略断面構成を示す図である。
図4は、本発明の第2実施形態に係るフリップチップ実装構造体としての半導体装置の概略断面構成を示す図である。上記第1実施形態との相違点を中心に述べる。
図5は、本発明の第3実施形態に係る半導体装置の製造方法におけるアンダーフィル樹脂40の注入工程を示す工程図である。本実施形態は、上記第1実施形態に示した注入工程において、無機フィラー41について一部変形を行ったところが相違するものであり、この相違点を中心に述べる。
図6は、本発明の第4実施形態に係る半導体装置の製造方法を示す工程図であり、各工程におけるワークを断面的に示したものである。
なお、半導体素子としては、上述したLow−k材料よりなる層間絶縁膜を持たないものであってもよい。また、基板にバンプ接合される半導体素子は、複数個であってもよく、その場合には、各半導体素子のアンダーフィル樹脂について上記実施形態を採用すればよい。
Claims (3)
- 基板(20)の一面(20a)と半導体素子(10)の一面(10a)とをバンプ(30)を介して対向させ、前記バンプ(30)を介して前記基板(20)と前記半導体素子(10)とを接合した後、
前記半導体素子(10)の側面(10b)側から前記基板(20)の前記一面(20a)と前記半導体素子(10)の前記一面(10a)との間に、無機フィラー(41)を含有するアンダーフィル樹脂(40)を注入して充填するようにした半導体装置の製造方法において、
前記アンダーフィル樹脂(40)の注入工程では、前記基板(20)を天側に位置させ、前記半導体素子(10)を地側に位置させた状態で、前記アンダーフィル樹脂(40)を注入することにより、前記アンダーフィル樹脂(40)のうち前記基板(20)寄りに位置する部位よりも前記半導体素子(10)寄りに位置する部位の方が、前記無機フィラー(41)が多く含有された状態となるようにすることを特徴とする半導体装置の製造方法。 - 前記基板(20)の前記一面(20a)における前記注入される前記アンダーフィル樹脂(40)に対する濡れ性を、前記半導体素子(10)の前記一面(10a)における当該濡れ性よりも大きくしたことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記アンダーフィル樹脂(40)に含有される前記無機フィラー(41)として、比重の異なる複数のものよりなるとともに比重が大きいもの(41a)が比重が小さいもの(41b)よりも細かい形状となっているものを用いることを特徴とする請求項1または2に記載の半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007213489A JP5125309B2 (ja) | 2007-08-20 | 2007-08-20 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007213489A JP5125309B2 (ja) | 2007-08-20 | 2007-08-20 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009049164A JP2009049164A (ja) | 2009-03-05 |
JP5125309B2 true JP5125309B2 (ja) | 2013-01-23 |
Family
ID=40501123
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007213489A Expired - Fee Related JP5125309B2 (ja) | 2007-08-20 | 2007-08-20 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
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JP (1) | JP5125309B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110193211A1 (en) * | 2010-02-05 | 2011-08-11 | Qualcomm Incorporated | Surface Preparation of Die for Improved Bonding Strength |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2930186B2 (ja) * | 1996-03-28 | 1999-08-03 | 松下電器産業株式会社 | 半導体装置の実装方法および半導体装置の実装体 |
JP3999840B2 (ja) * | 1997-04-16 | 2007-10-31 | 日東電工株式会社 | 封止用樹脂シート |
JP2000031345A (ja) * | 1998-07-13 | 2000-01-28 | Ricoh Co Ltd | 半導体装置 |
JP3992893B2 (ja) * | 1999-12-02 | 2007-10-17 | 富士通株式会社 | 半導体装置のアンダーフィル方法 |
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2007
- 2007-08-20 JP JP2007213489A patent/JP5125309B2/ja not_active Expired - Fee Related
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JP2009049164A (ja) | 2009-03-05 |
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