CN101252108A - 具有晶粒容纳通孔与连接通孔的半导体元件封装与其方法 - Google Patents

具有晶粒容纳通孔与连接通孔的半导体元件封装与其方法 Download PDF

Info

Publication number
CN101252108A
CN101252108A CNA2008100096973A CN200810009697A CN101252108A CN 101252108 A CN101252108 A CN 101252108A CN A2008100096973 A CNA2008100096973 A CN A2008100096973A CN 200810009697 A CN200810009697 A CN 200810009697A CN 101252108 A CN101252108 A CN 101252108A
Authority
CN
China
Prior art keywords
crystal grain
substrate
hole
connection pad
die receiving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2008100096973A
Other languages
English (en)
Inventor
杨文焜
林殿方
王东传
许献文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yupei Science & Technology Co Ltd
Original Assignee
Yupei Science & Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yupei Science & Technology Co Ltd filed Critical Yupei Science & Technology Co Ltd
Publication of CN101252108A publication Critical patent/CN101252108A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01059—Praseodymium [Pr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明提供一种具有晶粒容纳通孔与连接通孔的半导体元件封装与其方法，该半导体元件封装包含一具有一晶粒容纳通孔的基底、连接通孔结构、以及位于基底一上表面的第一接垫与位于基底一下表面的第二接垫。一晶粒配置在晶粒容纳通孔内部。一第一黏着材料形成在晶粒的底部以及一第二黏着材料被填入晶粒与晶粒容纳通孔侧壁之间的间隙。再者，一焊接线(bondingwire)被形成来耦合焊接垫(bonding pad)与第一接垫。介电层在焊线、晶粒以及基底上形成。本发明提供一种新的超薄封装结构，其能达到较佳的测试可靠度并且制造工艺简单，同时可降低成本并增加良率。

Description

具有晶粒容纳通孔与连接通孔的半导体元件封装与其方法
技术领域
本发明与一种半导体元件封装的结构有关，特别是关于一种具有晶粒容纳通孔与连接通孔的半导体元件封装结构与其方法，此结构能缩小封装的尺寸并改善其良率与可靠度。
背景技术
近年来，高科技电子制造工业推出了许多含有更多功能组合、更人性化的电子产品。半导体科技的发展使得半导体封装在尺寸缩小方面有快速的进程，如多脚位(multi-pin)和微脚距(fine pitch)技术的采用、电子零件的微型化之类。晶片级封装(wafer level package，WLP)的目的与好处包含减少生产成本、减少因为使用较短的导线路径而产生的寄生电容与寄生电感效应、获得较佳的信噪比(signal to noise ratio，SNR)。
因为一般封装技术得先将晶片上的晶粒(dice)分成个别的晶粒(dies)再分别进行封装，因此就制造方法而言，此类技术相当耗时。由于芯片封装技术深受集成电路发展的影响，因此对电子装置的大小要求越来越多，对封装技术亦然。基于上述理由，今日封装技术的趋势是朝球门阵列(ball grid array，BGA)、覆晶球门阵列(flip chip ball grid array，FC-BGA)、芯片尺寸封装(chipscale package，CSP)及晶片级封装(wafer level package，WLP)发展。“晶片级封装”被认为是在晶片被分(切割)成晶粒(dies)之前先进行整体的封装与连接以及其它制成步骤。通常，完成所有组装步骤或封装步骤后，独立的半导体封装会从一含有多个半导体芯片的晶片上分离。晶片级封装具有极小的尺寸兼极佳的电性。
在制造方法中，晶片级芯片尺寸封装(WLCSP)为一先进的封装技术，其晶粒是在晶片上制造与测试的，随后再以切割(dicing)的方式分离以在一表面黏着线(surface mount line)上进行组装。因为晶片级封装技术采用整片晶片作为一对象，而非采用单一的芯片或晶粒，因此，在划线(scribing)流程施行之前封装与测试就已经完成了；再者，WLP因为是非常先进的技术，以往焊接线接合(wire bonding)、芯片黏结(die mount)、点胶(under-fill)的步骤都可以省略。借着使用WLP技术，其成本与制造时间都可减少，且产生的WLP结构可与晶粒相同；因此，此技术可以满足电子装置微型化的需求。再者，晶片级芯片尺寸封装能使用晶粒的周边区域作为焊接点来将重布电路(redistribution circuit)直接印刷在晶粒上，为其优点之一。此方法是将晶粒表面上一区域阵列作重新分布，可充分运用到整块晶粒区域。焊接点是以形成覆晶凸块的方式配置在重布电路上，故晶粒的底面能通过间距微小的焊接点直接连接到印刷电路板(PCB)。
虽然晶片级芯片尺寸封装(WLCSP)能大幅减少信号路径的距离，但随着晶粒与内部元件的整合度越来越高，要将所有焊接垫配置在晶粒表面上仍旧是非常困难的。因为晶粒上的脚位数会随着整合度的提升而增加，故此要在一区域阵列内将脚位重布化是很困难的。就算脚位成功地重布化，其脚位间的距离会太小而无法配合印刷电路板(PCB)的间距(pitch)。换言之，由于封装的尺寸庞大，此种先前技术的制造工艺与结构会有良率与可靠度的问题。另外在制造上也有成本较高与耗时的缺点。
WLP技术是一种先进的封装技术，其晶粒是在晶片上制造与测试的，随后再以切割(dicing)的方法分离在一表面黏着线(surface mount line)上进行组装。因为晶片级封装技术采用整片晶片作为一对象，而非采用单一的芯片或晶粒，因此，在划线切割(scribing)流程施行之前封装与测试就已经完成了；再者，因为WLP是非常先进的技术，以往焊线接合(wire bonding)、芯片黏结(die mount)、底部填充(under-fill)的步骤都可以省略。借着使用WLP技术，其成本与制造时间都可减少，且产生的WLP结构可与晶粒相同；因此，此技术可以满足电子装置微型化的需求。
尽管有上述的优点，WLP技术仍旧存在有一些问题影响着业界对于WLP技术的接受度，举例而言，WLP与母板(PCB)之间结构材料的热膨胀系数差别(不合)就成为另一个关系到结构机械性不稳定的重要因素。美国专利号US 6,271,469中所揭示的一封装架构就遭遇热膨胀系数不合的问题。这是因为其先前技术使用由塑模化合物(molding compound)包覆的硅晶粒。如所知者，硅材料的热膨胀系数为2.3，但塑模化合物的热膨胀系数约在20到80之间。因为塑模化合物与介电层材料的热固温度(curing temperature)比较高，此配置会在制造工艺期间造成芯片位置的偏移，而其接垫(pads)将偏移而造成良率与效能问题。在热循环的过程中要回到其原始位置是很困难的(其为环氧树脂在热固温度接近/超过Tg温度时的性质所致)。此意味着先前的封装结构不能以大尺寸方式处理，而这会使得制造成本更高。
再者，有一些技术牵涉到将晶粒直接在基底的上表面形成。如所知者，半导体晶粒的接垫会经过重布制造工艺(redistribution)进行再分布，其牵涉到一重布层(redistribution layer，RDL)被形成在一阵列区域中多个金属接垫上。增层(build-up layer)会增加封装的尺寸。因此，整体封装的厚度会增加。这会与减少芯片尺寸大小的需求冲突到。
况且，一般形成面板类型封装时，先前技术将衍生制造工艺过于复杂的问题。它需要封装用的成形工具以及射出用的成形材料。由于成形材料加热后会产生翘曲，要将晶粒表面与成形材控制在同样的高度水平是不大可能的，故需要化学机械研磨制造工艺(CMP)来研磨其不平整的表面，成本也因而增加。
依前述观点，本发明提供一种具有晶粒容纳通孔与连接通孔的新的结构与方法来进行面板尺寸封装(panel scale package，PSP)以克服上述的缺点。
发明内容
此处本发明将描述一些较佳实施例。然而，本发明能在这些细节描述以外的其它实施例中广泛的实行。本发明的范畴并不局限于这些实施例，而应依据下列专利权利要求的限制。
本发明的目的之一为提出一种半导体元件封装的结构与其方法，能提供一种新的超薄封装结构。
本发明的另一目的为提出一种半导体元件封装结构与其方法。由于此结构的基底与PCB具有相同的热膨胀系数，故能达到较佳的测试可靠度。
本发明的又一目的为提出一种半导体元件封装结构与其方法，能提供一简单的制造工艺来形成一半导体元件封装。
本发明的又一目的为提出一种半导体元件封装结构与其方法，可降低成本并增加良率。
本发明的另一目的为提出一种半导体元件封装结构与其方法，可提供低脚数元件一良好的解决方案。
本发明提供一种半导体元件封装的结构，包含：一基底具有一晶粒容纳通孔、连接通孔结构，基底的上表面有第一接垫，基底的下表面有第二接垫；一含有焊接垫的晶粒配置在晶粒容纳通孔内部；一第一黏着材料形成在晶粒的底部；一第二黏着材料填入其基底上晶粒与晶粒容纳通孔侧壁之间的间隙；一焊接线被形成来耦合焊接垫与第一接垫；以及一介电层形成在焊接线、晶粒及基底上。
本发明提供一种方法来形成一半导体元件封装，其包含：提供一基底，其具有晶粒容纳通孔、电连接通孔结构，该基底的上表面上有第一接垫，基底的下表面上有第二接垫；使用一捡放(pick and place)精细对准系统来将具有焊接垫的晶粒依其理想的间距在一晶粒重布工具上进行重布；将基底置放于晶粒重布工具并黏结；在晶粒的背面填上一第一黏着材；将一第二黏着材料填入其晶粒边缘与该基底的晶粒容纳通孔之间的空间；将面板(片板形式代表其基底上带有晶粒且彼此相黏)从晶片重布层分开；形成一焊接线以连接焊接垫与第一接垫；将一介电层以印刷(print)、封胶(molding)或分注(dispensing)的方法形成在晶粒的主动面与基底的上表面上；并将封装结构(面板形式)固定在一胶带上来切割成独立的晶粒以进行后续的切割(singulartion)步骤。
本发明提供一种方法来形成一半导体元件封装，其包含：提供一基底，其具有一晶粒容纳通孔、连接通孔结构，基底的上表面上有第一接垫，基底的下表面上有第二接垫；将基底黏结在一晶粒重布工具上；使用一捡放(pickand place)精细对准系统在一晶粒重布工具上进行重布，其具有焊接垫的晶粒会依其理想的脚距置入基底的晶粒容纳通孔中；形成一焊接线来连接焊接垫与第一接垫；形成一介电层在晶粒的有效表面上与基底的上表面上以及晶粒与晶粒容纳通孔侧壁之间的间隙中；将面板(面板形式代表基底上带有晶粒，而此处的黏着材料为介电层)从晶粒重布工具上分开；并将封装结构(面板形式)固定在一胶带上切割成独立的晶粒以进行后续的切割分离(singulartion)步骤。
本发明提供一种新的超薄封装结构，其能达到较佳的测试可靠度并且制造工艺简单，同时可降低成本并增加良率。
附图说明
本发明前述的观点与许多伴随的优点将由参照下列的细节描述连同其随附图而变得更佳清楚明了，其中：
图1为说明一根据本发明一实施例的半导体元件封装结构的截面图；
图2a为说明一根据本发明另一实施例的半导体元件封装结构的截面图；
图2b为说明一根据本发明另一实施例的半导体元件封装结构的截面图；
图3为说明一根据本发明一实施例的半导体元件封装结构的截面图；
图4为说明一根据本发明一实施例的半导体元件封装结构的顶视图；
图5a为说明一根据本发明一实施例的半导体元件封装结构的顶视图；
图5b为说明一根据本发明另一实施例的半导体元件封装结构的顶视图；
图6a至图6b为说明根据本发明一实施例一形成半导体元件封装的方法的截面图；
图7a至图7f为说明根据本发明另一实施例一形成半导体元件封装的方法的截面图；
主要元件符号说明：
100  封装结构
102  基底
104  晶粒
105  晶粒容纳通孔
106  第一黏着材料
107  第二黏着材料
108  焊接垫
110  导电层
112  焊接线
113  第一接垫
114  连接通孔结构
115  第二接垫
118  介电层
120  凸块
200  封装结构
202  基底
204  晶粒
205  晶粒容纳通孔
206  第一黏着材料
207  第二黏着材料
208  焊接垫
210  导电层
212  焊接线
213  第一接垫
214  连接通孔结构
215  第二接垫
218  介电层
220  凸块
230  切割道
232  切割刀
具体实施方式
本发明于下列的描述中提出有多个具体的细节以让阅者对于本发明的实施方式有一全盘性的了解。现在请参照下列的描述，其中该描述的目的仅为说明本发明的较佳实施例，而非局限。然而，相关领域的熟习技艺者可认知到本发明的实行不需有一或多个特定具体的细节，或是需要具备其它的方法、元件、材料等。
请参照图1，其为根据本发明一实施例的一半导体元件封装结构100的截面图。封装结构100包含一基底102、一晶粒104、一晶粒容纳通孔105、一第一黏着材料106、一第二黏着材料107、焊接垫108、一金属或导电层110、焊接线112、第一接垫113、连接通孔结构114、第二接垫115、一介电层118以及多个导电凸块(bumps)120。
在图1中，基底102具有一晶粒容纳通孔105形成于其中以容纳一晶粒104。晶粒容纳通孔105自基底102的上表面穿透基底102达下表面形成。晶粒容纳通孔105为预先形成于基底102内。第二黏着材料107也被填入晶粒边缘104与晶粒容纳通孔105侧壁之间的空间。第一黏着材料106被涂布晶粒104的下表面，因而将晶粒104密封。
第一黏着材料106与第二黏着材料107可使用相同的材料。
基底102还包含连接通孔结构114形成于其中。第一接垫113与第二接垫115(用于有机材料基底)分别形成在连接通孔结构114与部分基底102的上表面与下表面上。导电材料被填入连接通孔结构114以导通电流，此制造工艺可在基底制作过程中实行。
也可选择将一金属或导电层110镀在晶粒容纳通孔105的侧壁上，也就是说，金属层110于第二黏着材料107所围绕的晶粒104与基底102之间形成。使用一些特殊的黏着材料，特别是橡胶类的黏着材料，可改善晶粒边缘与基底的晶粒容纳通孔105侧壁之间的黏着强度。
晶粒104被配置在基底102上的晶粒容纳通孔105内部。如所知者，焊接垫被形成用以耦合焊接垫108与第一接垫113。一介电层118被形成用以覆盖焊接线112以及晶粒104与基底102的上表面。接着，数个导电凸块(bumps)120会形成并耦合至第二接垫115，其作法为将锡膏(solder paste)印在表面上，再施行回焊步骤以利于将锡膏焊接起来。如此，在晶粒104内部形成的焊接垫108可经由连接通孔结构114与导电凸块120导通。
介电层118是用来避免封装受到外力影响造成封装受损。由于第二黏着材料107具有弹性，金属层110与第二黏着材料107可作为缓冲层来吸收温度循环期间晶粒104与基底102之间的热机械应力。前述的结构建构出一种基板栅格阵列(land grid array，LGA)封装形式。
在一实施例中，基底102的材料包含环氧树脂类的FR5、FR4或BT树脂(Bismaleimide triazine双马来酰亚胺三嗪)。基底102的材料也可为金属、合金、玻璃、硅材、陶瓷或印刷电路板(PCB)。其合金可还包含42合金(42％Ni-58％Fe)或Kovar合金(29％Ni-17％Co-54％Fe)。再者，其合金金属最好以含有铁镍成分的42合金组成，其热膨胀系数适合用于微型电路的硅芯片中。而合金金属也能以含有镍钴铁成分的Kovar合金组成。
基底102的材料以有机基底为佳，如含有已定义通孔的环氧树脂类FR5、BT、PCB或是含有预先刻蚀出的电路的铜金属。其热膨胀系数最好与母板(PCB)一样。由于基底102的热膨胀系数与PCB(或母板)相合，本发明可提供一测试可靠度较佳的结构。具有高玻璃转换温度(glass transitiontemperature，Tg)的有机基底以环氧树脂类的FR5或BT类的基底为佳。铜金属(热膨胀系数约为16)也可被使用。玻璃、陶瓷、硅材也可作为基底材料。其第二黏着材料是以硅胶弹性材料形成。
在一实施例中，第一黏着材料106与第一黏着材料的材质包含紫外线固化类(UV curing)与/或热固类(thermal curing)材料、环氧树脂或橡胶类材料。第一黏着材料106也可包含金属材料。再者，介电层118的材料包括液态化合物、树脂、硅胶，也可为BCB(benzocyclobutene，苯环丁烯)、SINR(siloxanepolymer，硅氧烷聚合物)或PI(polyimide，聚酰亚胺)等材料。
请参照图2a，其为根据本发明另一实施例的一半导体元件封装结构200的截面图。基底202包含一连接通孔结构214在基底的四端形成，也就是说，连接通孔结构214是分别在基底202的两侧边形成(也可能是四边)。第一接垫213与第二接垫215分别形成在连接通孔结构214与基底202部分结构的上表面与下表面。导电材料会被填入连接通孔结构中以导通电流。接着，数个导电凸块(bumps)220被耦合至第二接垫215。如此，在晶粒204中形成的焊接垫208可经由连接通孔结构214与导电凸块220导通。
也可选择将一金属或导电层210镀在晶粒容纳通孔205的侧壁上，即，金属层210在第二黏着材料207所围绕的晶粒204与基底202之间形成。
此外，封装结构200中多种的组成对象都与封装结构100中的类似，如图1与图2a、图2b所示，故此处省略其细节描述。
图2b为根据本发明一半导体元件封装结构200的截面图。其第一接垫213是在连接通孔结构214的上方形成。连接通孔结构214为于切割道(scribeline)230中。换言之，每个封装在切割后会具有一半的通孔结构214。这能改善SMT制造工艺期间焊点(solder joint)的质量并能缩小连接垫(footprint)的大小。同样地，半通孔结构214可形成在晶粒容纳通孔205上(图中未表示)，它可用来取代导电层210。
请参照图3，其为根据本发明的一半导体元件封装100的截面图。图3中可见到另一实施例，其封装结构100不需在第二终端接垫115上形成导电凸块120。此结构其它部分与图1的结构类似，故此处省略其细节描述。
基底102与第二接垫115之间的厚度a最好约为118-218μm。介电层的厚度b最好约为50-100μm。如此，本发明可提供一种厚度小于200μm的超薄结构，其封装尺寸约为晶粒尺寸每边加0.5mm到1mm之间，可使用一般印刷电路板的制造工艺来形成一芯片尺寸封装(CSP，chip scalepackage)。
请参照图4，其说明了一根据本发明实施例的一半导体元件封装结构100的底视图。此封装结构100的背面包含基底102(防焊绿漆层并未在图中显示)与一第二黏着层107形成于其中并被多个第二接垫115围绕。封装结构100包含：一第一黏着材料106，其为一层金属层溅镀与/或电镀在晶粒104上；一第二黏着材料107来加强其热传导性，如图中的虚线区域所示。可用锡膏将其与印刷电路板(PCB)焊接。它可经由印刷电路板的铜金属来排除晶粒产生的热。
请参照图5a，其说明了一根据本发明实施例的一半导体元件封装结构100的顶视图。封装结构100的顶面包含基底102、一晶粒具有多个焊接垫108形成在第一黏着材料106上。多个第一接垫113在基底102四周的的边缘区域形成。此外，封装100还包含多个焊接线112来耦合焊接垫108与第一接垫113。须注意焊接线112在介电层118形成之后是被隐蔽的。
在其它方面，封装100也可以应用到较高的脚位数中。图5b说明了一根据本发明的半导体元件封装结构100的顶视图。此结构的其它部位与图5a相似，故此处省略其细节描述。据此，本发明的周边安排方式可提供低脚数装置一良好的解决方案。
须注意根据本发明的观点，图4、图5a及图5b中的封装结构100也可为封装结构200。
根据本发明的观点，本发明还提供一方法来形成一种带有晶粒容纳通孔105与连接通孔结构114的半导体元件封装100。请参照图6a与图6b的截面图，其说明了一种用来形成一半导体元件封装100的方法。其步骤如下，而下述的步骤也可参照图7a至图7f。
首先，基底102被提出，其具有晶粒容纳通孔105、连接通孔结构114，该基底102的上表面有第一接垫113，基底的下表面有第二接垫115，其中晶粒容纳通孔105与连接通孔结构114与第一接垫113以及第二接垫115在基底102中形成，如图6a所示。用一捡放精细对准系统来将具有焊接垫108的晶粒104依理想的间距在一晶粒重布工具300上进行重布，如图6b所示。基底102被黏结到晶粒重布工具300，也就是说，晶粒104的有效表面黏在由图形胶(未表示)印出的晶粒重布工具300上。在第二黏着材料107被填入晶粒104与其背面的第一黏着材料106之间的空隙后，第一与第二黏着材料106会被固化(cured)。在此应用中，第一黏着材料106与第二黏着材料107可为相同的材料。其后，将封装结构从晶粒重布工具300上分离。
在清洁焊接垫108与第一接垫113的上表面之后(图形胶可能会残留在焊接垫108与第一接垫113的上表面)，焊接线112会被形成来连接焊接垫108与第一接垫113。为了要保护焊接线112，介电层118被涂布(或印刷或分注)并固化在晶粒104的动态表面与基底102的上表面上。其后，以锡膏(或锡球)印刷的方式将终端接垫形成在第二接垫115的上方。之后，用红外线(IR)回焊的方法形成多个导电凸块120并将其耦合至第二接垫115。随后，封装结构被固定在一胶带302上来切割成独立的晶粒以进行后续的切割分离(singulation)步骤。
一金属或导电层110可选择性地形成在基底102的晶粒容纳通孔105侧壁上，此金属层是在基底制造的期间就预先在基底上形成。一金属薄膜(或金属层)可用溅镀或电镀的方式形成在晶粒104的背面作为第一黏着材料以提供较佳的热管理需求(thermal management inquiry)。
根据本发明另一实施例，本发明还提出另一方法来形成具有晶粒容纳通孔205与连接通孔结构214的半导体元件封装200。请参照图7a至图7f的截面图，其根据本发明说明了一种用来形成一半导体元件封装200的方法。
形成封装200的步骤包含：提供一基底202，其具有晶粒容纳通孔205、连接通孔结构215，该基底202的上表面上有第一接垫213，基底的下表面上有第二接垫215。基底202与一晶粒重布工具300黏结，如图7a所示。换言之，基底202的主动面(焊点分布的那一面)黏着在由具有图形的胶材质上(未表示)，胶材质可印刷在晶粒重布工具300上。挑出的晶粒204上具有焊接垫208且第一黏着材料206(选择性的)形成在该晶粒204的背面，如图7b所示。用一捡放精细对准系统将晶粒204依理想的间距在晶粒重布工具300上进行重布。随后，焊接线212会被形成来连接焊接垫208与第一接垫213，如图7c所示。
接着，介电层218会形成在晶粒204与基底202的上表面上，用以将完全覆盖焊接线212并填入其晶粒边缘与晶粒容纳通孔205侧壁之间的空隙作为一第二黏着材料207，如图7d所示。随后将介电层218固化。在封装结构与晶粒重布工具300分离后，将基底202的背面与第一黏着材料206清洁干净，如图7e所示。
此外，用锡膏(或锡球)印刷的方式在第二接垫215上形成终端接垫，其为选择性地形成多个导电凸块220并耦合至第二接垫215。随后，封装结构会被固定在一胶带302上切割成独立的晶粒以进行切割分离(singulation)步骤。
在一实施例中，其于切割分离制造工艺中得使用一传统的切割刀片232。切割分离制造工艺期间，切割刀片232会与切割道230对齐以将晶粒分割成独立的晶粒，如图7f所示。
一金属层或导电层210可选择性地形成在基底202的晶粒容纳通孔205侧壁上，此金属层于基底202的制造期间便预先在基底上形成。另一制造工艺中，其使用包含：晶种金属溅镀、图案成形、电镀(铜)、去光刻胶、金属湿刻蚀等制造工艺步骤来形成第一黏着材料206作为其后的金属层。
一实施例中，导电凸块120与220是用红外线回焊(IR reflow)的方法形成。
须注意者，实施例中结构材料与排列的说明是用以描述本发明而非限制本发明。其结构的材料与排列可根据不同的情况需求而作变更。
根据本发明的一观点，本发明提出了一种具有晶粒容纳通孔与连接通孔结构的半导体元件结构，可提供一厚度低于200μm的超薄封装结构，其封装尺寸比晶粒尺寸稍微大一点。此外，由于其周边排列的形式，本发明可提供低脚数(low pin count)元件一良好的解决方案。本发明提出一简单的方法来形成一种可改善可靠度与良率的半导体元件封装。再者，本发明还提出一种具有晶粒容纳通孔与连接通孔的新结构，因而能够缩小芯片尺寸封装(chipscale package)结构的大小。由于其材料成本较低与制造工艺简单，故也能降低生产成本。因此，本发明所揭示的超薄芯片尺寸封装结构与其方法可提供的于先前技术不可预期的效果，并解决先前技术的问题。本方法可应用在晶片或面板工业，并可被修改来用在其它相关的应用方面。
如同相关领域的熟习技艺者所能了解的，前述本发明的较佳实施例为本发明的解说，而非局限了本发明。随着发明连同其较佳实施例的描述，其中的修改变更自能为相关领域的熟习技艺者所知悉。故，本发明并不为此实施例所限制。反之，本发明欲涵盖其权利要求的精神与范畴中不同的变更修改与类似的排列配置，其范畴应从宽释意以涵盖所有此类变更与类似的结构。

Claims (10)

1.一种半导体元件封装结构，其特征在于，所述半导体元件封装结构包含：
一基底，具有一晶粒容纳通孔与一内部填有导电材料的连接通孔结构形成在所述基底的侧边，所述基底的上表面具有第一接垫，所述基底的下表面具有第二接垫；
一具有焊接垫的晶粒，配置在所述晶粒容纳通孔内部；
第一黏着材料，形成在所述晶粒的底部；
第二黏着材料，被填入所述晶粒与所述基底的晶粒容纳通孔侧壁之间的间隙；
一焊接线，被形成来耦合所述焊接垫与所述第一接垫；及
一介电层，形成在所述焊接线、所述晶粒以及所述基底上。
2.如权利要求1所述的半导体元件封装结构，其特征在于，所述半导体元件封装结构还包含多个导电凸块耦合至所述第二接垫，所述多个导电凸块可经由所述通孔结构与所述焊接垫电性导通。
3.如权利要求1所述的半导体元件封装结构，其特征在于，所述半导体元件封装结构还包含金属层或导电层形成在所述基底的晶粒容纳通孔的侧壁上。
4.如权利要求1所述的半导体元件封装结构，其中所述第一黏着材料与第二黏着材料的材质包含紫外线固化类与/或热固类材料、环氧树脂或橡胶类材料。
5.一种用来形成半导体元件封装的方法，该方法包含：
提供一具有晶粒容纳通孔与连接通孔结构的基底，所述基底的上表面有第一接垫，所述基底的下表面有第二接垫，所述连接通孔分别耦合所述第一接垫与所述第二接垫；
使用一捡放精细对准系统将具有焊接垫的晶粒依适当的间距在一晶粒重布工具上进行重布；
将所述基底黏在所述晶粒重布工具上；
将第一黏着材料涂在所述晶粒的背面；
将第二黏着材料填入所述晶粒边缘与所述基底的晶粒容纳通孔之间的空间中；
将所述封装结构与所述晶粒重布工具分离；
形成焊接线来连接所述焊接垫与所述第一接垫；
将介电层形成在所述晶粒的有效表面以及所述基底的上表面；及
将所述封装结构固定在胶带上切割成独立的晶粒以进行切割步骤。
6.如权利要求5所述的方法，其特征在于，所述方法还包含下列步骤：将多个焊接凸块焊在所述第二接垫上，将所述晶粒的有效面黏在所述具有图案的胶材质上，将所述第一黏着材料与第二黏着材料固化，将所述介电层固化。
7.如权利要求5所述的方法，其特征在于，所述方法还包含下列步骤：在所述基底的晶粒容纳通孔侧壁上形成一金属层或导电层，在形成所述焊接线前先清洗所述封装的上表面。
8.一种用来形成半导体元件封装的方法，该方法包含：
提供一具有晶粒容纳通孔与连接通孔结构的基底，所述基底的上表面有第一接垫，所述基底的下表面有第二接垫；
将所述基底黏到一晶粒重布工具；
将所述具有接垫的晶粒用一精细对准取置系统在所述晶粒重布工具上以适当的间距进行重布；
形成一焊接线以连接所述接垫与所述第一接垫；
在所述晶粒的有效面与所述基底的上表面形成一介电层并将其填入晶粒边缘与所述基底的晶粒容纳通孔侧壁之间的空隙；
将所述封装结构与所述晶粒重布工具分离；及
将所述晶粒结构固定在一胶带上并切割成个别独立的晶粒。
9.如权利要求8所述的方法，其特征在于，所述方法还包含下列步骤：
将复数个导电凸块焊在所述第二接垫上；
用图形胶将所述晶粒背面黏在所述晶粒重布工具上；
将所述介电层固化。
10.如权利要求8所述的方法，其特征在于，所述方法还包含下列步骤：
将复数个导电凸块焊在所述第二接垫上；
在所述晶粒背面形成一第一黏着层；
在所述基底的晶粒容纳通孔侧壁上形成一层金属层。
CNA2008100096973A 2007-02-21 2008-02-20 具有晶粒容纳通孔与连接通孔的半导体元件封装与其方法 Pending CN101252108A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/677,489 2007-02-21
US11/677,489 US20080197478A1 (en) 2007-02-21 2007-02-21 Semiconductor device package with die receiving through-hole and connecting through-hole and method of the same

Publications (1)

Publication Number Publication Date
CN101252108A true CN101252108A (zh) 2008-08-27

Family

ID=39646282

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2008100096973A Pending CN101252108A (zh) 2007-02-21 2008-02-20 具有晶粒容纳通孔与连接通孔的半导体元件封装与其方法

Country Status (7)

Country Link
US (1) US20080197478A1 (zh)
JP (1) JP2008244451A (zh)
KR (1) KR20080077936A (zh)
CN (1) CN101252108A (zh)
DE (1) DE102008010098A1 (zh)
SG (1) SG145666A1 (zh)
TW (1) TW200836320A (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102132403A (zh) * 2008-08-28 2011-07-20 费查尔德半导体有限公司 模制超薄半导体管芯封装和使用该封装的系统及其制造方法
CN103378016A (zh) * 2012-04-28 2013-10-30 鸿富锦精密工业（深圳）有限公司 芯片组装结构、芯片组装方法及光纤耦合模块
CN106601701A (zh) * 2017-01-19 2017-04-26 贵州煜立电子科技有限公司 大功率二端表面引出脚电子元器件立体封装方法及结构
CN109920773A (zh) * 2019-01-31 2019-06-21 厦门云天半导体科技有限公司 一种基于玻璃的芯片再布线封装结构及其制作方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102270622A (zh) * 2010-06-07 2011-12-07 佳邦科技股份有限公司 裸片尺寸半导体元件封装及其制造方法
US9570376B2 (en) 2010-06-29 2017-02-14 General Electric Company Electrical interconnect for an integrated circuit package and method of making same
US8653670B2 (en) * 2010-06-29 2014-02-18 General Electric Company Electrical interconnect for an integrated circuit package and method of making same
US9508674B2 (en) * 2012-11-14 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control of semiconductor die package
US10109588B2 (en) 2015-05-15 2018-10-23 Samsung Electro-Mechanics Co., Ltd. Electronic component package and package-on-package structure including the same
WO2017105502A1 (en) * 2015-12-18 2017-06-22 Intel IP Corporation Vertical wire connections for integrated circuit package
CN106024650A (zh) * 2016-07-19 2016-10-12 常州市武进区半导体照明应用技术研究院 一种免封装器件的紫外固化压膜装置及工艺
CN113555326A (zh) * 2021-06-03 2021-10-26 珠海越亚半导体股份有限公司 可润湿侧面的封装结构与其制作方法及垂直封装模块

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102132403A (zh) * 2008-08-28 2011-07-20 费查尔德半导体有限公司 模制超薄半导体管芯封装和使用该封装的系统及其制造方法
CN102132403B (zh) * 2008-08-28 2014-03-12 费查尔德半导体有限公司 模制超薄半导体管芯封装和使用该封装的系统及其制造方法
CN103378016A (zh) * 2012-04-28 2013-10-30 鸿富锦精密工业（深圳）有限公司 芯片组装结构、芯片组装方法及光纤耦合模块
CN106601701A (zh) * 2017-01-19 2017-04-26 贵州煜立电子科技有限公司 大功率二端表面引出脚电子元器件立体封装方法及结构
CN106601701B (zh) * 2017-01-19 2023-03-28 贵州煜立电子科技有限公司 大功率二端表面引出脚电子元器件立体封装方法及结构
CN109920773A (zh) * 2019-01-31 2019-06-21 厦门云天半导体科技有限公司 一种基于玻璃的芯片再布线封装结构及其制作方法

Also Published As

Publication number Publication date
SG145666A1 (en) 2008-09-29
TW200836320A (en) 2008-09-01
US20080197478A1 (en) 2008-08-21
DE102008010098A1 (de) 2008-08-28
KR20080077936A (ko) 2008-08-26
JP2008244451A (ja) 2008-10-09

Similar Documents

Publication Publication Date Title
CN101252108A (zh) 具有晶粒容纳通孔与连接通孔的半导体元件封装与其方法
US7763494B2 (en) Semiconductor device package with multi-chips and method of the same
CN210006732U (zh) 芯片封装结构
US7525185B2 (en) Semiconductor device package having multi-chips with side-by-side configuration and method of the same
US7459729B2 (en) Semiconductor image device package with die receiving through-hole and method of the same
US8178963B2 (en) Wafer level package with die receiving through-hole and method of the same
US7655501B2 (en) Wafer level package with good CTE performance
US7838332B2 (en) Method of manufacturing a semiconductor package with a bump using a carrier
US7413925B2 (en) Method for fabricating semiconductor package
US20080251908A1 (en) Semiconductor device package having multi-chips with side-by-side configuration and method of the same
US8178964B2 (en) Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same
KR100985809B1 (ko) 반도체 장치의 제조 방법
US20080217761A1 (en) Structure of semiconductor device package and method of the same
US20110209908A1 (en) Conductor package structure and method of the same
CN101221937A (zh) 具有晶粒容纳通孔之晶圆级封装与其方法
CN101262002A (zh) 具有晶粒容纳通孔的影像传感器封装与其方法
US20080157358A1 (en) Wafer level package with die receiving through-hole and method of the same
US20020074147A1 (en) Bump chip lead frame and package
US20080197480A1 (en) Semiconductor device package with multi-chips and method of the same
CN101728368A (zh) 具有多晶粒的半导体组件封装结构及其方法
US20080157398A1 (en) Semiconductor device package having pseudo chips
US20110031594A1 (en) Conductor package structure and method of the same
US20040061243A1 (en) Window-type semiconductor package and fabrication method thereof
US20050248029A1 (en) Embedded chip semiconductor without wire bondings
JP3694469B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20080827