US20130288430A1 - Semiconductor device and method for manufacturing thereof - Google Patents
Semiconductor device and method for manufacturing thereof Download PDFInfo
- Publication number
- US20130288430A1 US20130288430A1 US13/921,956 US201313921956A US2013288430A1 US 20130288430 A1 US20130288430 A1 US 20130288430A1 US 201313921956 A US201313921956 A US 201313921956A US 2013288430 A1 US2013288430 A1 US 2013288430A1
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- semiconductor chip
- semiconductor
- resin portion
- chip
- manufacturing
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title description 24
- 229920005989 resin Polymers 0.000 claims abstract description 69
- 239000011347 resin Substances 0.000 claims abstract description 69
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- 229910052710 silicon Inorganic materials 0.000 description 3
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Abstract
Description
- The present invention is based on Japanese Patent Application No. 2007-070016 filed on Mar. 19, 2007, the entire disclosure of which is hereby incorporated by reference.
- The invention relates to a semiconductor device and a method for manufacturing thereof, and more particularly to a semiconductor device formed by flip-chip bonding a second semiconductor chip onto a first semiconductor chip and a method for manufacturing thereof.
- The semiconductor device formed by stacking plural semiconductor chips has been under development for the purpose of reducing the packaging density. The CoC (Chip-on-Chip) technique for flip-chip bonding the semiconductor chip onto the other one has been employed to reduce the packaging density.
- Japanese Unexamined Patent Application Publication No. 2000-156461 discloses the following technique as shown in
FIGS. 8 to 13 . That is, the second semiconductor chip (numbered as 130 in the document) and the solder ball interposer (32 in the document) are flip-chip bonded (FCB) onto the semiconductor wafer (140 in the document), and then the second semiconductor chip is coated. The coating (34 in the document) is flattened to expose the surface of the solder ball interposer. The first semiconductor chip formed from the semiconductor wafer has the second semiconductor chip flip-chip bonded thereto and is coated to be connectable from the upper surface. - Japanese Unexamined Patent Application Publication No. 2004-146728 discloses the following technique. That is, the second semiconductor chip (numbered as 1 in the document) is flip-chip bonded onto the first semiconductor chip (2 in the document) to form the solder electrode (11 in the document) on the first semiconductor chip so as to be connectable to the outside at the position higher than the second semiconductor chip.
- In the case where the second semiconductor chip is flip-chip bonded onto the first semiconductor chip for increasing the packaging density, it is difficult to satisfy the requirement to reduce the thickness of the second semiconductor chip to less than 100 μm due to difficulty in handling of the thin semiconductor chip from the wafer and the chip tray. In the case where the flip chip bonding (FCB) is performed with the Au (gold)-Au pressure bonding process, the following difficulty occurs in addition to the difficulty in handling of the semiconductor chip. That is, the thin semiconductor chip which has been pressure bonded causes the underfill material to flow to the upper surface of the semiconductor chip and to be further adhered to the bonding tool used for handling the semiconductor chip. Accordingly, it is difficult to reduce the thickness of the semiconductor chip used in the CoC technique for packaging the semiconductor chip through the FCB.
- In the process disclosed in Japanese Unexamined Patent Application Publication No. 2000-156461 and Japanese Unexamined Patent Application Publication No. 2004-146728, the side surface of the first semiconductor chip is exposed, which may be damaged during the test or packaging to the interposer.
- In view of the aforementioned difficulties, it is an object of the invention to ensure reduction of the semiconductor device thickness, and to suppress the damage applied to the first semiconductor chip.
- According to an aspect of the present invention, there is provided a semiconductor device including a first semiconductor chip, a second semiconductor chip flip-chip bonded to the first semiconductor chip, a resin portion for sealing the first semiconductor chip and the second semiconductor chip such that a lower surface of the first semiconductor chip and an upper surface of the second semiconductor chip are exposed and a side surface of the first semiconductor chip is covered, and a post electrode which pierces the resin portion and is connected to the first semiconductor chip. In the aforementioned structure, the side surface of the first semiconductor chip is covered with the resin portion to suppress the damage applied to the first semiconductor chip. This also makes it possible to reduce the semiconductor device thickness.
- According to another aspect of the present invention, there is provided a manufacturing method of a semiconductor device including the steps of forming a post electrode on a semiconductor wafer, flip-chip bonding a second semiconductor chip onto the semiconductor wafer, forming a groove in an upper surface of the semiconductor wafer, forming a resin portion on the semiconductor wafer for sealing to cover the post electrode and the second semiconductor chip, performing one of grinding and polishing of the resin portion and the second semiconductor chip such that an upper surface of the post electrode and an upper surface of the second semiconductor chip are exposed, performing one of grinding and polishing of a lower surface of the semiconductor wafer such that the semiconductor wafer is thinner than a depth of the groove, so as to form a first semiconductor chip from the semiconductor wafer, and cutting the resin portion along the groove to separate the first semiconductor chip. In the method according to the invention, grinding or polishing is performed in the state where the resin portion and the second semiconductor chip are flip-chip bonded onto the semiconductor wafer so as to reduce the thickness of the second semiconductor chip. As the second semiconductor chip is protected by the resin portion, the second semiconductor chip may be prevented from being cracked. The semiconductor wafer is subjected to the grinding or polishing to reduce its thickness to be smaller than the depth of the groove. The resin portion is cut along the groove to separate the first semiconductor chip. This makes it possible to cover the side surface of the first semiconductor chip with the resin portion.
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FIGS. 1A to 1C are sectional views showing manufacturing process steps of a semiconductor device according to a first embodiment (type 1). -
FIGS. 2A to 2C are sectional views showing manufacturing process steps of a semiconductor device according to the first embodiment (type 2). -
FIG. 3 is a sectional view of the semiconductor device according to the first embodiment. -
FIG. 4 is a sectional view of a semiconductor device according to a second embodiment. -
FIGS. 5A to 5C arc sectional views showing manufacturing process steps of a semiconductor device according to a third embodiment. -
FIG. 6 is a sectional view of the semiconductor device according to the third embodiment. -
FIG. 7 is a view showing the semiconductor according to the third embodiment in a packaged state. -
FIG. 8 is a sectional view of a semiconductor device according to a fourth embodiment. -
FIG. 9 is a sectional view of a semiconductor device according to a fifth embodiment. -
FIGS. 10A to 10C are sectional views showing manufacturing process steps of a semiconductor device according to a sixth embodiment. -
FIG. 11 is a sectional view of a semiconductor device according to a sixth embodiment. -
FIG. 12 is a sectional view of a semiconductor device according to a seventh embodiment. -
FIG. 13 is a sectional view of another semiconductor device according to the seventh embodiment. -
FIG. 14 is a sectional view showing a semiconductor device according to an eighth embodiment. -
FIG. 15 is a sectional view of another semiconductor device according to the eighth embodiment. - Embodiments according to the invention will be described referring to the drawings.
- The method for manufacturing a semiconductor device according to a first embodiment will be described referring to
FIGS. 1A to 2C . Referring toFIG. 1A , apost electrode 40 formed of for example, an Au stud bump is formed on apad 14 on the upper surface of asilicon semiconductor wafer 11 having a circuit formed on its upper surface. Abump 16 formed of Au, Cu (copper) or solder is formed below apad 22 on the lower surface of asecond semiconductor chip 20 formed of silicon and having a circuit on its lower surface. An interconnection (not shown) allows the electric coupling between thepost electrodes 40, betweenpads 14, and between thepost electrode 40 and thepad 14. Thesecond semiconductor chip 20 is flip-chip bonded onto thesemiconductor wafer 11 with thebump 16. The thickness of the thus bonded semiconductor wafer 11 and thesecond semiconductor chip 20 is approximately 750 μm. - Referring to
FIG. 1B , agroove 18 with its width w1 set to 60 μm and its depth t1 set to 60 μm is formed in thesemiconductor wafer 11 by performing half dicing of thesemiconductor wafer 11 using a dicing device. - Referring to
FIG. 1C , aresin portion 30 is formed to cover and seal thepost electrode 40 and thesecond semiconductor chip 20, and to fill thegroove 18. Theresin portion 30 may be formed by spin coating and heating the liquid thermosetting epoxy resin. Theresin portion 30 may be formed with the mold. The spin coating allows theresin portion 30 to be formed even in the narrow gap between thefirst semiconductor chip 10 and thesecond semiconductor chip 20. It is preferable to use a liquid resin containing no filler for the spin coating. - Referring to
FIG. 2A , theresin portion 30 and thesecond semiconductor chip 20 are ground such that the upper surfaces of both thepost electrode 40 and thesecond semiconductor chip 20 are exposed. Theresin portion 30 and thesecond semiconductor chip 20 are ground until the thickness of thesecond semiconductor chip 20 becomes 50 μm, and the thickness of theresin portion 30 becomes 80 μm, for example. - Referring to
FIG. 2B , the lower surface of thesemiconductor wafer 11 is subjected to the grinding to reduce its thickness to be smaller than the depth t1 of thegroove 18, for example, to 50 μm. Thesemiconductor wafer 11 may be separated into thefirst semiconductor chips 10. - Referring to
FIG. 2C , theresin portion 30 is cut along thegroove 18 to separate thesecond semiconductor chips 20 using the dicing device. The blade used for cutting has the width narrower than that of the blade used for the half dicing as shown inFIG. 1B . This makes it possible to cut theresin portion 30 with the cutting width smaller than the width w1 of thegroove 18. If the width t1 of the half dicing is set to 60 μm, and the cutting width is set to 40 μm, theresin portion 30 is allowed to remain on the side surface of thefirst semiconductor chip 10 by the width of approximately 10 μm. -
FIG. 3 is a sectional view of asemiconductor device 100 according to the first embodiment. Referring toFIG. 3 , thesemiconductor device 100 has a CoC structure formed by flip-chip bonding the second semiconductor chip onto thefirst semiconductor chip 10. Theresin portion 30 seals thefirst semiconductor chip 10 and thesecond semiconductor chip 20 such that the lower surface of thefirst semiconductor chip 10 and the upper surface of thesecond semiconductor chip 20 are exposed, and the side surfaces S10 of thefirst semiconductor chip 10 are covered. Thepost electrode 40 pierces theresin portion 30 to be connected to thefirst semiconductor chip 10. - In the case where the
second semiconductor chip 20 is flip-chip bonded onto thefirst semiconductor chip 10, it is difficult to reduce the thickness of thesecond semiconductor chip 20 to less than 100 um owing to handling difficulty. In the manufacturing method of thesemiconductor device 100 according to the first embodiment, theresin portion 30 and thesecond semiconductor chip 20 which are flip-chip bonded onto thesemiconductor wafer 11 are ground as shown inFIG. 2A so as to reduce the thickness of thesecond semiconductor chip 20 to less than 100 μm, for example. As thesecond semiconductor chip 20 is protected by theresin portion 30 during the grinding, thesecond semiconductor chip 20 is prevented from being cracked. As shown inFIG. 1B , thegroove 18 is formed in thesemiconductor wafer 11, and as shown inFIG. 2B , thesemiconductor wafer 11 is subjected to the grinding such that its thickness is smaller than the depth t1 of thegroove 18. Theresin portion 30 is cut along thegroove 18 to separate thefirst semiconductor chips 10. As the side surface S10 of thefirst semiconductor chip 10 is covered with theresin portion 30 as shown inFIG. 3 , thefirst semiconductor chip 10 may be prevented from being damaged during the test or packaging of thesemiconductor device 100, that is, handling thereof. Theresin portion 30 is ground such that the upper surface of thepost electrode 40 is exposed as shown inFIG. 2A . In this way, thepost electrode 40 pierces theresin portion 30 as shown inFIG. 3 to be electrically coupled with thefirst semiconductor chip 10 from the upper surface of theresin portion 30. - Referring to
FIG. 2C , thefirst semiconductor chips 10 may be separated while reducing the thickness of thesemiconductor device 100, regardless of whether theresin portion 30 remains on the side surface S10 of thefirst semiconductor chip 10. However, it is preferable to cut thesemiconductor wafer 11 such that theresin portion 30 remains on the side surface S10 of thefirst semiconductor chip 10. This makes it possible to suppress the damage applied to thefirst semiconductor chip 10. - The
resin portion 30 may be formed to partially coat the side surface S10 of thefirst semiconductor chip 10. Preferably, however, theresin portion 30 is formed to entirely coat the side surface S10 of thefirst semiconductor chip 10 as shown inFIG. 3 . This makes it possible to further suppress the damage applied to thefirst semiconductor chip 10. - Preferably, the
post electrode 40 is electrically coupled not only with thefirst semiconductor chip 10 but also with thesecond semiconductor chip 20 via the interconnection (not shown) of thefirst semiconductor chip 10. This makes it possible to connect the first and thesecond semiconductor chips post electrode 40. - Preferably, the
post electrode 40 is formed of the stud bump so as to be easily produced. The number of threads of the stud bump may be set to an appropriate value depending on a preferable height of thepost electrode 40. - A second embodiment is an example for packaging the
semiconductor device 100 on the interposer. Referring toFIG. 4 , thesemiconductor device 100 according to the first embodiment is mounted on an insulated interposer 50 (mount portion) formed of the glass epoxy and the like through adie adhesive material 64 such as an adhesive agent. The upper surface of thepost electrode 40 is connected to anelectrode 54 of theinterposer 50 via abonding wire 62. Thesemiconductor device 100 is sealed with a sealingportion 60 formed of a resin material. Asolder ball 58 is formed on the lower surface of theinterposer 50 via anelectrode 52. Theelectrodes interposer 50. The solder resist 56 is applied onto the lower surface of theinterposer 50 so as not to be in contact with thesolder ball 58. Thesemiconductor device 100 has the same structure as that of the first embodiment shown inFIG. 3 , and the explanation thereof, thus will be omitted. - The second embodiment allows the
semiconductor device 100 according to the first embodiment to be packaged onto theinterposer 50. Thesemiconductor device 100 has thepost electrode 40 exposed to the upper surface of theresin portion 30 as shown inFIG. 3 . This makes it possible to implement the test prior to packaging of thesemiconductor device 100 as shown inFIG. 4 , thus improving the yield of the semiconductor device after packaging. - The embodiment allows the thickness of the
semiconductor device 100 to be reduced to 130 μm, thus thinning the semiconductor device according to the second embodiment. - A third embodiment is an example for forming the post electrode through plating. Referring to
FIGS. 5A to 5C , the method for manufacturing the semiconductor device according to the third embodiment will be described. Referring toFIG. 5A , aCu layer 42 formed of Cu is formed on apad 14 on thesemiconductor wafer 11 through electrolytic plating. The other structure of the embodiment is the same as that of the first embodiment shown inFIG. 1A , and the explanation thereof, thus will be omitted. - Referring to
FIG. 5B , the same manufacturing steps as those of the first embodiment shown inFIGS. 1B and 1C are performed. Theresin portion 30 and thesecond semiconductor chip 20 are ground until the upper surface of theCu layer 42 is exposed. Referring toFIG. 5C , aNi layer 44 formed of Ni (nickel) is formed on theCu layer 42 through nonelectrolytic plating, thus forming apost electrode 46 formed of theCu layer 42 and theNi layer 44. The manufacturing steps of the first embodiment shown inFIGS. 2A to 2C are performed to complete production of the semiconductor device according to the third embodiment. -
FIG. 6 is a sectional view of asemiconductor device 100 a according to the third embodiment, which has thepost electrode 46 formed of the Cu layer 42 (electrode layer) and the Ni layer 44 (barrier layer). The other structure is the same as that of the first embodiment shown inFIG. 3 , and the explanation thereof, thus will be omitted. TheNi layer 44 functions as the barrier layer when the solder ball is formed on thepost electrode 46. TheNi layer 44 does not have to be provided, but it is preferable to provide the Ni layer as the barrier layer. TheCu layer 42 may be the electrode layer using a metal other than Cu. However, it is preferable to use a material with a small resistivity. Preferably, the barrier layer exhibits high barrier performance. The thickness of theNi layer 44 may be selected in the range where the barrier function is performed. -
FIG. 7 is an example for packaging thesemiconductor device 100 a according to the third embodiment onto theinterposer 50. The structure of the embodiment is the same as that of the second embodiment shown inFIG. 4 except that thesemiconductor device 100 a is packaged, and the explanation thereof, thus will be omitted. - In the first and the second embodiments, the stud bump is used as the
post electrode 40 which may be formed without using the plating apparatus for Cu plating as in the third embodiment. Meanwhile, in the third embodiment, thepost electrode 46 may be formed through the plating, and does not have to be individually produced unlike the stud bump used in the first and the second embodiments. Accordingly, the use of the third embodiment is advantageous for manufacturing a large amount of the semiconductor devices. It is difficult to form thetall post electrode 40 with the stud bump. The use of the third embodiment is advantageous to form the relativelytall post electrode 40. Thepost electrode resin portion 30 to be electrically coupled with thefirst semiconductor chip 10 from the upper surface of theresin portion 30. - A fourth embodiment is an example for packaging
plural semiconductor devices 100 on theinterposer 50. Referring toFIG. 8 , twostacked semiconductor devices 100 according to the first embodiment are packaged on the interposer 50 (mount portion) via dieadhesive materials FIG. 4 , and the explanation thereof, thus will be omitted. The fourth embodiment is capable of reducing the thickness of thesemiconductor device 100. In this way, theplural semiconductor devices 100 may be packaged onto theinterposer 50. - A fifth embodiment is an example for packaging the
semiconductor device 100 and the plural semiconductor chips onto theinterposer 50. Referring toFIG. 9 ,plural semiconductor chips 70 which are stacked are packaged onto the interposer (mount portion) 50 with thedie adhesive material 72 as the adhesive agent. Thesemiconductor device 100 according to the first embodiment is packaged on the stackedsemiconductor chip 70 via thedie adhesive material 72. Thebonding wire 62 is connected to apad 74 formed on the upper surfaces of thepost electrode 40 of thesemiconductor device 100 and thesemiconductor chip 70. The use of thebonding wire 62 electrically couples thesemiconductor device 100, theinterposer 50, and the semiconductor chips 70 with one another. The other structure is the same as that of the fourth embodiment shown inFIG. 8 , and the explanation thereof, thus will be omitted. In the fifth embodiment, one ormore semiconductor chips 70 may be stacked and packaged onto theinterposer 50 together with thesemiconductor device 100. - The fourth and the fifth embodiments show the example for packaging the
semiconductor device 100 according to the first embodiment onto theinterposer 50. Those embodiments allow thesemiconductor device 100 a according to the third embodiment to be packaged onto theinterposer 50. - A sixth embodiment is an example with respect to the first semiconductor chip having the through electrode. Referring to
FIGS. 10A to 10C , the method for manufacturing the semiconductor device according to the sixth embodiment will be described. Referring toFIG. 10A , an embeddedelectrode 80 made of Cu is formed to be embedded in thesemiconductor wafer 11. The thickness of the embeddedelectrode 80, that is, t3 is substantially the same as the depth of thegroove 18, which may be set to 60 μm, for example. Thepost electrode 40 is formed on the embeddedelectrode 80. The other structure is the same as that of the first embodiment shown inFIG. 1A , and the explanation thereof, thus will be omitted. - Referring to
FIG. 10B , the same manufacturing steps as those of the first embodiment shown inFIGS. 1B to 2B are performed. Theresin portion 30 and thesecond semiconductor chip 20 are ground until the upper surface of thepost electrode 40 is exposed. Referring toFIG. 10C , the lower surface of thesemiconductor wafer 11 is ground such that its depth becomes less than that of the embeddedelectrode 80 and thegroove 18. This may divide thesemiconductor wafer 11 to form thefirst semiconductor chip 10 as well as to form the throughelectrode 81 which pierces from the embeddedelectrode 80 to thefirst semiconductor chip 10. Thereafter, the manufacturing process of the first embodiment shown inFIG. 2C is performed to complete formation of thesemiconductor device 10 according to the sixth embodiment. - Referring to
FIG. 11 , asemiconductor device 100 b according to the sixth embodiment pierces thefirst semiconductor chip 10, and has the throughelectrode 81 connected to thepost electrode 40. The other structure is the same as that of the first embodiment shown inFIG. 3 , and the explanation thereof, thus will be omitted. In the sixth embodiment, the use of the throughelectrode 81 which pierces thefirst semiconductor chip 10 allows thefirst semiconductor chip 10 to be electrically coupled with thesecond semiconductor chip 20 from the upper and the lower surfaces of thesemiconductor device 100 b. The sixth embodiment shows the example for using the stud bump employed in the first embodiment as thepost electrode 40. However, theCu layer 42 formed through the plating process in the same manner as in the third embodiment may be used. - A seventh embodiment is an example for stacking the
semiconductor devices 100 b to be packaged onto theinterposer 50. Referring toFIG. 12 , theplural semiconductor devices 100 b are flip-chip bonded to be stacked via bumps 76. The thus stackedplural semiconductor devices 100 b are further flip-chip bonded onto the interposer 50 (mount portion). - Referring to
FIG. 13 ,plural semiconductor devices 100 b are flip-chip bonded via thebumps 76. The stackedplural semiconductor devices 100 b are mounted on theinterposer 50 via thedie adhesive material 72, and electrically coupled with theinterposer 50 with thebonding wire 62. The other structure is the same as that of the second embodiment shown inFIG. 4 , and the explanation thereof, thus will be omitted. - The
semiconductor device 100 b according to the sixth embodiment electrically couples the first and thesecond semiconductor chips semiconductor devices 100 b through the flip chip bonding. - An eighth embodiment is an example for stacking the
semiconductor device 100 b and plural semiconductor chips to be packaged onto theinterposer 50. Referring toFIG. 14 ,plural semiconductor chips 70 a are flip-chip bonded to be stacked on thesemiconductor device 100 b via thebumps 76. Thesemiconductor chip 70 a includes a throughelectrode 78 which pierces the semiconductor chip. Thebump 76 is formed to be in contact with the throughelectrode 78. Thesemiconductor device 100 b is flip-chip bonded onto the interposer 50 (mount portion). - Referring to
FIG. 15 , theplural semiconductor chips 70 a are flip-chip bonded via thebumps 76. Thesemiconductor device 100 b is flip-chip bonded onto the thus stackedplural semiconductor chips 70 a. The plural stackedsemiconductor chips 70 a are mounted on theinterposer 50 via thedie adhesive material 72. Thesemiconductor device 100 b and theinterposer 50 are electrically coupled with thebonding wire 62. The other structure is the same as that of the second embodiment shown inFIG. 4 , and the explanation thereof, thus, will be omitted. - The
semiconductor device 100 b according to the sixth embodiment allows thefirst semiconductor chip 10 and thesecond semiconductor chip 20 to be electrically coupled from its upper and lower surfaces. Thus, the eighth embodiment makes it possible to flip-chip bond thesemiconductor device 100 b onto theplural semiconductor chips 70 a. - In the aforementioned embodiments, the single
second semiconductor chip 20 is flip-chip bonded onto thefirst semiconductor chip 10. However, pluralsecond semiconductor chips 20 may be flip-chip bonded onto thefirst semiconductor chip 10. In the embodiments, theresin portion 30 and the sealingportion 60 formed of epoxy resin are employed. However, they may be formed of polyimide resin, silicon resin and the like. - In the aforementioned embodiments, the
resin portion 30, and either thesecond semiconductor chip 20 or thesemiconductor wafer 11 are ground. However, they may be subjected to the polishing instead of the grinding. Theinterposer 50 has been described as the mount portion. However, the mount portion may be formed in an arbitrary form so long as it has the function of packaging thesemiconductor device 100. - Finally, several aspects of the present invention are summarized as follows.
- According to an aspect of the present invention, there is provided a semiconductor device including a first semiconductor chip, a second semiconductor chip flip-chip bonded to the first semiconductor chip, a resin portion for sealing the first semiconductor chip and the second semiconductor chip such that a lower surface of the first semiconductor chip and an upper surface of the second semiconductor chip are exposed and a side surface of the first semiconductor chip is covered, and a post electrode which pierces the resin portion and is connected to the first semiconductor chip. In the aforementioned structure, the side surface of the first semiconductor chip is covered with the resin portion to suppress the damage applied to the first semiconductor chip. This also makes it possible to reduce the semiconductor device thickness.
- In the aforementioned structure, the resin portion may entirely cover the side surface of the first semiconductor chip. The structure is capable of further suppressing the damage applied to the first semiconductor chip.
- In the aforementioned structure, the post electrode may be formed of a stud bump. In the structure, the post electrode may be structured to contain copper.
- The aforementioned structure may further include a through electrode which pierces the first semiconductor chip and is connected to the post electrode. The structure allows the electric coupling with the first semiconductor chip from the upper and the lower surfaces.
- In the aforementioned structure, the post electrode may be electrically coupled with the first semiconductor chip and the second semiconductor chip. In the structure, the post electrode exposed from the resin portion is used to connect the first and the second semiconductor chips.
- The aforementioned structure may further include a mount portion to which the first semiconductor chip is packaged. The structure is capable of suppressing the damage applied to the first semiconductor chip when it is packaged onto the mount portion.
- According to another aspect of the present invention, there is provided a manufacturing method of a semiconductor device including the steps of forming a post electrode on a semiconductor wafer, flip-chip bonding a second semiconductor chip onto the semiconductor wafer, forming a groove in an upper surface of the semiconductor wafer, forming a resin portion on the semiconductor wafer for sealing to cover the post electrode and the second semiconductor chip, performing one of grinding and polishing of the resin portion and the second semiconductor chip such that an upper surface of the post electrode and an upper surface of the second semiconductor chip are exposed, performing one of grinding and polishing of a lower surface of the semiconductor wafer such that the semiconductor wafer is thinner than a depth of the groove, so as to form a first semiconductor chip from the semiconductor wafer, and cutting the resin portion along the groove to separate the first semiconductor chip. In the method according to the invention, grinding or polishing is performed in the state where the resin portion and the second semiconductor chip are flip-chip bonded onto the semiconductor wafer so as to reduce the thickness of the second semiconductor chip. As the second semiconductor chip is protected by the resin portion, the second semiconductor chip may be prevented from being cracked. The semiconductor wafer is subjected to the grinding or polishing to reduce its thickness to be smaller than the depth of the groove. The resin portion is cut along the groove to separate the first semiconductor chip. This makes it possible to cover the side surface of the first semiconductor chip with the resin portion.
- In the aforementioned process, the step for separating the first semiconductor chip may include a step for cutting the semiconductor wafer such that the resin portion remains on a side surface of the first semiconductor chip. The process suppresses the damage applied to the first semiconductor chip.
- In the aforementioned process, the step for forming the post electrode may be performed using a stud bump or an electrolytic plating process.
- The aforementioned process may include a step for forming an embedded electrode which is embedded in the semiconductor wafer. In the step for forming the post electrode, the post electrode may be formed on the embedded electrode. In the step for performing one of grinding and polishing of the lower surface of the semiconductor wafer, the lower surface of the semiconductor wafer may be subjected to one of the grinding and polishing such that the semiconductor wafer is thinner than a depth of the embedded electrode. The process allows the connection with the first semiconductor chip from the upper and the lower surfaces.
- The aforementioned process may further include a step for packaging the first semiconductor chip onto a mount portion. The process is capable of reducing the thickness of the semiconductor device.
- While the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to those specific embodiments, and within the spirit and scope of the present invention, various modifications and alterations can be made.
Claims (14)
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US13/921,956 US8586412B1 (en) | 2007-03-19 | 2013-06-19 | Semiconductor device and method for manufacturing thereof |
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Also Published As
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JP2008235401A (en) | 2008-10-02 |
US20080230898A1 (en) | 2008-09-25 |
US8492890B2 (en) | 2013-07-23 |
US8586412B1 (en) | 2013-11-19 |
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