KR100767193B1 - Line flip chip package and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a line flip chip package and a method of manufacturing the same. The technical problem to be solved is to implement a flip chip at low cost by using a wire terminal without a bumping process, to improve the connection reliability between the semiconductor die and the substrate, A line flip chip package and a method of manufacturing the same are easily applicable to a semiconductor die and a substrate having a large amount of bond pads in fine pitch.

To this end, the gist of the solution according to the present invention is a semiconductor die having a plurality of bond pads formed thereon, and a substrate having a plurality of wiring patterns formed on the surface thereof, the substrate having a plurality of wiring patterns formed thereon, and bond pads and subs of the semiconductor die formed thereon. Disclosed are a line flip chip package consisting of a plurality of wire terminals interconnecting a straight wiring pattern and formed of substantially "S", and a spacer formed between the semiconductor die and the substrate to protect the wire terminals, and a method of manufacturing the same.

Flip Chip, Wire Terminals, Ultra Fine Pitch, Spacer, Substrate

Description

LINE FLIP CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

1A is a cross-sectional view showing a line flip chip package according to an embodiment of the present invention, FIG. 1B is a cross-sectional view showing a line flip chip package according to another embodiment of the present invention, and FIG. 1C is a line according to the present invention. A partial plan view showing a wire terminal formed on a semiconductor die in a flip chip package.

2A is a cross-sectional view illustrating a line flip chip package according to another exemplary embodiment of the present invention, and FIG. 2B is a partial plan view illustrating a wire terminal formed on a semiconductor die.

3A is a cross-sectional view illustrating a line flip chip package according to another exemplary embodiment of the present invention, and FIG. 3B is a partial plan view illustrating a wire terminal formed on a semiconductor die.

4 is a flowchart illustrating a method of manufacturing a line flip chip package according to the present invention.

5A to 5I are views sequentially illustrating a method of manufacturing a line flip chip package according to the present invention.

5A is a perspective view illustrating a step of forming a spacer on a wafer;

5B is a perspective view showing a state in which individual semiconductor dies are sawed from a wafer;

5C is a perspective view illustrating a state in which a semiconductor die is mounted on a jig;

5D is a perspective view illustrating a state in which a wire terminal is formed on a semiconductor die by using wire bonding equipment;

5E is a cross-sectional view showing a state of forming an adhesive on a spacer;

5F and 5G are cross-sectional views illustrating a state where the semiconductor die is picked and placed on the substrate;

5H is a sectional view showing a reflow state;

Figure 5i is a cross-sectional view showing the completed state after the sealing operation and the package cutting operation.

<Description of Symbols for Main Parts of Drawings>

100a, 100b, 200, 300; Line flip chip package according to the present invention

110; semiconductor die 110a; Front page

110b; Second surface 110c; side

112; Bond pads 120; Substate

121; Insulating layer 121a; Front page

121b; Second page 121c; side

122; Wiring pattern 123 for terminals; Mounting wiring pattern

124; Conductive via holes 125,126; Solder mask

130; Wire terminal 131; Terminal 1

132; Second terminal portion 133; Terminal 3 part

135; Solder pasted 140; Spacer

142; Adhesive 150; Encapsulant

150a; Upper surface 150b; side

160; Under fill

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line flip chip package and a method of manufacturing the same, and more particularly, to implement flip chip at low cost by using a wire terminal without a bumping process, to improve connection reliability between a semiconductor die and a substrate, and to improve ultra fine pitch. And a line flip chip package which can be easily applied to a semiconductor die in which a large amount of bond pads are formed, and a method of manufacturing the same.

In general, a flip chip package refers to a form in which conductive bumps, such as solder bumps or Au stud bumps, are formed on the bond pads of a semiconductor die, and then inverted and electrically connected to the substrate. do. Of course, a bumping process of forming a plurality of bumps using gold (Au), solder (Sn / Pb), nickel / copper (Ni / Cu), or the like is typically performed on the bond pad of the semiconductor die.

This bumping process is performed by a wide variety of methods, typically electrolytic plating and electroless plating. In addition, if the material used for bumping is gold, there are gold electroplating and gold stud bumping methods. In the case of solder, vacuum deposition, electrolytic plating, printing, and robotic ball placement methods are used. have.

However, since the conventional flip chip package uses a bumping method, a large amount of money must be purchased to purchase a separate bumping device, and a plurality of subsidiary materials are used for bumping, thereby increasing the cost of the package and manufacturing a package. There is a problem that the failure rate is high.

In addition, bumps formed in the semiconductor die have a predetermined deviation in their thickness, so that certain bumps are not electrically connected or weakly connected to the substrate. That is, there is a problem that the electrical connection reliability between the semiconductor die and the substrate is low.

In addition, the bumps formed on the semiconductor die are thicker and thicker than the conductive wires, so that the pitch between the bumps should be relatively far, and thus there is a limit on the number of bond pads that can be formed on the semiconductor die, and also in recent years. There is a problem that is difficult to apply to a package having an ultra fine pitch.

In addition, a conventional flip chip package is cracked or damaged by a plastic stress caused by a difference in thermal expansion coefficient between a semiconductor die and a substrate when mounted in a manufacturing process or an external device and exposed to a high temperature environment. there is a problem. Of course, this bump cracking or damage can cause secondary problems in which the semiconductor die malfunctions or fails to perform proper electrical function.

SUMMARY OF THE INVENTION The present invention has been made to overcome the above-mentioned problems, and an object of the present invention is to provide a line flip chip package and a method of manufacturing the same, which can implement a flip chip at low cost using a wire terminal without a bumping process.

Another object of the present invention is to provide a line flip chip package and a method for manufacturing the same, which can improve the connection reliability between the semiconductor die and the substrate by implementing the connection between the semiconductor die and the substrate with a plastic elastic wire terminal.

Another object of the present invention is to implement a connection between the semiconductor die and the substrate with a small diameter wire terminal, a line flip chip package that can be easily applied to a semiconductor die having a recent ultra fine pitch and formed with a large amount of bond pads. And a method for producing the same.

It is still another object of the present invention to provide a line flip chip package and a method of manufacturing the same, by forming a spacer having a thickness smaller than that of a bump on the surface of a semiconductor die.

In order to achieve the above object, a line flip chip package according to the present invention includes a semiconductor die having a plurality of bond pads formed thereon, and a substrate having a plurality of wiring patterns formed on a surface thereof, the substrate having a plurality of wiring patterns formed thereon; A plurality of wire terminals may be included to interconnect the bond pads of the semiconductor die and the respective wiring patterns of the substrate.

Here, the wire terminal may be connected to the wiring pattern of the substrate by solder paste.

In addition, a plurality of insulating spacers may be further interposed between the semiconductor die and the substrate.

In addition, one side of the insulating spacer may be directly bonded to the surface of the semiconductor die, and the other side may be attached to the substrate through an adhesive.

In addition, the insulating spacer may have a thickness of 100 μm or more, preferably 100 to 150 μm.

In addition, the wire terminal may have a minimum pitch of 100 ~ 300㎛.

In addition, the wire terminal may be bent in the "S" shape.

The wire terminal may include a first terminal portion connected to a bond pad of the semiconductor die, a second terminal portion bent by a predetermined angle from the first terminal portion, a predetermined length extending, and a predetermined angle bending from the second terminal portion. It may include a third terminal portion connected to the wiring pattern of the substrate.

The wire terminal may have a bending angle of 5 ° to 85 ° between the first terminal part and the second terminal part.

In addition, the second terminal portion of the wire terminal may be formed having at least two kinds of length.

In addition, the wire terminal may be a fan-in type that is bent toward the inner side of the semiconductor die.

In addition, the wire terminal may be a fan-out type bent toward the outside of the semiconductor die.

In addition, the wire terminal may be formed by mixing a fan-in type bent toward the inside of the semiconductor die and a fan-out type bent toward the outside of the semiconductor die. have.

In addition, the conductive wire may be formed of any one selected from gold wire, aluminum wire or copper wire.

In addition, the semiconductor die and the plurality of wire terminals may be encapsulated with an encapsulant.

In addition, an opposite surface of the semiconductor die on which the bond pad is formed may be exposed to the outside of the encapsulant.

In addition, an underfill may be further injected between the semiconductor die and the substrate to protect the plurality of wire terminals from an external environment.

In addition, the substrate includes a plate-shaped insulating layer, a terminal connection wiring pattern formed on one surface of the insulating layer and connected to the wire terminal, and a mounting wiring formed on the other surface of the insulating layer and mounted on an external device. The pattern may include a conductive via that interconnects the terminal connection wiring pattern and the mounting wiring pattern.

In addition, the substrate has a solder mask coated on one surface and the other surface, respectively, and the terminal connection wiring pattern and the mounting wiring pattern may be exposed to the outside through the solder mask.

In addition, the method for manufacturing a line flip chip package according to the present invention includes a spacer forming step of forming a plurality of spacers having a predetermined thickness in each semiconductor die of a wafer, sawing each semiconductor die from the wafer, and A die fixing step of fixing the die to a jig, a wire terminal forming step of forming a wire terminal having a predetermined length on a bond pad of the fixed semiconductor die, an adhesive forming step of forming an adhesive on a spacer of the semiconductor die, and Pick and place a semiconductor die to pick and place the wire terminal on the wiring pattern of the substrate, and a reflow step of providing a high temperature so that the wire terminal of the semiconductor die is completely connected to the wiring pattern of the substrate. And the semiconductor die, a plurality of spaces In an exemplary embodiment, the encapsulating step may include encapsulating a plurality of wire terminals with an encapsulant.

In addition, the spacer forming step may form the insulating solution by any one of a screen printing method or a jet dispensing method.

In addition, the wire terminal forming step may be formed in the "S" shape using a wire bonding equipment.

In addition, the die pick and place step may be performed after the solder paste is formed in advance on the wiring pattern of the substrate.

In addition, the solder paste may be formed on the wiring pattern of the substrate by any one of a screen printing method and a pin dotting method.

In addition, an underfill may be injected before the encapsulation step to protect the wire terminal between the semiconductor die and the substrate.

As described above, the line flip chip package and the method of manufacturing the same according to the present invention form a wire terminal instead of a bump using a conventional wire bonding equipment without an expensive bumping process, and connect it to the substrate in a flip chip method, thereby providing a low cost. This results in a line flip chip package.

In addition, the line flip chip package and the method of manufacturing the same according to the present invention electrically connect the semiconductor die and the substrate to each other using wire terminals and solder paste, thereby further improving the electrical connection reliability and stability of the semiconductor die and the substrate. That is, conventionally, due to the thickness variation in the bumps, the specific bumps may not be electrically connected to the substrate, and the bumps may be cracked or separated from the substrates due to the difference in thermal expansion coefficient. By using a wire terminal which is present, and also by connecting the wire terminal electrically to the substrate through solder paste, connection reliability and stability are further improved.

In addition, the line flip chip package and the manufacturing method thereof according to the present invention can easily accommodate a semiconductor die having a recent ultra fine pitch and formed with a large amount of bond pads by electrically connecting the semiconductor die and the substrate with a small diameter wire terminal. You can do it.

In addition, the line flip chip package and the method of manufacturing the same according to the present invention can further reduce the thickness of the package as a whole by interposing a spacer having a smaller thickness than the conventional bump between the semiconductor die and the substrate.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art may easily implement the present invention.

1A is a cross-sectional view showing a line flip chip package according to an embodiment of the present invention, FIG. 1B is a cross-sectional view showing a line flip chip package according to another embodiment of the present invention, and FIG. 1C is a line according to the present invention. A partial plan view showing a wire terminal formed on a semiconductor die in a flip chip package.

As shown in FIG. 1A, the line flip chip package 100a according to the present invention includes a semiconductor die 110, a substrate 120 positioned below the semiconductor die 110, and the semiconductor die 110. A plurality of wire terminals 130 electrically connected to the substrate 120 in a flip chip form, and a plurality of spacers 140 stably fixing the semiconductor die 110 on the substrate 120. And an encapsulant 150 encapsulating the semiconductor die 110, the plurality of wire terminals 130, and the plurality of spacers 140 to protect them from the external environment.

First, the semiconductor die 110 has a substantially flat first surface 110a and a substantially flat second surface 110b as an opposite surface thereof. Of course, the side surface 110c which is substantially perpendicular to the first surface 110a and the second surface 110b of the semiconductor die 110 is formed. In addition, a plurality of bond pads 112 (eg, aluminum pads) are formed on the inner circumference of the first surface 110a of the semiconductor die 110, and the bond pads 112 may have a substrate to be described below. Head 120. In addition, although not shown, a semiconductor integrated circuit for performing a predetermined electrical function is formed on the first surface 110a of the semiconductor die 110.

The substrate 120 is located toward the first surface 110a of the semiconductor die 110. That is, the substrate 120 is formed on the bond pad 112 side of the semiconductor die 110. In other words, the semiconductor die 110 is seated on the substrate 120 in a substantially flip chip form. The substrate 120 includes an insulating layer 121 having an approximately flat first surface 121a and an approximately flat second surface 121b opposite thereto. Of course, the insulating layer 121 has side surfaces 121c formed at edges of the first surface 121a and the second surface 121b in a direction substantially perpendicular thereto. In addition, the side surface 121c of the insulating layer 121 is formed in an outer region than the side surface 110c of the semiconductor die 110. In other words, the width of the substrate 120 is slightly larger than the width of the semiconductor die 110. The insulating layer 121 may be formed of any one selected from pre-preg, thermosetting resin, or equivalents thereof, but the material is not limited thereto. Subsequently, a mounting wiring pattern 123 is later formed on the first surface 121a of the insulating layer 121, and is mounted on the second surface 121b of the insulating layer 121. A wiring pattern 122 for a terminal to which the wire terminal 130 to be described below is connected is formed. Of course, the mounting wiring pattern 123 and the terminal wiring pattern 122 are electrically connected to each other by the conductive via hole 124. In addition, the mounting wiring pattern 123 and the terminal wiring pattern 122 may be formed of copper (Cu) or an equivalent thereof, but the material is not limited thereto. In addition, a solder mask 126 is coated on the first surface 121a of the insulating layer 121, and the mounting wiring pattern 123 is exposed to the outside through the solder mask 126. In addition, a solder mask 125 is also coated on the second surface 121b of the insulating layer 121, and the terminal wiring pattern 122 is exposed to the outside through the solder mask 125. Here, the solder masks 125 and 126 may be formed of any one selected from polyimide or equivalents thereof, but the material is not limited thereto.

The plurality of wire terminals 130 electrically connects the bond pad 112 of the semiconductor die 110 and the terminal wiring pattern 122 of the substrate 120 with each other. Here, the wire terminal 130 may be formed in an approximately "S" shape to electrically connect the bond pad 112 and the terminal wiring pattern 122 to elastically, but the present invention is limited to this form. It is not. More specifically, the wire terminal 130 is bent at a predetermined angle from the first terminal portion 131 connected to the bond pad 112 of the semiconductor die 110 in a direction substantially perpendicular to the first terminal portion 131. The third terminal portion 132 extending a predetermined length and the third terminal portion bent at a predetermined angle from the second terminal portion 132 and connected in a substantially perpendicular direction to the terminal wiring pattern 122 of the substrate 120. (133), but the present invention is not necessarily limited to this form. Here, the bending angle (or shoulder angle) between the first terminal portion 131 and the second terminal portion 132 may be a semiconductor die even in a high temperature environment generated during the package manufacturing process or the operation of the semiconductor die 110. It may be formed to approximately 5 ~ 85 ° so that the connection reliability between the 110 and the substrate 120 is not degraded. That is, when the bending angle is 5 ° or less, there is a disadvantage in that the elastic force of the wire terminal 130 is reduced, and when the bending angle is 85 ° or more, between the first terminal part 131 and the second terminal part 132. The disadvantage is that the mechanical stress is too large. In addition, the wire terminal 130 has a fan-in type or an outside of the semiconductor die 110 in which the second terminal portion 132 and the third terminal portion 133 are formed to face inwardly of the semiconductor die 110. The fan-out type may be formed toward the direction, but the type is not limited thereto. That is, the fan-in type or the fan-out type is appropriately selected according to the number of bond pads 112 formed on the semiconductor die 110 and the arrangement of the terminal wiring patterns 122 formed on the substrate 120. Can be. In addition, the wire terminal 130 may be formed of a gold wire (Au wire), an aluminum wire (Al wire), a copper wire (Cu wire), or an equivalent thereof, where the material of the wire terminal 130 is limited. It is not.

Meanwhile, the third terminal part 133 of the wire terminal 130 may be electrically and mechanically connected to the terminal wiring pattern 122 formed on the substrate 120 through the solder paste 135. That is, in the wire terminal 130 according to the present invention, the first terminal part 131 is ball-bonded to the bond pad 112 of the semiconductor die 110 by capillary among wire bonding equipment. Although it may be ball bonding, the third terminal portion 133 is difficult to stitch bonding or ball bonding to the terminal wiring pattern 122 of the substrate 120. Therefore, a predetermined amount of the solder paste 135 is formed in the terminal wiring pattern 122 of the substrate 120 during the manufacturing process, and the third terminal portion 133 of the wire terminal 130 is aligned. By performing the reflow process, the third terminal part 133 of the wire terminal 130 is electrically and mechanically connected to the terminal wiring pattern 122 of the substrate 120. This manufacturing method will be described in more detail below. Of course, the solder paste 135 may be lead-free solder in response to recent environmental pollution regulations, and various conductive fluxes may be used.

In addition, the wire terminal 130 preferably has a minimum pitch of approximately 100 to 300 μm. That is, the minimum pitch between the third terminals 133 of the wire terminal 130 is preferably 100 ~ 300㎛. If the minimum pitch of the third terminal 133 of the wire terminal 130 is about 100 μm or less, the wiring pattern (so called “land”) of 100 μm or less is realized in the substrate to which it is connected. Not only is it difficult, but there is a disadvantage in that the cost increases, and when the minimum pitch of the wire terminal 130 is about 300 μm or more, the pitch between the wiring patterns in the substrate is too large.

The spacer 140 is bonded to the first surface 110a of the semiconductor die 110 and is formed to have a predetermined thickness toward the substrate 120. That is, the spacer 140 is adhered to the solder mask 125 formed on the second surface 121b of the insulating layer 121 of the substrate 120 through the adhesive 142. The wire terminal 130 is not damaged by the weight of the semiconductor die 110 during the manufacturing process by the spacer 140. In addition, the spacer 140 is preferably an insulator to prevent electrical short, and is a highly elastic material to prevent separation between the semiconductor die 110 and the substrate 120 during thermal expansion or thermal contraction of the package. Absorption may be formed of epoxy, silicone, elastomer, polyimide or the like having low moisture absorption. However, the present invention is not limited to the material of the spacer 140, it is obvious that various materials can be used in addition. In addition, although three spacers 140 are illustrated in the drawing, respectively, spaced apart from each other by a predetermined distance, they may be formed between the semiconductor die 110 and the substrate 120 in an integral form.

Furthermore, the thickness of the spacer 140 is formed to be slightly smaller than the height of the wire terminal 130, so that the wire terminal 130 is surely in contact with the terminal wiring pattern 122. For example, the thickness of the spacer 140 is preferably 100 μm or more, preferably about 100 μm to 150 μm. When the thickness of the spacer 140 is 100 μm or less, a wire having a loop having an “S” shape should also be 100 μm or less, which is currently technically difficult, and also a gap between the semiconductor die and the substrate, that is, As the thickness of the spacer is smaller, the strain due to the difference in thermal expansion coefficient increases, so there is a problem that the conventional reliability improvement effect is lowered compared to the thickness of 100 µm or more with a spacer thickness of 100 µm or less. More specifically, in the case of a flip chip having a bump thickness of less than 80 μm, since the bump thickness, thermal expansion coefficient difference, and stress ratio due to repeated thermal stress are inversely related, cracks between metal interfaces of the flip chip bump occur, thereby deteriorating reliability. do. However, in the case of the present invention, the thickness of the spacer interposed between the semiconductor die and the substrate is maintained at a height of approximately 100 μm to 150 μm, and the conductive wire itself and the “S” shaped loop lower the thermal stress and thus reliability. This is further improved. On the other hand, when the thickness of the spacer 140 is 150㎛ or more, as a matter of course, there is a disadvantage in that the overall thickness of the package becomes thick.

The encapsulant 150 covers the semiconductor die 110, the plurality of wire terminals 130, the plurality of spacers 140, and the plurality of solder pastes 135 on the substrate 120 so that they are external. In addition to being completely protected from mechanical and chemical impact of the mechanical structure it is possible to maintain a predetermined structure. In this case, the semiconductor die 110 may have the second surface 110b coplanar with the upper surface 150a of the encapsulant 150. That is, since the second surface 110b of the semiconductor die 110 is exposed to the outside through the top surface 150a of the encapsulant 150, heat generated during the operation of the semiconductor die 110 may be quickly transferred to the outside. Can be released. Of course, the semiconductor die 110 may have a second surface 110b may be completely covered by the encapsulant 150. In addition, the encapsulant 150 has a side surface 150b coplanar with the substrate 120, that is, the side surface 121c of the insulating layer 121, so that the encapsulant 150 is formed into a single package through a sawing process after the encapsulation process. It may also be prepared in a separate manner. The encapsulant 150 may be any one selected from an encapsulant, an epoxy molding compound, or an equivalent thereof, but is not limited thereto.

In the line flip chip package 100a according to the present invention as described above, a mounting wiring pattern 123 formed on the substrate 120 is mounted on a conductive pad (not shown) of an external device. That is, the solder paste is interposed between the mounting wiring pattern 123 and the conductive pad and then reflowed, so that the line flip chip package 100a according to the present invention is mechanically and electrically mounted to an external device. .

1B, an underfill 160 may be further injected between the semiconductor die 110 and the substrate 120 in the line flip chip package 100b according to another embodiment of the present invention. That is, the underfill 160 is injected into a portion of the first surface 110a and the side surface 110c of the semiconductor die 110, such that the underfill 160 is provided with a plurality of wire terminals 130 and spacers 140. ) And the solder paste 135. Therefore, the underfill 160 as described above can further reduce the plastic stress due to the difference in thermal expansion coefficient between the semiconductor die 110 and the substrate 120, and thus the semiconductor die 110 due to the difference in thermal expansion coefficient. ) And the reliability of the electrical connection between the substrate 120 is further improved. The underfill 160 may be epoxy or an equivalent thereof, as is well known, and the underfill 160 is not limited thereto.

Of course, since the present invention interconnects the semiconductor die 110 and the substrate 120 using a substantially "S" shaped wire terminal 130, the plastic stress is already considerably smaller than the conventional bump technology. It is in a gin. Therefore, the underfill 160 is not an essential component of the present invention, which may be omitted according to the characteristics of the package. However, it is obvious that the underfill 160 may be additionally formed in all the other embodiments described below.

Subsequently, as illustrated in FIG. 1C, wire terminals 130 may be ball bonded to the plurality of bond pads 112 formed on the first surface 110a of the semiconductor die 110. In this case, the wire terminal 130 may be formed by mixing a fan-in type formed in the substantially inward direction of the semiconductor die 110 and a fan-out type formed in the substantially outward direction of the semiconductor die 110 as described above. As described above, the fan-in type wire terminal 130 or the fan-out type wire terminal 130 includes the number of bond pads 112 formed on the semiconductor die 110 and the wiring pattern 122 for terminals formed on the substrate 120. Since it can be variously formed according to the arrangement state of the), in the present invention is not limited to the fan-in type or fan-out type of the wire terminal 130.

2A is a cross-sectional view illustrating a line flip chip package according to another exemplary embodiment of the present invention, and FIG. 2B is a partial plan view illustrating a wire terminal formed on a semiconductor die.

As shown, the line flip chip package 200 according to another embodiment of the present invention is almost the same as the line flip chip package 100a described above. Therefore, the same reference numerals will be used for the same components, and the structural differences will be described.

As shown in FIG. 2A, the wire terminals 130 may be formed in a fan type. That is, among the first terminal portion 131, the second terminal portion 132, and the third terminal portion 133 constituting the wire terminal 130, both the second terminal portion 132 and the third terminal portion 133 are the semiconductor die 110. It may be formed to face inward. At this time, in order to realize the fine pitch of the wire terminal 130, the fan-type second terminal portion 132 may be formed in various lengths. That is, as illustrated in FIG. 2B, the lengths of the second terminal portions 132 of the wire terminals 130 may be alternately formed. In other words, the specific wire terminal 130 is formed relatively short, and the other wire terminal 130 adjacent thereto is formed relatively long, and this form is repeated.

 Therefore, the present invention can be easily applied to the package of the semiconductor die 110 and the ultra fine pitch in which a large amount of the bond pads 112 are formed even though all the wire terminals 130 are formed in the fan-in type. do.

In addition, when the wire terminals 130 are all formed in a fan type as described above, the side surface 110c of the semiconductor die 110, the side surface 150b of the encapsulant 150, and the substrate 120 (insulating layer) Both side surfaces 121c of 121 may be coplanar. Therefore, since the width of the semiconductor die 110 and the width of the package 200 are the same, a true chip size package may be implemented. However, in the drawing, the side surface 110c of the semiconductor die 110 is shown sealed with the encapsulant 150.

3A is a cross-sectional view illustrating a line flip chip package according to another exemplary embodiment of the present invention, and FIG. 3B is a partial plan view illustrating a wire terminal formed on a semiconductor die.

Here, the line flip chip package 300 according to another embodiment of the present invention is almost the same as the above-described line flip chip package 100a. Therefore, the same reference numerals will be used for the same components, and will be described based on structural differences.

As shown in FIG. 3A, the wire terminal 130 may be formed by mixing a fan-in type and a fan-out type, and also may include a second terminal part 132 or a fan-out type wire constituting the fan-in type wire terminal 130. The length of the second terminal unit 132 constituting the terminal 130 may be formed in two or more types rather than one type. That is, as shown in FIG. 3B, the lengths of the second terminal portion 132 of the fan type wire terminal 130 and the second terminal portion 132 of the other fan type wire terminal 130 may be different from each other. have. In addition, although not shown, the lengths of the second terminal portion 132 of the wire terminal 130 of a fanout type and the second terminal portion 132 of the wire terminal 130 of the other fanout type may be different from each other. . Therefore, this structure enables the present invention to be more suitably applied to the semiconductor die 110 and the ultra fine pitched package having the large amount of bond pads 112.

4 is a flowchart illustrating a method of manufacturing a line flip chip package according to the present invention.

As illustrated, the method for manufacturing a line flip chip package according to the present invention includes a spacer forming step S1 of forming a plurality of spacers having a predetermined thickness in each semiconductor die of a wafer, and a single semiconductor die from the wafer. A semiconductor die sawing step (S2) of sawing and separating by using a blade or the like, a semiconductor die fixing step (S3) of fixing the sawed semiconductor die to a jig of a predetermined form; A wire terminal forming step (S4) of forming a wire terminal having a predetermined length on a bond pad of the semiconductor die fixed to the jig, an adhesive forming step (S5) of forming an adhesive on a spacer of the semiconductor die, and the semiconductor die Pick and place a semiconductor die pick and place step (S6) to allow the wire terminals to be seated in the substrate wiring pattern of the substrate. A reflow step (S7) of providing a high temperature so that the wire terminals of the semiconductor die are completely connected to the substrate wiring patterns of the substrate by solder paste, the semiconductor die, a plurality of spacers, a plurality of wire terminals, Encapsulation step (S8) for wrapping a plurality of solder paste and the like with an encapsulant.

The method of manufacturing a semiconductor package according to the present invention will be described in more detail with reference to FIGS. 5A to 5I as follows.

First, referring to FIG. 5A, a spacer forming step S1 is illustrated. As shown, a plurality of semiconductor dies 110 are formed on the wafer w with a substantially scribed line of scribe lines s formed therein, and each of the semiconductor dies 110 has a plurality of bond pads. 112 is formed, and a plurality of insulating spacers 140 having a predetermined thickness are formed in the inner region of the bond pad 112. The spacer 140 may be formed by, for example, any one of a screen printing method, a jet dispensing method, or an equivalent method of the insulating solution. ) Is not limited. In addition, the spacer 140 may be formed of any one insulating material selected from epoxy, silicon, polyimide, elastomer, or equivalent thereof having a predetermined elasticity, but the material is not limited thereto. Of course, such a spacer 140 may not be formed on a reject die and an edge die. In addition, the thickness of the spacer 140 is preferably 100 μm or more, preferably about 100 μm to 150 μm. When the thickness of the spacer 140 is 100 μm or less, a wire having a “S” shaped loop must also be 100 μm or less, which is technically difficult, and also a gap between the semiconductor die and the substrate, that is, the spacer. The lower the thickness of, the higher the strain due to the difference in thermal expansion coefficient, there is a problem that the conventional reliability improvement effect is lower than the thickness of 100㎛ or more with a spacer thickness of 100㎛ or less. In addition, when the thickness of the spacer 140 is 150㎛ or more, there is a disadvantage in that the overall thickness of the package becomes thick.

Referring to FIG. 5B, a sawing step S2 of the semiconductor die is shown. More precisely, a single semiconductor die 110 is shown, which is sawed and separated from the wafer w. This sawing of the semiconductor die 110 is performed by cutting along a scribe line s formed in the wafer w using a diamond blade (not shown) or the like as is well known. Of course, the sawing of the semiconductor die 110 is performed, for example, in a state in which the adhesive tape is adhered to the circular ring and the wafer is adhered to the surface thereof. In addition, the individual semiconductor die 110 as described above is picked up from the wafer by an adsorption tool.

Referring to FIG. 5C, a semiconductor die fixing step S3 is shown. More precisely, the step of securing the semiconductor die 110 to a jig z of some form is shown. That is, the groove z1 having a predetermined depth is formed in the jig z having a substantially rectangular hexahedron shape, and a plurality of vacuum suction holes z2 are formed at the bottom surface of the groove z1 to provide a predetermined suction force. . Of course, this recess z1 is almost similar to the width and thickness of the semiconductor die 110. Therefore, after the semiconductor die 110 is seated in the recess z1 of the jig z, the semiconductor die 110 is firmly fixed to the jig z by the strong adsorption force of the vacuum adsorption hole z2. It becomes a state.

Referring to FIG. 5D, the wire terminal forming step S4 is illustrated. Here, the jig is omitted in the drawing. Such a wire terminal 130 is performed by a wire bonding equipment used in a general packaging process. That is, as shown, the lower end of the wire w1 is ball bonded to the bond pad 112 of the semiconductor die 110 by the capillary c of the wire bonding equipment, and then the capillary c of the For example, the first terminal portion 131, the second terminal portion 132, and the third terminal portion 133 are continuously defined and formed by the predetermined trajectory. Of course, after the third terminal portion 133 is formed, the wire w1 is cut from the third terminal portion 133 by the spark of the discharge tip e. As described above, the wire terminal 130 is formed to be substantially "S" to have a predetermined elastic force. Of course, as described above, the wire terminal 130 has a fan-in type, a fan-out type, a type in which the fan-in type and the fan-out type are mixed, and the length of each second terminal portion 132 is different depending on a preset value. Can be formed. Here, since the vacuum suction force is continuously provided through the suction holes formed in the jig during the formation of the wire terminal 130, the semiconductor die 110 is not shaken during the formation of the wire terminal 130. In addition, the wire terminal 130 preferably has a minimum pitch of approximately 100 to 300 μm. That is, the minimum pitch between the third terminals 133 of the wire terminal 130 is preferably 100 ~ 300㎛. If the minimum pitch of the third terminal 133 of the wire terminal 130 is about 100 μm or less, the wiring pattern (so called “land”) of 100 μm or less is realized in the substrate to which it is connected. Not only is it difficult, but there is a disadvantage in that the cost increases, and when the minimum pitch of the wire terminal 130 is about 300 μm or more, the pitch between the wiring patterns in the substrate is too large.

Referring to FIG. 5E, an adhesive forming step S5 is shown. As shown, the formation of the adhesive 142 is formed by a given adhesive tool (a). To this end, first, the vacuum suction force is removed through the suction hole formed in the groove of the jig. Subsequently, the adhesive tool a adsorbs the semiconductor die 110 coupled to the jig and rises a predetermined height upward. In this case, an adhesive 142 having a predetermined thickness is formed on the bottom surface of the adhesive tool a. The adhesive 142 is embedded in the spacer 140 formed on the semiconductor die 110 by a predetermined amount, thereby forming the spacer ( An amount of adhesive 142 is naturally formed at the end of the 140.

5F and 5G, the pick and place step S6 of the semiconductor die is shown. For this pick-and-place of the semiconductor die 110, the adhesive tool a first rotates approximately 180 ° as shown in FIG. 5F. Then, the pick-and-place tool p rises a predetermined height in a state in which the pick-and-place tool p strongly vacuum-adsorbs the opposite surface on which the bond pad 112 is not formed in the semiconductor die 110. Then, while the semiconductor die 110 is separated from the adhesive tool a, a certain amount of adhesive 142 remains in the spacer 140. Subsequently, as shown in FIG. 5G, the pick and place tool p positions the semiconductor die 110 at a predetermined position of the substrate 120. Here, a predetermined amount of solder paste 135 may be formed at a predetermined position of the substrate 120 by any one method selected from a screen printing method, a pin dotting method, or an equivalent method thereof. As described above, the substrate 120 has a mounting wiring pattern 123 formed on the lower surface of the insulating layer 121 and a terminal wiring pattern 122 formed on the upper surface of the substrate 120. A predetermined amount of solder paste 135 is formed in 122. Of course, the mounting wiring pattern 123 and the terminal wiring pattern 122 are connected to each other by the conductive via hole 124. In addition, solder masks 125 and 126 are coated on the upper and lower surfaces of the insulating layer 121, respectively, and the mounting wiring patterns 123 and the terminal wiring patterns 122 are respectively formed through the solder masks 125 and 126. It is exposed to the outside.

Referring to FIG. 5H, a reflow step S7 is shown. As described above, after temporarily attaching the wire terminal 130 of the semiconductor die 110 to the terminal wiring pattern 122 of the substrate 120 by using the solder paste 135, it is about 100 to 250 as it is. The furnace is heated in a hot furnace provided a temperature of °. Then, all of the flux of the solder paste 135 is removed by volatilization and the solder is melted to fix the wire terminal 130 to the terminal wiring pattern 122. Of course, after melting the solder, the semiconductor die 110 and the substrate 120 and the like are integrally taken out from the furnace and cooled to room temperature. By such cooling, the wire terminal 130 is firmly fixed to the terminal wiring pattern 122 mechanically and electrically.

Referring to FIG. 5I, an encapsulation step S8 is shown. Such encapsulation is accomplished through conventional molds or dispensers. In the case of using a mold, the reflow-completed package is placed between the upper mold and the lower mold, and the encapsulant 150 such as an epoxy molding compound or encapsulant of high temperature and high pressure is filled in the upper region of the substrate 120. The encapsulant 150 is formed. In this case, one surface of the semiconductor die 110 may be exposed to the outside of the encapsulant 150 so that heat generated during the operation of the semiconductor die 110 may be easily released to the outside. In addition, when using a dispenser, a predetermined amount of encapsulant 150 is dispensed on the substrate 120 in the reflowed package. Then, the encapsulant 150 is naturally filled in the gap between the semiconductor die 110 and the substrate 120 by the weight of the encapsulant 150, thereby forming an encapsulant 150 having a predetermined shape. Done.

In addition, an underfill process may be further performed before the encapsulation step so that the plastic stress between the semiconductor die 110 and the substrate 120 may be further reduced. That is, by injecting a predetermined amount of underfill into the gap between the semiconductor die 110 and the substrate 120, the semiconductor die 110 and the substrate 120 may be more firmly fixed to each other. The underfill serves to more actively prevent separation due to the difference in thermal expansion coefficient between the semiconductor die 110 and the substrate 120.

As described above, the line flip chip package according to the present invention and a method of manufacturing the same by forming a wire terminal instead of bump using conventional wire bonding equipment without expensive bumping process, by connecting it to the substrate in a flip chip method, This has the effect of implementing a line flip chip package at low cost.

In addition, the line flip chip package and the method of manufacturing the same according to the present invention have an effect of improving the electrical connection reliability and stability of the semiconductor die and the substrate by electrically connecting the semiconductor die and the substrate to each other using wire terminals and solder paste. . That is, conventionally, due to the thickness variation in the bumps, the specific bumps may not be electrically connected to the substrate, and the bumps may be cracked or separated from the substrates due to the difference in thermal expansion coefficient. By using a wire terminal which is present, and also by connecting such a wire terminal electrically to the substrate through solder paste, there is an effect of improving connection reliability and stability.

In addition, the line flip chip package and the manufacturing method thereof according to the present invention can easily accommodate a semiconductor die having a recent ultra fine pitch and formed with a large amount of bond pads by electrically connecting the semiconductor die and the substrate with a small diameter wire terminal. It can work.

In addition, the line flip chip package and the method of manufacturing the same according to the present invention have the effect of further reducing the thickness of the package as a whole by interposing a spacer having a smaller thickness than the conventional bump between the semiconductor die and the substrate. Of course, by using a spacer having a thickness smaller than the bump as described above, the stress rate due to thermal stress can be increased, but the conductive wire itself and the "S" shaped wire loop absorb all of the thermal stress. By lowering the power, thereby improving reliability.

What has been described above is just one embodiment for carrying out the line flip chip package and the manufacturing method according to the present invention, the present invention is not limited to the above embodiment, as claimed in the following claims Without departing from the gist of the present invention, anyone of ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

Claims (25)

A semiconductor die having a plurality of bond pads formed thereon; A substrate positioned to face a bond pad of the semiconductor die, the substrate having a plurality of wiring patterns formed on a surface thereof; A plurality of wire terminals interconnecting each bond pad of the semiconductor die and each wiring pattern of the substrate, The wire terminal is A first terminal portion connected to a bond pad of the semiconductor die and extending in a vertical direction from a surface of the bond pad; A second terminal portion having a bending angle of 5 to 85 ° from the first terminal portion and extending; And a third terminal portion which is bent from the second terminal portion and connected to the wiring pattern of the substrate, wherein the third terminal portion is perpendicular to the wiring pattern. The line flip chip package according to claim 1, wherein the wire terminal is connected to the wiring pattern of the substrate by solder paste. The line flip chip package of claim 1, further comprising a plurality of insulating spacers between the semiconductor die and the substrate. The line flip chip package of claim 3, wherein one side of the insulating spacer is directly bonded to the surface of the semiconductor die, and the other side is bonded to the substrate through an adhesive. The line flip chip package of claim 3, wherein the insulating spacer has a thickness of about 100 μm to about 150 μm. The line flip chip package of claim 1, wherein the wire terminal has a minimum pitch of 100 μm to 300 μm. delete delete delete The line flip chip package of claim 1, wherein the second terminal portion of the wire terminal has at least two kinds of lengths. The line flip chip package of claim 1, wherein the wire terminal is a fan-in type that is bent toward an inner side of the semiconductor die. The line flip chip package of claim 1, wherein the wire terminal is a fan-out type bent toward the outside of the semiconductor die. The method of claim 1, wherein the wire terminal is a fan-in type bent toward the inside of the semiconductor die (fan-in type), and a fan-out type bent toward the outside of the semiconductor die (mixed) Line flip chip package, characterized in that formed. The line flip chip package of claim 1, wherein the conductive wire is formed of one selected from a gold wire, an aluminum wire, or a copper wire. The line flip chip package of claim 1, wherein the semiconductor die and the plurality of wire terminals are encapsulated with an encapsulant. The line flip chip package of claim 15, wherein an opposite surface of the semiconductor die on which the bond pad is formed is exposed to the outside of the encapsulant. The line flip chip package of claim 1, wherein an underfill is further injected between the semiconductor die and the substrate to protect the plurality of wire terminals from an external environment. The method of claim 1, wherein the substrate is Plate-shaped insulation layer, A wiring pattern for terminal connection formed on one surface of the insulating layer and to which the wire terminal is connected; A mounting wiring pattern formed on the other surface of the insulating layer and mounted on an external device; And a conductive via configured to interconnect the terminal connection wiring pattern and the mounting wiring pattern to each other. The line flip chip of claim 18, wherein a solder mask is coated on one surface and the other surface of the substrate, and the terminal connection wiring pattern and the mounting wiring pattern are exposed to the outside through the solder mask. package. A spacer forming step of forming a plurality of spacers having a predetermined thickness in each semiconductor die of the wafer, Sawing a single semiconductor die from the wafer and fixing the sawed semiconductor die to a jig; A wire terminal forming step of forming a wire terminal having a predetermined length on a bond pad of the fixed semiconductor die; An adhesive forming step of forming an adhesive on a spacer of the semiconductor die; A die pick and place step of pick and place the semiconductor die so that the wire terminals are seated on the wiring pattern of the substrate; A reflow step of providing a high temperature so that the wire terminals of the semiconductor die are completely connected to the wiring pattern of the substrate; Encapsulating the semiconductor die, a plurality of spacers, and a plurality of wire terminals with an encapsulant; The wire terminal forming step The wire terminal A first terminal portion connected to a bond pad of the semiconductor die and extending in a vertical direction from a surface of the bond pad; A second terminal portion having a bending angle of 5 to 85 ° from the first terminal portion and extending; And a third terminal portion which is bent from the second terminal portion and connected to the wiring pattern of the substrate, the third terminal portion being perpendicular to the wiring pattern. 21. The method of claim 20, wherein the forming of the spacers comprises forming the insulating solution in any one of a screen printing method and a jet dispensing method. delete 21. The line flip chip package of claim 20, wherein the die pick and place step is performed after a solder paste is formed in advance on a wiring pattern of the substrate. 24. The line flip chip package of claim 23, wherein the solder paste is formed on the wiring pattern of the substrate by any one of a screen printing method and a pin dot method. 21. The line flip chip package of claim 20 wherein an underfill is implanted to protect the wire terminals between the semiconductor die and the substrate prior to the encapsulation step.

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