JPH07263490A - Flip chip and microbonding method - Google Patents

Flip chip and microbonding method

Info

Publication number
JPH07263490A
JPH07263490A JP6050513A JP5051394A JPH07263490A JP H07263490 A JPH07263490 A JP H07263490A JP 6050513 A JP6050513 A JP 6050513A JP 5051394 A JP5051394 A JP 5051394A JP H07263490 A JPH07263490 A JP H07263490A
Authority
JP
Japan
Prior art keywords
circuit board
electrode
semiconductor chip
chip
external electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6050513A
Other languages
Japanese (ja)
Inventor
Hiroshi Akasaki
博 赤▲崎▼
Takashi Miwa
孝志 三輪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP6050513A priority Critical patent/JPH07263490A/en
Publication of JPH07263490A publication Critical patent/JPH07263490A/en
Withdrawn legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent fatigue damage by providing an elastic protrusion between an outer electrode of a side having a dummy electrode and the dummy electrode, and providing a conductive wire for connecting the outer electrode to the dummy electrode in a loop to cross over the protrusion. CONSTITUTION:A dummy electrode 18 and an elastic protrusion 15 made of silicone rubber between chip electrodes 16 and the electrode 18 are provided, in addition to the electrodes 16, on an element forming surface of a semiconductor chip 11, and one end of a conductive wire 17 is connected to the electrode 18 by wedge bonding in a loop on the protrusion 15. The chip 11 is so aligned in a face-down bonding manner that board electrodes 19 on a circuit board 12 are touched to the wire 17, and the chip 11 is fixed to the board 12 with optically curable resin as adhesive. Thus, fatigue damage of a connecting part of the chip to the board can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、特
に、フリップチップボンディング型半導体装置に適用し
て有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a flip chip bonding type semiconductor device.

【０００２】[0002]

【従来の技術】従来における半導体装置には、半導体チ
ップをフェイスダウンで回路基板と接続するフリップチ
ップボンディング型半導体装置があり、これは半田で半
導体チップと回路基板を接続するものであり、そのフリ
ップチップボンディング型半導体装置の半導体チップの
電極上には、半田ぬれを確保し、かつ、半田の電極への
浸食を防止するためのＣｒ−Ｃｕ−Ａｕ等の下地金属層
と、その上に半田を蒸着等で供給して形成されたバンプ
とが設けられ、一方、半導体チップの電極に対応する回
路基板の電極上に前述と同様な下地金属層と半田流れ防
止のガラス膜を設け、その上に半田を供給して形成した
バンプが設けられており、半導体チップと回路基板の両
者の半田バンプを突き合わせて加熱溶融させてボンディ
ングしたものからなる。2. Description of the Related Art A conventional semiconductor device is a flip chip bonding type semiconductor device in which a semiconductor chip is connected to a circuit board face down. This is a device for connecting the semiconductor chip and the circuit board with solder. On the electrode of the semiconductor chip of the chip bonding type semiconductor device, a base metal layer of Cr-Cu-Au or the like for securing solder wettability and preventing erosion of the solder to the electrode, and solder on the base metal layer. Bumps that are formed by supplying by vapor deposition are provided.On the other hand, a similar underlying metal layer and solder flow prevention glass film as described above are provided on the electrodes of the circuit board that correspond to the electrodes of the semiconductor chip. The bumps formed by supplying solder are provided, and the solder bumps of both the semiconductor chip and the circuit board are abutted, heated, melted, and bonded. That.

【０００３】[0003]

【発明が解決しようとする課題】本発明者は、上記従来
技術を検討した結果、以下の問題点を見いだした。DISCLOSURE OF THE INVENTION The present inventors have found the following problems as a result of examining the above prior art.

【０００４】従来のフリップチップボンディング型半導
体装置は、半導体チップと回路基板とが半田バンプで固
定されて接続されているが、半導体チップと回路基板と
に熱膨張差があるため、半導体チップの発熱や環境温度
変化により、接続部の半田ににストレスが発生し、疲労
破壊に至るという問題点があった。In the conventional flip-chip bonding type semiconductor device, the semiconductor chip and the circuit board are fixedly connected by solder bumps, but since the semiconductor chip and the circuit board have a difference in thermal expansion, the semiconductor chip generates heat. There is a problem that stress is generated in the solder at the connection portion due to changes in the ambient temperature and fatigue breakdown occurs.

【０００５】また、電極上に下地金属層を形成するプロ
セスが必要になるため、半導体チップ製造コストが高く
なるという問題点があった。Further, since a process of forming a base metal layer on the electrode is required, there is a problem that the manufacturing cost of the semiconductor chip becomes high.

【０００６】本発明の目的は、半導体チップと回路基板
の接続部における疲労破壊を防止することが可能な技術
を提供することにある。It is an object of the present invention to provide a technique capable of preventing fatigue damage at a connecting portion between a semiconductor chip and a circuit board.

【０００７】本発明の他の目的は、半導体装置（半導体
チップ、回路基板等を含む）の製造コストを低くするこ
とが可能な技術を提供することにある。Another object of the present invention is to provide a technique capable of reducing the manufacturing cost of a semiconductor device (including a semiconductor chip, a circuit board, etc.).

【０００８】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【０００９】[0009]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

【００１０】半導体チップの素子形成面上または、回路
基板上のいづれか一方の外部電極の近傍にダミーの電極
及びそのダミー電極を設けた側の外部電極とダミーの電
極間に弾性体突起を設け、その弾性体突起上を跨ぐよう
にループさせて前記外部電極とダミー電極を結線する導
電性ワイヤを設け、その導電性ワイヤと回路基板上また
は、半導体チップ上の外部電極とを圧接荷重してボンデ
ィングする。A dummy electrode is provided on the element formation surface of the semiconductor chip or in the vicinity of one of the external electrodes on the circuit board, and an elastic protrusion is provided between the external electrode on the side where the dummy electrode is provided and the dummy electrode. A conductive wire for connecting the external electrode and the dummy electrode is provided by looping over the elastic protrusion, and the conductive wire and the external electrode on the circuit board or on the semiconductor chip are pressure-contacted and bonded. To do.

【００１１】[0011]

【作用】上述した手段によれば、半導体チップの素子形
成面上または、回路基板上のいづれか一方の外部電極の
近傍にダミーの電極と、そのダミー電極を設けた側の外
部電極とダミーの電極間に弾性体突起を設け、その弾性
体突起上を跨ぐようにループさせて前記外部電極とダミ
ー電極を結線する導電性ワイヤを設け、その導電性ワイ
ヤと回路基板上または、半導体チップ上の外部電極とを
圧接荷重してボンディングすることにより、半導体チッ
プや回路基板がそれぞれ熱膨張しても、圧接部における
導電性ワイヤと外部電極は電気的に繋がれた状態で摺動
するのみで接続部に応力の集中が発生しないので、半導
体チップと回路基板の接続部における疲労破壊を防止す
ることが可能となる。According to the above-mentioned means, the dummy electrode is provided on the element forming surface of the semiconductor chip or in the vicinity of either one of the external electrodes on the circuit board, and the external electrode on the side where the dummy electrode is provided and the dummy electrode. An elastic protrusion is provided between the elastic protrusion and a conductive wire that connects the external electrode and the dummy electrode by looping over the elastic protrusion, and the conductive wire is connected to the circuit board or the outside of the semiconductor chip. Even if the semiconductor chip or circuit board undergoes thermal expansion by bonding under pressure contact with the electrode, the conductive wire in the pressure contact part and the external electrode only slide while being electrically connected to the connection part. Since stress concentration does not occur in the semiconductor chip, it is possible to prevent fatigue damage at the connecting portion between the semiconductor chip and the circuit board.

【００１２】また、下地金属層を形成する必要がないの
で、半導体装置（半導体チップ、回路基板等を含む）の
製造コストを低くすることが可能となる。Further, since it is not necessary to form the underlying metal layer, the manufacturing cost of the semiconductor device (including the semiconductor chip, the circuit board, etc.) can be reduced.

【００１３】以下、本発明の構成について、実施例とと
もに説明する。The structure of the present invention will be described below together with embodiments.

【００１４】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

【００１５】[0015]

【実施例】図１は、本発明の一実施例であるフリップチ
ップボンディング型半導体装置を説明するためのもので
あり、図１（ａ）はその構成図を、図１（ｂ）は、破線
で囲まれた接続部の拡大図をそれぞれ示す。1 is a view for explaining a flip-chip bonding type semiconductor device which is an embodiment of the present invention. FIG. 1 (a) is a configuration diagram thereof, and FIG. 1 (b) is a broken line. The enlarged view of the connection part enclosed with each is shown, respectively.

【００１６】図１において、１０は半導体装置、１１は
半導体チップ、１２は回路基板、１３は接続部、１４は
固定部材（光硬化性樹脂）、１５は弾性体突起（シリコ
ンゴム）、１６は半導体チップの外部電極（以下、チッ
プ電極と記す）、１７は導電性ワイヤ（金線）、１８は
ダミーの外部電極（以下、ダミー電極と記す）、１９は
回路基板の外部電極（以下、基板電極と記す）をそれぞ
れ示す。In FIG. 1, 10 is a semiconductor device, 11 is a semiconductor chip, 12 is a circuit board, 13 is a connecting portion, 14 is a fixing member (photo-curing resin), 15 is an elastic protrusion (silicon rubber), and 16 is. External electrodes of semiconductor chip (hereinafter referred to as chip electrodes), 17 is a conductive wire (gold wire), 18 is a dummy external electrode (hereinafter referred to as dummy electrode), 19 is an external electrode of a circuit board (hereinafter referred to as substrate) Electrode)).

【００１７】図１に示すように、本実施例のフリップチ
ップボンディング型半導体装置の半導体チップ１１の素
子形成面上には、チップ電極１６の他にダミー電極１８
とその両者間に、シリコンゴム等よりなる弾性体突起１
５が設けられ、この弾性体突起１５上をループして導電
性ワイヤ１７の一端が外部電極１６にネールヘッドボン
ディングで結線され、他端がダミー電極１８にウェッジ
ボンディングで結線されている。As shown in FIG. 1, on the element formation surface of the semiconductor chip 11 of the flip chip bonding type semiconductor device of this embodiment, the dummy electrode 18 is provided in addition to the chip electrode 16.
And the elastic protrusion 1 made of silicon rubber or the like between them.
5 is provided, and one end of the conductive wire 17 is looped over the elastic protrusion 15 and connected to the external electrode 16 by nail head bonding, and the other end is connected to the dummy electrode 18 by wedge bonding.

【００１８】なお、図１（ｂ）に示したチップ電極１６
やダミー電極１８や弾性体突起１５の配置や形状、及び
導電性ワイヤ１７の結線形態は、これに限られるもので
はなく、回路基板側に弾性体突起１５を設けてもよい
し、両者の電極の配置が逆であったり、両方の結線とも
にウェッジであってもよい。The chip electrode 16 shown in FIG.
The arrangement and shape of the dummy electrode 18 and the elastic projection 15 and the connection form of the conductive wire 17 are not limited to this, and the elastic projection 15 may be provided on the circuit board side, or both electrodes may be provided. The arrangement may be reversed, or both connections may be wedges.

【００１９】そして、図１（ａ）に示すように、半導体
チップ１１をフェースダウンで、回路基板１２上の基板
電極１９と導電性ワイヤ１７とが接するように位置合わ
せして、半導体チップ１１の中央部付近で光硬化性樹脂
（アクリレート系または、エポキシ系との混合物等）を
接着剤として、半導体チップ１１と回路基板１２を固定
してある。Then, as shown in FIG. 1A, the semiconductor chip 11 is positioned face down so that the substrate electrode 19 on the circuit board 12 and the conductive wire 17 are in contact with each other. The semiconductor chip 11 and the circuit board 12 are fixed to each other in the vicinity of the center by using a photo-curable resin (a mixture of acrylate or epoxy) as an adhesive.

【００２０】次に、本実施例の半導体装置のマイクロボ
ンディング方法について説明する。Next, a microbonding method for the semiconductor device of this embodiment will be described.

【００２１】図２（ａ）〜図２（ｄ）は、本実施例にお
けるフリップチップボンディングの過程を説明するため
のものである。2 (a) to 2 (d) are for explaining the process of flip chip bonding in this embodiment.

【００２２】本実施例におけるマイクロボンディング
は、まず、図２（ａ）に示すように、半導体チップ１１
の素子形成面上のチップ電極１６付近にシリコンゴム等
の弾性体突起１５をポッティング等で設け、かつ、ダミ
ー電極１８をその弾性体突起１５を挟んでチップ電極１
６と反対側にチップ電極１６の形成と同様にスパッタリ
ング等で設ける。In the microbonding in this embodiment, first, as shown in FIG.
An elastic protrusion 15 such as silicon rubber is provided by potting or the like near the chip electrode 16 on the element forming surface of the chip electrode 1, and a dummy electrode 18 is sandwiched between the elastic protrusions 15 to form the chip electrode
Similar to the formation of the chip electrode 16, it is provided on the side opposite to 6 by sputtering or the like.

【００２３】その後、図２（ｂ）に示すように、金線等
の導電性ワイヤ１７で弾性体突起１５を跨ぐようにチッ
プ電極１６とダミー電極１８間を結線する。このときの
導電性ワイヤ１７の結線は、チップ電極１６側をネール
ヘッドボンディングし、ダミー電極１８側は、ウェッジ
ボンディングするが、前述したように、結線のボンディ
ング形式はこれに限定されない。After that, as shown in FIG. 2B, the chip electrode 16 and the dummy electrode 18 are connected by a conductive wire 17 such as a gold wire so as to straddle the elastic protrusion 15. Regarding the connection of the conductive wire 17 at this time, the chip electrode 16 side is nail head bonded and the dummy electrode 18 side is wedge bonded, but as described above, the connection bonding method is not limited to this.

【００２４】その後、図２（ｃ）に示すように、この素
子形成面に設けられた導電性ワイヤ１７を有する半導体
チップ１１をフェイスダウンにし、図２（ｄ）に示すよ
うに、半導体チップ１１と回路基板１２の中央部付近に
光硬化性樹脂１４を介在させて、半導体チップ１１の上
方から荷重して導電性ワイヤ１７と基板電極１９とを圧
接する。After that, as shown in FIG. 2C, the semiconductor chip 11 having the conductive wires 17 provided on the element forming surface is face down, and as shown in FIG. The photo-curable resin 14 is interposed near the central portion of the circuit board 12, and a load is applied from above the semiconductor chip 11 to press-contact the conductive wire 17 and the board electrode 19.

【００２５】そして、その光硬化性樹脂に光を照射して
半導体チップ１１と回路基板１２を固定する。Then, the photocurable resin is irradiated with light to fix the semiconductor chip 11 and the circuit board 12.

【００２６】また、この樹脂が硬化するとき生じる収縮
応力により、導電性ワイヤ１７と基板電極１９堅固に圧
接される。Further, the conductive wire 17 and the substrate electrode 19 are firmly pressed against each other due to the contraction stress generated when the resin is cured.

【００２７】したがって、半導体チップの素子形成面上
または、回路基板上の外部電極の近傍のいづれか一方に
ダミーの電極と、そのダミー電極を設けた側の外部電極
とダミーの電極間に弾性体突起を設け、その弾性体突起
上を跨ぐようにループさせて前記外部電極とダミー電極
を結線する導電性ワイヤを設け、その導電性ワイヤと回
路基板上または、半導体チップ上の外部電極とを圧接荷
重してボンディングすることにより、半導体チップや回
路基板がそれぞれ熱膨張しても、圧接部における導電性
ワイヤと外部電極は電気的に繋がれた状態で摺動するの
みで接続部に応力の集中が発生しないので、半導体チッ
プと回路基板の接続部における疲労破壊を防止すること
が可能となる。Therefore, the dummy electrode is provided on either the element formation surface of the semiconductor chip or in the vicinity of the external electrode on the circuit board, and the elastic protrusion is provided between the external electrode on the side where the dummy electrode is provided and the dummy electrode. And a conductive wire that connects the external electrode and the dummy electrode by looping over the elastic protrusion and connecting the conductive wire and the external electrode on the circuit board or on the semiconductor chip with a pressure load. Even if the semiconductor chip and the circuit board are respectively thermally expanded, the conductive wire and the external electrode in the pressure contact portion slide only in the electrically connected state, and the stress concentrates on the connection portion. Since it does not occur, it is possible to prevent fatigue damage at the connection between the semiconductor chip and the circuit board.

【００２８】また、下地金属層を形成する必要がないの
で、半導体装置（半導体チップ、回路基板等を含む）の
製造コストを低くすることが可能となる。Further, since it is not necessary to form the base metal layer, the manufacturing cost of the semiconductor device (including the semiconductor chip, the circuit board, etc.) can be reduced.

【００２９】さらに、弾性体突起を設けることにより、
半導体チップまたは、回路基板表面の凹凸を吸収できる
ので、半導体チップや回路基板の凹凸に依存しないで電
気的に良好に接続可能である。Furthermore, by providing an elastic protrusion,
Since the irregularities on the surface of the semiconductor chip or the circuit board can be absorbed, good electrical connection can be achieved without depending on the irregularities of the semiconductor chip or the circuit board.

【００３０】次に、本発明の他の実施例について図３〜
図６を用いて説明する。Next, another embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

【００３１】図３は、前述の弾性体突起１５の代わりに
半導体チップ１１の素子形成面上に延在した棒状の弾性
体突起１５を設けた例を示したものである。FIG. 3 shows an example in which a bar-shaped elastic protrusion 15 extending on the element forming surface of the semiconductor chip 11 is provided instead of the elastic protrusion 15 described above.

【００３２】図３（ａ）に示すように、弾性体突起１５
を個別に形成するのではなく、各チップ電極１６及びダ
ミー電極１８に共通の棒状の弾性体突起１５を設けるこ
とにより、形成時間の短縮や、導電性ワイヤ間のピッチ
を狭くでき、半導体装置の多ピン化に対応できる。As shown in FIG. 3A, the elastic projection 15
By providing a common rod-shaped elastic protrusion 15 for each chip electrode 16 and dummy electrode 18 instead of individually forming each, the formation time can be shortened and the pitch between the conductive wires can be narrowed. It can support multiple pins.

【００３３】また、図３（ｂ）に示すように、図３
（ａ）の棒状の弾性体突起１５のパターンを複数個設け
ることにより、超多ピン化にも対応可能である。Further, as shown in FIG.
By providing a plurality of patterns of the rod-shaped elastic protrusions 15 of (a), it is possible to cope with an increase in the number of pins.

【００３４】次に、図４は、前述の導電性ワイヤの代わ
りに、絶縁被覆された導電性ワイヤ２０を用いた時の例
である。Next, FIG. 4 shows an example in which an insulating coated conductive wire 20 is used instead of the above-mentioned conductive wire.

【００３５】この絶縁被覆された導電性ワイヤ２０を用
いることにより、ワイヤ間の短絡を防止でき、多ピン化
に対応可能である。また、この絶縁被覆された導電性ワ
イヤ２０は、荷重圧接により、接合箇所だけの被覆が破
れて電気的に接合される。By using the electrically conductive wire 20 coated with insulation, it is possible to prevent short-circuiting between the wires, and it is possible to cope with an increase in the number of pins. In addition, the insulation-coated conductive wire 20 is electrically joined by the load pressure contact so that the coating only at the joining portion is broken.

【００３６】次に、図５は、図１（ａ）に示した本実施
例の半導体装置の半導体チップ上に放熱フィン２１を設
けて、この放熱フィン２１と回路基板１２とをクランプ
治具２２を用いて半導体チップ１１を締め付けた例を示
したものである。Next, in FIG. 5, a radiation fin 21 is provided on the semiconductor chip of the semiconductor device of this embodiment shown in FIG. 1A, and the radiation jig 21 and the circuit board 12 are clamped by a clamp jig 22. It shows an example in which the semiconductor chip 11 is tightened by using.

【００３７】このようにすることにより、図１（ａ）に
示した接続部１３が常に圧接状態を保つことが可能にな
り、電気的に良好な接続状態を保つことが可能となる。By doing so, the connection portion 13 shown in FIG. 1A can always be kept in a pressure contact state, and an electrically good connection state can be maintained.

【００３８】さらに、図６に示すように、光硬化性樹脂
１４を半導体チップ１１の素子形成面全体を覆うように
半導体チップ１１と回路基板１２を固定することによっ
ても、図１（ａ）に示した接続部１３が常に圧接状態を
保つことが可能になり、電気的に良好な接続状態を保つ
ことが可能となる。Further, as shown in FIG. 6, by fixing the semiconductor chip 11 and the circuit board 12 so that the photo-curable resin 14 covers the entire element forming surface of the semiconductor chip 11, the structure shown in FIG. The connection portion 13 shown can always be kept in a pressure contact state, and can be kept in an electrically excellent connection state.

【００３９】なお、本実施例での半導体装置は、裸チッ
プ（ベアチップ）のフリップチップボンディング型を対
象に説明してきたが、本発明は半導体チップがキャップ
または、樹脂等で封止された半導体装置に適用可能であ
る。Although the semiconductor device in this embodiment has been described as a bare chip flip chip bonding type, the present invention is a semiconductor device in which the semiconductor chip is capped or sealed with resin or the like. Is applicable to.

【００４０】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。The inventions made by the present inventors are as follows.
Although the specific description has been given based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

【００４１】[0041]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

【００４２】半導体チップや回路基板がそれぞれ熱膨張
しても、圧接部における導電性ワイヤと外部電極は電気
的に繋がれた状態で摺動するのみで接続部に応力の集中
が発生しないので、半導体チップと回路基板の接続部に
おける疲労破壊を防止することが可能となる。Even when the semiconductor chip and the circuit board are respectively thermally expanded, the conductive wire and the external electrode in the pressure contact portion slide only in the electrically connected state, and stress concentration does not occur in the connection portion. It is possible to prevent fatigue damage at the connecting portion between the semiconductor chip and the circuit board.

【００４３】また、下地金属層を形成する必要がないの
で、半導体装置（半導体チップ、回路基板等を含む）の
製造コストを低くすることが可能となる。Further, since it is not necessary to form the base metal layer, the manufacturing cost of the semiconductor device (including the semiconductor chip, the circuit board, etc.) can be reduced.

【００４４】各チップ電極及びダミー電極に共通の棒状
の弾性体突起を設けることにより、形成時間の短縮や、
導電性ワイヤ間のピッチを狭くでき、半導体装置の多ピ
ン化に対応できる。By providing a common rod-shaped elastic protrusion for each chip electrode and dummy electrode, the formation time can be shortened and
The pitch between the conductive wires can be narrowed, and the number of pins of the semiconductor device can be increased.

【００４５】導電性ワイヤと基板電極が常に圧接状態を
保つことが可能になり、電気的に良好な接続状態を保つ
ことが可能となる。Since the conductive wire and the substrate electrode can always be kept in pressure contact, it is possible to maintain a good electrical connection.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第一の実施例であるフリップチップボ
ンディング型半導体装置を説明するための図である。FIG. 1 is a diagram for explaining a flip chip bonding type semiconductor device which is a first embodiment of the present invention.

【図２】本実施例の半導体装置のマイクロボンディング
方法について説明するための図である。FIG. 2 is a diagram for explaining a microbonding method for a semiconductor device of this embodiment.

【図３】本発明の第二の実施例であるフリップチップボ
ンディング型半導体装置を説明するための図である。FIG. 3 is a diagram for explaining a flip-chip bonding type semiconductor device which is a second embodiment of the present invention.

【図４】本発明の第三の実施例であるフリップチップボ
ンディング型半導体装置を説明するための図である。FIG. 4 is a diagram for explaining a flip chip bonding type semiconductor device which is a third embodiment of the present invention.

【図５】本発明の第四の実施例であるフリップチップボ
ンディング型半導体装置を説明するための図である。FIG. 5 is a diagram for explaining a flip-chip bonding type semiconductor device which is a fourth embodiment of the present invention.

【図６】本発明の第五の実施例であるフリップチップボ
ンディング型半導体装置を説明するための図である。FIG. 6 is a diagram for explaining a flip-chip bonding type semiconductor device which is a fifth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１０…半導体装置、１１…半導体チップ、１２…回路基
板、１３…接続部、１４…固定部材（光硬化性樹脂）、
１５…弾性体突起（シリコンゴム）、１６…半導体チッ
プの外部電極、１７…導電性ワイヤ（金線）、１８…ダ
ミーの外部電極）、１９…回路基板の外部電極、２０…
放熱フィン、２１…クランプ治具。DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 11 ... Semiconductor chip, 12 ... Circuit board, 13 ... Connection part, 14 ... Fixing member (photocurable resin),
15 ... Elastic protrusions (silicon rubber), 16 ... Semiconductor chip external electrodes, 17 ... Conductive wires (gold wires), 18 ... Dummy external electrodes, 19 ... Circuit board external electrodes, 20 ...
Radiating fin, 21 ... Clamp jig.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 三輪 孝志 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Miwa 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップ及び回路基板を有し、前記
半導体チップの素子形成面を下にして回路基板とボンデ
ィングしたフリップチップボンディング型半導体装置で
あって、 前記半導体チップの素子形成面上または、回路基板上の
いづれか一方に外部電極の近傍にダミーの電極及びその
ダミー電極を設けた側の外部電極とダミーの電極間に弾
性体突起を設け、その弾性体突起上を跨ぐようにループ
させて前記外部電極とダミー電極を結線する導電性ワイ
ヤを設け、その導電性ワイヤと回路基板上または、半導
体チップ上の外部電極とを荷重圧着して固定する固定手
段を設けたことを特徴とするフリップチップボンディン
グ型半導体装置。1. A flip-chip bonding type semiconductor device having a semiconductor chip and a circuit board, the element forming surface of the semiconductor chip facing down, and being bonded to the circuit board, the element forming surface of the semiconductor chip or Provide a dummy electrode on either side of the circuit board near the external electrode and an elastic protrusion between the external electrode on the side where the dummy electrode is provided and the dummy electrode, and loop over the elastic protrusion. A flip provided with a conductive wire for connecting the external electrode and the dummy electrode, and fixing means for fixing the conductive wire and the external electrode on the circuit board or on the semiconductor chip by pressure bonding. Chip bonding type semiconductor device. 【請求項２】 前記請求項１に記載のフリップチップボ
ンディング型半導体装置であって、前記弾性体突起の代
わりに半導体チップの素子形成面上または、回路基板上
に延在した棒状の弾性体突起を設けたことを特徴とする
フリップチップボンディング型半導体装置。2. The flip chip bonding type semiconductor device according to claim 1, wherein a rod-shaped elastic protrusion extending on an element forming surface of a semiconductor chip or on a circuit board instead of the elastic protrusion. A flip-chip bonding type semiconductor device comprising: 【請求項３】 前記請求項１に記載のフリップチップボ
ンディング型半導体装置であって、前記導電性ワイヤの
代わりに絶縁膜で被服した導電性ワイヤを設けたことを
特徴とするフリップチップボンディング型半導体装置。3. The flip chip bonding type semiconductor device according to claim 1, wherein a conductive wire covered with an insulating film is provided in place of the conductive wire. apparatus. 【請求項４】 半導体チップの素子形成面と反対の面に
放熱用のフィンを設けた半導体チップと回路基板を有
し、半導体チップと回路基板をフリップチップボンディ
ングしたフリップチップボンディング型半導体装置であ
って、 前記半導体チップの素子形成面上または、回路基板上の
外部電極の近傍のいづれか一方にダミーの電極と、その
ダミー電極を設けた側の外部電極とダミーの電極間に弾
性体突起を設け、その弾性体突起上を跨ぐようにループ
させて前記外部電極とダミー電極を結線する導電性ワイ
ヤを設け、その導電性ワイヤと回路基板上の外部電極が
接する位置で半導体チップと回路基板間を固定する弾性
体の接着剤と、前記半導体チップを挟み込むように前記
放熱用フィンと前記回路基板とを固定する固定部材を設
けたことを特徴とするフリップチップボンディング型半
導体装置。4. A flip chip bonding type semiconductor device comprising a semiconductor chip having a fin for heat radiation provided on a surface opposite to an element forming surface of the semiconductor chip and a circuit board, wherein the semiconductor chip and the circuit board are flip chip bonded. A dummy electrode on either the element formation surface of the semiconductor chip or in the vicinity of the external electrode on the circuit board, and an elastic protrusion is provided between the external electrode on the side where the dummy electrode is provided and the dummy electrode. , Providing a conductive wire that connects the external electrode and the dummy electrode by looping over the elastic protrusion, and between the semiconductor chip and the circuit board at a position where the conductive wire and the external electrode on the circuit board are in contact with each other. An elastic adhesive for fixing and a fixing member for fixing the heat radiation fin and the circuit board so as to sandwich the semiconductor chip are provided. Flip chip bonding type semiconductor device according to. 【請求項５】 半導体チップの素子形成面を下にして回
路基板とボンディングするマイクロボンディング方法で
あって、 前記半導体チップの素子形成面上または、回路基板上の
外部電極の近傍のいづれか一方にダミーの電極を形成
し、そのダミー電極を設けた側の外部電極とダミーの電
極間に弾性体突起を形成し、その弾性体突起上を跨ぐよ
うにループさせて前記外部電極とダミー電極を導電性ワ
イヤで結線し、その導電性ワイヤと回路基板上または、
半導体チップ上の外部電極とを荷重圧着して固定部材で
固定することを特徴とするマイクロボンディング方法。5. A micro-bonding method for bonding a semiconductor chip with an element forming surface facing down to a circuit board, wherein a dummy is provided on either the element forming surface of the semiconductor chip or in the vicinity of an external electrode on the circuit board. Electrode is formed, an elastic protrusion is formed between the dummy electrode and the external electrode on the side where the dummy electrode is provided, and the external electrode and the dummy electrode are made conductive by looping over the elastic protrusion. Connect with a wire and connect it to the conductive wire on the circuit board, or
A micro-bonding method, characterized in that an external electrode on a semiconductor chip is pressure-bonded and fixed by a fixing member.
JP6050513A 1994-03-22 1994-03-22 Flip chip and microbonding method Withdrawn JPH07263490A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6050513A JPH07263490A (en) 1994-03-22 1994-03-22 Flip chip and microbonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6050513A JPH07263490A (en) 1994-03-22 1994-03-22 Flip chip and microbonding method

Publications (1)

Publication Number Publication Date
JPH07263490A true JPH07263490A (en) 1995-10-13

Family

ID=12861059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6050513A Withdrawn JPH07263490A (en) 1994-03-22 1994-03-22 Flip chip and microbonding method

Country Status (1)

Country Link
JP (1) JPH07263490A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6677677B2 (en) 2001-09-25 2004-01-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
KR100767193B1 (en) * 2006-03-13 2007-10-17 하나 마이크론(주) Line flip chip package and manufacturing method thereof
CN100444370C (en) * 2004-06-14 2008-12-17 精工爱普生株式会社 Semiconductor device, circuit substrate, electro-optic device and electronic appliance

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6677677B2 (en) 2001-09-25 2004-01-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
CN100444370C (en) * 2004-06-14 2008-12-17 精工爱普生株式会社 Semiconductor device, circuit substrate, electro-optic device and electronic appliance
KR100767193B1 (en) * 2006-03-13 2007-10-17 하나 마이크론(주) Line flip chip package and manufacturing method thereof

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