JPS615535A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS615535A JPS615535A JP59125151A JP12515184A JPS615535A JP S615535 A JPS615535 A JP S615535A JP 59125151 A JP59125151 A JP 59125151A JP 12515184 A JP12515184 A JP 12515184A JP S615535 A JPS615535 A JP S615535A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- terminal
- wiring sheet
- semiconductor chip
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［技術分野］
本発明は、半導体装置に係り、特に、外部回路と接続す
るための電極を数多く備えた半導体装置に適用して有効
な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and in particular, to a technique that is effective when applied to a semiconductor device equipped with a large number of electrodes for connection to an external circuit.
［背景技術］
半導体チップとパッケージ内部の配線とを電気的に接続
する技術手段として、半導体チップにボンディングバッ
トを設け、それを前記内部配線（リード）にボンディン
グワイヤによって接続することが行われている。[Background Art] As a technical means for electrically connecting a semiconductor chip and wiring inside a package, a bonding bat is provided on the semiconductor chip and connected to the internal wiring (lead) using a bonding wire. .
しかし、前記機械的に行うワイヤボンディング方式では
、ボンディングワイヤが２００本以上の多入出力点の集
積回路になると、ボンディングワイヤが相互に接近して
接触するために、この方式の技術手段を適用することに
は限界がある。However, in the mechanical wire bonding method, when an integrated circuit has multiple input/output points with more than 200 bonding wires, the bonding wires come close to each other and come into contact with each other, so the technical means of this method is not applied. There are limits to things.
そこで、前記ボンディングバットに代えて、ボンディン
グワイヤを介すことなく半導体チップとパッケージの内
部配線とを電気的に接続するために、半導体チップに半
田バンプ等の突起電極（以下、半田バンプという）を設
け、それを半導体チップを反転させることによってパッ
ケージ基板等の配線端子（バット）上に載置し、その後
に半田バンプに熱処理を施して溶融させ、半田バンプと
配線とを接続する方式（以下、フェイスダウン方式とい
う）が採用されている。Therefore, instead of the bonding bat, protruding electrodes such as solder bumps (hereinafter referred to as solder bumps) are installed on the semiconductor chip in order to electrically connect the semiconductor chip and the internal wiring of the package without using bonding wires. A method in which the semiconductor chip is placed on a wiring terminal (bat) of a package board, etc. by inverting the semiconductor chip, and then the solder bumps are heat-treated to melt and connect the solder bumps and the wiring (hereinafter referred to as The face-down method) is used.
かかる技術手段について検討した結果１本発明者は、前
記フェイスダウン方式では、半導体チップとパッケージ
との接触面積が半田バンプのみであるために、半導体チ
ップの活性領域等において発生する熱を効率よく放熱さ
せることができないという問題点を見い出した。なお、
半導体チップとリードとの接続技術、については１例え
ば、工業−交会、１９８０年１月１５日発行、ｒＩＣ４
ビ実装技術」 （日本マイクロエレクトロニクス協会編
）、ＰＩＯＩ−ＰＩ １４に示されている。As a result of studying such technical means, the present inventor discovered that in the face-down method, since the contact area between the semiconductor chip and the package is only the solder bumps, the heat generated in the active area of the semiconductor chip can be efficiently dissipated. I found a problem in that I couldn't do it. In addition,
Regarding connection technology between semiconductor chips and leads, see 1, for example, Kogyo-Kokai, published January 15, 1980, rIC4.
"Bi-mounting technology" (edited by Japan Microelectronics Association), PIOI-PI 14.
［発明の目的］
本発明の目的は、ワイヤボンディング方式と同等の低熱
抵抗で、かつ、フェイスダウン方式と同様に多入出力点
の電気接続をとることができる半導体装置を提供するこ
とにある。[Object of the Invention] An object of the present invention is to provide a semiconductor device which has a low thermal resistance equivalent to that of the wire bonding method and which can make electrical connections at multiple input/output points like the face-down method.
本発明の他の目的は、フェイスダウン方式と同様の技術
手段を採用した半導体装置において、半導体チップで発
生する熱を効率よく放熱することができる技術手段を提
供することにある。Another object of the present invention is to provide technical means that can efficiently dissipate heat generated in a semiconductor chip in a semiconductor device employing technical means similar to the face-down method.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
［発明の概要］
采願番；おいて開示される発明のうち、代表的なものの
概要を簡単に説明すれば、下記のとおりである。[Summary of the Invention] Among the inventions disclosed in the application number, a brief outline of typical inventions is as follows.
すなわち、フェイスダウン方式と同様の技術手段を採用
した半導体装置において、半導体チップ下面全面をパッ
ケージ基板の所定部に熱伝導率の良好な接着剤によって
固定し、半田バンプとパッケージ基板に設けられた端子
との電気的接続を、柔軟な特性を有する配線シートで接
続することにより、半導体チップで発生する熱を効率よ
く放熱させるようにしたものである。In other words, in a semiconductor device that employs a technical means similar to the face-down method, the entire bottom surface of the semiconductor chip is fixed to a predetermined part of the package substrate using an adhesive with good thermal conductivity, and solder bumps and terminals provided on the package substrate are By electrically connecting the semiconductor chip with a flexible wiring sheet, the heat generated in the semiconductor chip can be efficiently dissipated.
以下、本発明の構成について、実施例とともに説明する
。Hereinafter, the configuration of the present invention will be explained along with examples.
なお、実施例の全回において、同一機能を有するものは
同一符号を付け、そのくり返しの説明は＠″ａｔ、ａ・
１［実施例］
ｉ
第１図及び第２図は、本発明の一実施例の半導体装置を
説明するための図であり、第１図は、その半導体装置の
全体概略構成を示す断面図、第２図は、配線シートの構
成を示す平面図である。In addition, in all the examples, parts with the same function are given the same reference numerals, and the explanation of the repetition is @"at, a.
1 [Example]
i
1 and 2 are diagrams for explaining a semiconductor device according to an embodiment of the present invention, in which FIG. 1 is a cross-sectional view showing the overall schematic configuration of the semiconductor device, and FIG. 2 is a wiring diagram. FIG. 3 is a plan view showing the configuration of the sheet.
第１図において、１は半導体チップ、２は半田バンプ、
３はパッケージ基板４上に設けられた端子、５は接合剤
であり、金（Ａｕ）−シリコン（Ｓｉ）共晶合金又は半
田を用いる。、６はリード、７は配線を有する絶縁シー
ト（以下、単に、配線シートという）であり、第２図に
示すように。In FIG. 1, 1 is a semiconductor chip, 2 is a solder bump,
3 is a terminal provided on the package substrate 4, and 5 is a bonding agent, which is made of gold (Au)-silicon (Si) eutectic alloy or solder. , 6 is a lead, and 7 is an insulating sheet (hereinafter simply referred to as a wiring sheet) having wiring, as shown in FIG.
弾性とある程度の強度を有する柔軟なもので、かつ、耐
熱性（約２００乃至ａｏｏ’ｃに熱に耐えられるもの）
の材料、例えば、ポリイミドからなる絶縁シート８に端
子９を形成し、それに電気的に接続した金（Ａ ｕ ）
線等の配線１０を付着させて構成したものである。前記
端子９は、半導体チップ１上の半田バンプ２に対応する
位置に設けられている。また、配線１０の長さ寸法は、
前記端子９からパッケージ基板４上に設けられた配線の
終点の端子３までの距離を接続できる長さのものである
。１１はパッケージのキャップである。A flexible material that has elasticity and a certain degree of strength, and is heat resistant (able to withstand heat of approximately 200 to 200 cm).
A terminal 9 is formed on an insulating sheet 8 made of a material such as polyimide, and gold (A u ) is electrically connected to the terminal 9.
It is constructed by attaching wiring 10 such as a wire. The terminals 9 are provided at positions corresponding to the solder bumps 2 on the semiconductor chip 1. Moreover, the length dimension of the wiring 10 is
The length is such that the distance from the terminal 9 to the terminal 3 at the end point of the wiring provided on the package substrate 4 can be connected. 11 is a cap of the package.
次に、本実施例の半導体装置の製造方法を説明する
第３図乃至第６図は、本実施例の半導体装置の製造各工
程における概略構成を示す断面図である。Next, FIGS. 3 to 6, which explain the method of manufacturing the semiconductor device of this embodiment, are cross-sectional views showing the schematic structure of each step of manufacturing the semiconductor device of this embodiment.
本実施例の半導体装置は、第３図に示すように、半導体
チップ１の上部に端子として用いられる複数個の半田バ
ンプ２を形成した後に、半導体チップ１下面全面をパッ
ケージ基板４の所定部に接着剤５によって接着すること
により固定する。これ・により、消費電力の大きな半導
体チップ１から発生する熱を効率よく放熱できる。As shown in FIG. 3, in the semiconductor device of this embodiment, after forming a plurality of solder bumps 2 used as terminals on the upper part of the semiconductor chip 1, the entire lower surface of the semiconductor chip 1 is attached to a predetermined part of the package substrate 4. It is fixed by adhering with adhesive 5. This makes it possible to efficiently dissipate heat generated from the semiconductor chip 1, which consumes a large amount of power.
次に、第２図に示す配線シート７を用意する。Next, a wiring sheet 7 shown in FIG. 2 is prepared.
そして、第４図に示すように、配線シート７の端子９に
半田バンプ２を電気的に接続する。これは、配線シート
７を半田バンプ２上部に位置合せをして載置し、その後
に、熱処理を施すことにより半田バンプ２が溶融するの
で、それの表面張力によって自己整合的に接続できる。Then, as shown in FIG. 4, the solder bumps 2 are electrically connected to the terminals 9 of the wiring sheet 7. This is because the solder bumps 2 are melted by aligning and placing the wiring sheet 7 on top of the solder bumps 2 and then performing a heat treatment, so that the solder bumps 2 can be connected in a self-aligning manner due to their surface tension.
この方式の手段により、多くの半田バンプ２を有する半
導体チップ！でも問題なく正確に接続することができる
。By means of this method, a semiconductor chip having many solder bumps 2! However, you can connect it accurately without any problems.
次に、第５図に示すように、前記配線シート７の外周部
の配線１０の端子が、パッケージ４上に設けられている
端子３の位置の上にくるように位置合せを行い、配線１
０と端子とを加熱又は超音波を用いて接続する。この時
、第５図に示すように、位置合せの際に誤差があっても
配線シート７に少し余裕をもたせて無理な力が加わらな
いようにする。また、第６図に示すように、配線シート
ラと端子３との位置が多少ずれていても、前記配線シー
ト７の多少の余裕によるたるみと配線シート７の柔軟性
によって、この位置ずれを吸収してしまう。Next, as shown in FIG. 5, the terminals of the wiring 10 on the outer periphery of the wiring sheet 7 are aligned so that they are above the positions of the terminals 3 provided on the package 4, and the wiring 10 is aligned.
0 and the terminal using heating or ultrasonic waves. At this time, as shown in FIG. 5, even if there is an error in positioning, a little margin is provided on the wiring sheet 7 to prevent excessive force from being applied. Furthermore, as shown in FIG. 6, even if the position of the wiring sheet tracker and the terminal 3 is slightly misaligned, this misalignment can be absorbed by the slack of the wiring sheet 7 and the flexibility of the wiring sheet 7. It ends up.
前記配線１０ど端子３との接続が終ると、第１図に示す
ように、パッケージのキャップ１１により封止して半導
体装置が完成する。When the wiring 10 and the terminal 3 are connected, the package is sealed with a cap 11, as shown in FIG. 1, and the semiconductor device is completed.
また、一枚のパッケージ基板上に複数個のチップを塔載
し、同様の方法でボンディングすることもできる。It is also possible to mount a plurality of chips on one package substrate and bond them using the same method.
［効果］
以上説明したように１本願において開示された新規な技
術手段によれば、以下に述る効果を得ることができる。[Effects] As explained above, according to the novel technical means disclosed in this application, the following effects can be obtained.
（１）半導体チップの半田バンプとパッケージの配線端
子を、柔軟な弾性特性を有する絶縁シート上に配線を設
けた配線シートを介して電気的に接続し、半導体チップ
下面全面をパッケージ基板に接着することにより、半導
体チップで発生する熱の放熱効率を向上させることがで
きる。(1) The solder bumps of the semiconductor chip and the wiring terminals of the package are electrically connected via a wiring sheet in which wiring is provided on an insulating sheet with flexible elastic properties, and the entire bottom surface of the semiconductor chip is bonded to the package substrate. By doing so, it is possible to improve the efficiency of dissipating heat generated in the semiconductor chip.
（２）前記（１）の技術手段及びフェイスダウン方式と
同様のボンディング手段により、ワイヤ接触によるショ
ート不良がなくなるので、高密度のボンディングが可能
となる。(2) By using the technical means described in (1) above and a bonding means similar to the face-down method, short-circuit defects due to wire contact are eliminated, so high-density bonding is possible.
（３）前記（１）及び（２）により、配線密度の高い半
導体装置でも、パッケージの配線と半導体チップとを電
気的に接続するための工程を短縮できる。(3) According to (1) and (2) above, even in a semiconductor device with high wiring density, the process for electrically connecting the wiring of the package and the semiconductor chip can be shortened.
以上１本発明を実施例にもとすき具体的に説明したが１
本発明は前記実施例に限定されるもので
・（はなくその要旨を逸脱しない範囲において、種々
変形し得ることは勿論である。Above, the present invention was specifically explained using examples.
The present invention is not limited to the above embodiments.
・(Of course, various modifications can be made without departing from the gist of the invention.)
例えば、配線シート上の配線は多層配線にしてもよいこ
とはいうまでもない。For example, it goes without saying that the wiring on the wiring sheet may be multilayer wiring.
第１図及び第２図は、本発明の一実施例の半導体装置を
説明するための図であり、第１図は、その半導体装置の
全体概略構成を示す断面図、第２図は、配線シートの構
成を示す平面図、第３図乃至第６図は、本実施例の半導
体装置の製造各工程における概略構成を示す断面図であ
る。
図中、１・・・半導チップ、２・・・半田バンプ、３・
・・パッケージ基板上の配線端子、４・・・パッケージ
基板、５・・・接着剤、６・・・リード、７・・・配線
シート、８・・・絶縁シート、９・・・配線シート上の
配線端子、１０・・・配線シート上の配線、１１・・・
パッケージのキャップである。
代理人 弁理士 高 橋 明 夫
第 １ 図
第 ２ 図
第 ３ 図1 and 2 are diagrams for explaining a semiconductor device according to an embodiment of the present invention, in which FIG. 1 is a cross-sectional view showing the overall schematic configuration of the semiconductor device, and FIG. 2 is a wiring diagram. A plan view showing the structure of the sheet, and FIGS. 3 to 6 are cross-sectional views showing the schematic structure in each step of manufacturing the semiconductor device of this embodiment. In the figure, 1... semiconductor chip, 2... solder bump, 3...
...Wiring terminal on package board, 4...Package board, 5...Adhesive, 6...Lead, 7...Wiring sheet, 8...Insulating sheet, 9...On wiring sheet Wiring terminals, 10... Wiring on the wiring sheet, 11...
This is the cap of the package. Agent Patent Attorney Akio Takahashi Figure 1 Figure 2 Figure 3
Claims (1)
置において、前記半導体チップの表面に突起電極を設け
、該突起電極と電気的に接続する配線を有する絶縁シー
トを設けたことを特徴とする半導体装置。 ２、前記絶縁シートは、柔軟性を有する材料からなって
いることを特徴とする特許請求の範囲第１項記載の半導
体装置。 ３、前記絶縁シート上の配線を多層配線としたことを特
徴とする特許請求の範囲第１項又は第２項記載の半導体
装置。[Claims] 1. In a semiconductor device in which the entire back surface of a semiconductor chip is bonded to a substrate, a protruding electrode is provided on the surface of the semiconductor chip, and an insulating sheet having wiring electrically connected to the protruding electrode is provided. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the insulating sheet is made of a flexible material. 3. The semiconductor device according to claim 1 or 2, wherein the wiring on the insulating sheet is a multilayer wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59125151A JPS615535A (en) | 1984-06-20 | 1984-06-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59125151A JPS615535A (en) | 1984-06-20 | 1984-06-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS615535A true JPS615535A (en) | 1986-01-11 |
Family
ID=14903130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59125151A Pending JPS615535A (en) | 1984-06-20 | 1984-06-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS615535A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62211073A (en) * | 1986-03-12 | 1987-09-17 | 鐘淵化学工業株式会社 | Adsorbent for compliant component |
| JPS63272357A (en) * | 1987-04-30 | 1988-11-09 | Toyobo Co Ltd | Active complement adsorbing material and unit thereof |
| US7042104B2 (en) | 2003-08-13 | 2006-05-09 | Samsung Electronics Co., Ltd. | Semiconductor package using flexible film and method of manufacturing the same |
-
1984
- 1984-06-20 JP JP59125151A patent/JPS615535A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62211073A (en) * | 1986-03-12 | 1987-09-17 | 鐘淵化学工業株式会社 | Adsorbent for compliant component |
| JPS63272357A (en) * | 1987-04-30 | 1988-11-09 | Toyobo Co Ltd | Active complement adsorbing material and unit thereof |
| US7042104B2 (en) | 2003-08-13 | 2006-05-09 | Samsung Electronics Co., Ltd. | Semiconductor package using flexible film and method of manufacturing the same |
| US7396763B2 (en) | 2003-08-13 | 2008-07-08 | Samsung Electronics Co., Ltd. | Semiconductor package using flexible film and method of manufacturing the same |
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