JPS60157243A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60157243A JPS60157243A JP1371984A JP1371984A JPS60157243A JP S60157243 A JPS60157243 A JP S60157243A JP 1371984 A JP1371984 A JP 1371984A JP 1371984 A JP1371984 A JP 1371984A JP S60157243 A JPS60157243 A JP S60157243A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- terminals
- sealing resin
- sealed
- external terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、電力半導体モジュールなどに使用する半導
体装置の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in semiconductor devices used in power semiconductor modules and the like.
近年、電子機器の発達は著しく、その小形軽量化が急速
に進んでいる。これらの基をなすものは、半導体装置の
小形化および信頼性の同上によるものである。このなか
でも特にトランジスタの大電流容量化に伴う中容量の電
力用半導体装置としての応用が活発になっており、小形
軽量化を図ったパワーモジュールの分野への適用も多く
なってきて(する。2. Description of the Related Art In recent years, electronic devices have made remarkable progress, and their size and weight are rapidly decreasing. These factors are based on the miniaturization and reliability of semiconductor devices. Among these, applications are becoming more active as medium-capacity power semiconductor devices as the current capacity of transistors increases, and applications are also increasing in the field of power modules that are smaller and lighter.
コノよ5 ナバヮーモジュールの特長は軽量化と低価格
であるが、このためには樹脂封止形となる。Konoyo 5 Navawa module's features are its light weight and low price, and for this purpose it is resin-sealed.
パワーモジュールでは、複数個の半導体チップを組込ん
でおり、半導体チップ自体も大電流容量化に伴ない大き
くなるため、外形寸法は従来の樹脂封止形半導体装置に
比べ、かなり大きなものとなる。最近では、6素子入り
(トランジスタチップ。A power module incorporates a plurality of semiconductor chips, and the semiconductor chips themselves become larger as the current capacity increases, so the external dimensions are considerably larger than those of conventional resin-sealed semiconductor devices. Recently, 6-element (transistor chip) is used.
フライホイルタイオード、スピードアップダイオード各
1チップの6倍)のパワーモジュールも実用化されてい
る。このようなことから、パワーモジュールの樹脂封止
には従来のものとは異なった構造が必要となってくる。A power module with a flywheel diode and a speed-up diode (6 times each chip) has also been put into practical use. For this reason, resin sealing of power modules requires a structure different from conventional ones.
なかでも、最も問題となるのは外形が大きくなることに
より、容器内に充てんされる樹脂の体積が大きくなり半
導体チップの発熱による温度上昇で、封止樹脂の膨張や
温度低下時における収縮によるひずみがチップやアルミ
線に加わりチップの割れやアルミ線の断線の原因となる
ことがある。Among these, the biggest problem is that as the external size increases, the volume of resin filled in the container increases, and the temperature rises due to heat generation of the semiconductor chip, which causes distortion due to expansion of the sealing resin and contraction when the temperature drops. may be added to the chip and aluminum wire, causing cracking of the chip and breakage of the aluminum wire.
これらを防止するため、最近は、各器内部の下層には絶
縁材としてのゲル状軟質樹脂で封止してチップやアルミ
線部を囲み、上層には充てん後硬化することにより強度
の方が高くなる封止樹脂で封止し、引出された外部端子
の保持とモジュールの機械的保繰とを行う二重の樹脂封
止構造のものが増えてきた〇
この棟の従来の半導体装置を第1図に斜視図で示す。第
2図は第1図の要部を拡大して示す断面図である。これ
らの図はパワーモジュールに使用するトランジスタの場
合を示し、1は放熱板で、上面にアルミナ材などからな
る絶縁基板2が固着されている。この絶縁基板2上には
ベース電極3B、コレクタ電極3C,エミッタ電極3E
が固着されている。コレクタ電極3C上には、トランジ
スタ素子4が固着されている。また、ベース電極3Bか
ら外部端子14.エミッタ4極3Eから外部端子15へ
引出されている。トランジスタ素子4上面のペースボン
ディングバットおよびエミッタホンデインクバットと対
応するベース奄4113B。In order to prevent this, recently the lower layer inside each container is sealed with a gel-like soft resin as an insulating material to surround the chip and aluminum wire, and the upper layer is filled and hardened to make it stronger. The number of double resin-sealed structures that are sealed with an increasingly expensive sealing resin, retains the external terminals pulled out, and mechanically preserves the module is increasing. It is shown in perspective view in Figure 1. FIG. 2 is a sectional view showing an enlarged main part of FIG. 1. These figures show the case of a transistor used in a power module. Reference numeral 1 denotes a heat sink, and an insulating substrate 2 made of alumina material or the like is fixed to the upper surface. On this insulating substrate 2 are a base electrode 3B, a collector electrode 3C, and an emitter electrode 3E.
is fixed. A transistor element 4 is fixed on the collector electrode 3C. Also, from the base electrode 3B to the external terminal 14. It is drawn out to the external terminal 15 from the emitter 4-pole 3E. A base plate 4113B corresponding to the pace bonding butt and the emitter head ink butt on the upper surface of the transistor element 4.
エミッタ電ti3Bへは、それぞれアルミ線でボンディ
ング接続している。Each emitter voltage ti3B is connected by bonding with an aluminum wire.
次にや上記従来装置の組立てについて説明する。Next, the assembly of the above conventional device will be explained.
まず、絶縁基板20両面に所要はんだ付は箇所にメタラ
イズ層を施す。放熱板1上にはんだ薄片を介して絶縁基
板2を置く。次いで、この絶縁基板2上にそれぞれはん
だ薄片を介しコレクタkjt413C,ベース電!3B
、エミッタ電極3Eを載せる。First, a metallized layer is applied to both sides of the insulating substrate 20 at the required soldering locations. An insulating substrate 2 is placed on a heat sink 1 with a thin solder piece interposed therebetween. Next, the collector kjt413C, the base electric! 3B
, place the emitter electrode 3E.
さらに、コレクタ電極3C上にはんだ薄片を介しトラン
ジスタ素子4を配置する。このように、各部品が載せら
れた放熱板1を組立設備の熱板(図示せず)上に載せ、
加熱して各部品をはんだ融着する。次に、トランジスタ
素子4上面のポンティングパットと対応する各電極3B
、3C,3Eとをそれぞれアルミ線によりワイヤポンド
する。Furthermore, the transistor element 4 is placed on the collector electrode 3C via a thin solder piece. In this way, the heat sink 1 on which each component is mounted is placed on the heat plate (not shown) of the assembly equipment,
Heat and solder fuse each part. Next, each electrode 3B corresponding to the ponting pad on the upper surface of the transistor element 4
, 3C, and 3E are each wire-pounded using aluminum wire.
各電極3B、3C,3にの先端を上方に曲げ起こし、電
極の外部端子9〜15にはんだ付は等により接続し形成
する。次いで、放熱板1上に外装容器5を接着剤等で接
着し、外装容器5内部の下層には絶縁材としてのゲル状
封止樹脂6で封止し、外装容器5の上層には各外部端子
9〜15を固定のため硬化封止樹脂1で封止して製品が
完成される。The tips of each electrode 3B, 3C, 3 are bent upward and connected to external terminals 9 to 15 of the electrodes by soldering or the like. Next, the outer container 5 is glued onto the heat dissipation plate 1 with adhesive or the like, the lower layer inside the outer container 5 is sealed with a gel-like sealing resin 6 as an insulating material, and the upper layer of the outer container 5 is sealed with each external The product is completed by sealing the terminals 9 to 15 with a hardened sealing resin 1 for fixation.
ところで、上記従来の半導体装置は、外部端子9〜15
の位置決めが非常に困難であり、位置決めのための外部
端子9〜15の位置修正に多くの時間を必要とし、また
、治工具等を使用しなければ位置決めができず多くの作
業時間がかかる等の欠点があった。By the way, the conventional semiconductor device described above has external terminals 9 to 15.
It is very difficult to position the external terminals 9 to 15, and it takes a lot of time to correct the positions of the external terminals 9 to 15. Also, positioning cannot be done without using jigs and tools, which takes a lot of work time. There was a drawback.
この発明は、上記の欠点を解消するためになされたもの
で、外装容器の上部に、外部端子が確実に所定の位置に
来るように外装容器上部内側に穴または切欠部を設ける
ことにより外部でのプリント配線等が容易にできる半導
体装置を提供することを目的としている。This invention was made in order to eliminate the above-mentioned drawbacks, and by providing a hole or a notch inside the upper part of the outer container to ensure that the external terminal is in a predetermined position. The object of the present invention is to provide a semiconductor device that can be easily printed wiring.
〔発明の実施例J 以下、この発明について説明する。[Embodiment J of the invention This invention will be explained below.
第3図、第4図はこの発明の一実施例を示すもので、第
3図はモジュールに使用するトランジスタパワーの半導
体装置を示す斜視図、第4図は萬3図の要部を拡大して
示す断面図である。Figures 3 and 4 show an embodiment of the present invention. Figure 3 is a perspective view showing a transistor-powered semiconductor device used in a module, and Figure 4 is an enlarged view of the main parts of Figure 3. FIG.
これらの図において、第1図、第2図と同一符号は同一
部分を示し、8は前記外装容器5の上部内側で各外部端
子9〜15が確実に所定の位置に位置決めをするための
穴で、下方に向ってテーパが形成されている。In these figures, the same reference numerals as in FIGS. 1 and 2 indicate the same parts, and 8 is a hole for ensuring that each external terminal 9 to 15 is positioned at a predetermined position inside the upper part of the outer container 5. A taper is formed downward.
次に、上記半導体装置の組立てについて説明する。Next, assembly of the above semiconductor device will be explained.
第4図に示すごとく放熱板1上にはんだ薄片を介して絶
縁基板2を置く。次いで、この絶縁基板2上にそれぞれ
はんだ薄片を介しコレクタ電#3C,ベース電極3B、
エミッタ電極3Eを載せ、さらに、コレクタ電極3C上
にはんだ薄片を介しトランジスタ素子4を配置する。次
に、トランジスタ素子4上面のポンティングパッドと対
応する各電極3B、3C,3Bとをそれぞれアルミ線に
よりワイヤポンドする。各@m3B、3C,3Bの先端
を上方に曲げ起こし各電極3B、 30.3Hの外部端
子9〜15にはんだ付は等により接続し形成する。次い
で、放熱板1上に外装容器5を接着剤等で接着する場合
は、外装容器5の穴8に外部端子9〜15を挿入してか
ら接着する。その後、外装容器5内部の下層にをまゲル
状封止樹脂6.上層には外部端子9〜15を固定するた
め硬化封止樹脂Tで封止し製品を完成させる。As shown in FIG. 4, an insulating substrate 2 is placed on a heat sink 1 with a thin solder piece interposed therebetween. Next, collector electrode #3C, base electrode 3B, and
An emitter electrode 3E is placed on the emitter electrode 3E, and a transistor element 4 is further placed on the collector electrode 3C via a thin solder piece. Next, each electrode 3B, 3C, 3B corresponding to the ponting pad on the upper surface of the transistor element 4 is wire bonded with an aluminum wire. The tips of each @m3B, 3C, and 3B are bent upward and connected to the external terminals 9 to 15 of each electrode 3B and 30.3H by soldering or the like. Next, when bonding the outer container 5 onto the heat sink 1 with an adhesive or the like, the external terminals 9 to 15 are inserted into the holes 8 of the outer container 5 and then bonded. Thereafter, the gel-like sealing resin 6. is added to the lower layer inside the outer container 5. The upper layer is sealed with a hardened sealing resin T to fix the external terminals 9 to 15 to complete the product.
第5図はこの発明の他の実施例を示す要部の斜視図であ
る。この実施例では第3図、第4図の実施例における穴
8に代えて切欠部8′を用いたものである。作用効果は
穴8の場合とはとんと同一であるが、外部端子14.1
5の挿通が穴8より切欠部ぎの方が容易である。FIG. 5 is a perspective view of essential parts showing another embodiment of the invention. In this embodiment, a notch 8' is used in place of the hole 8 in the embodiments of FIGS. 3 and 4. The effect is exactly the same as that for hole 8, but the external terminal 14.1
5 is easier to insert through the notch than through the hole 8.
なお、外部端子9〜15の断面形状は、円形。Note that the external terminals 9 to 15 have a circular cross-sectional shape.
矩形等任意でよい。Any shape such as a rectangle may be used.
以上説明したようにこの発明は、半導体装置の上部内側
で各外部端子を所定の位置に位置決めするための穴また
は切欠部を設けたので、各外部端子の位置が正確に位置
決めされる。このため、パワーモジュールを使用したイ
ンバータセット等を組立てる場合、プリント配線等の利
用ができると同時に、外部端子の接続も一体化ができ組
立て工ら
数を直ことができる等の洞点を有する。As described above, the present invention provides holes or cutouts for positioning each external terminal at a predetermined position inside the upper part of the semiconductor device, so that each external terminal can be accurately positioned. Therefore, when assembling an inverter set using the power module, it is possible to use printed wiring, etc., and at the same time, the connection of external terminals can be integrated, reducing the number of assembly steps.
、4、図面の簡単な説明
第1図、第2図は従来の半導体装置を示す斜視図と、第
1図の要部を拡大して示す断面図、第3図、第4図はこ
の発明の一実施例を示−r斜視図と第3図の要部を拡大
して示す断面図、第5図はこの発明の他の実施例を示す
要部の斜視図である。, 4. Brief description of the drawings FIGS. 1 and 2 are perspective views showing a conventional semiconductor device, and a sectional view showing an enlarged main part of FIG. 1. FIGS. FIG. 5 is a perspective view showing an embodiment of the present invention and a sectional view showing an enlarged main part of FIG. 3, and FIG. 5 is a perspective view of the main part showing another embodiment of the present invention.
図中、1は放熱板、2は絶縁基板、3Bはベース電極、
3Cはコレクタ電極、3Bはエミッタ電極、4はトラン
ジスタ素子、5は外装容器、6はグル状封止樹脂、7は
硬化封止樹脂、8は穴、ビは切欠部、9j 10,11
,12,13,14゜15は外部端子である。In the figure, 1 is a heat sink, 2 is an insulating substrate, 3B is a base electrode,
3C is a collector electrode, 3B is an emitter electrode, 4 is a transistor element, 5 is an outer container, 6 is a glue-shaped sealing resin, 7 is a hardened sealing resin, 8 is a hole, B is a notch, 9j 10, 11
, 12, 13, 14, and 15 are external terminals.
なお、図中の同一符号は同一または相当部分を示す。Note that the same reference numerals in the figures indicate the same or corresponding parts.
代理人 大岩増雄 (外2名) 第1図 1q 第2図 (3C,3E) 第3図 第5図 第4図Agent: Masuo Oiwa (2 others) Figure 1 1q Figure 2 (3C, 3E) Figure 3 Figure 5 Figure 4
Claims (1)
の電極を配置して固層し、これらの電極のうち所定のW
tax上に半導体チップを装着し、前記各所定の電極か
ら上方に外部端子を引出し、前i己放熱板上の周縁部に
沿って固着され絶縁相かうなる外装容器の下層にはグル
状封止樹脂を封入し、前記外装容器の上層には前記外部
端子固定のための硬化封止樹脂で封止した半導体装置に
おいて、前記外装容器の上部内側に前記各外部端子を所
定の位置に位置決めをするための穴または切欠部を設け
たことを特徴とする半導体装置。An insulating substrate is fixed on a heat sink, and a few types of electrodes are arranged and fixed on this insulating substrate, and a predetermined W of these electrodes is
A semiconductor chip is mounted on the tax, external terminals are drawn upward from each of the predetermined electrodes, and a glue-like seal is attached to the lower layer of the outer container, which is fixed along the periphery of the heat sink and insulated. In a semiconductor device in which a resin is sealed and the upper layer of the outer container is sealed with a hardened sealing resin for fixing the external terminals, each of the external terminals is positioned at a predetermined position inside the upper part of the outer container. 1. A semiconductor device characterized by having a hole or cutout for the purpose.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1371984A JPS60157243A (en) | 1984-01-25 | 1984-01-25 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1371984A JPS60157243A (en) | 1984-01-25 | 1984-01-25 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60157243A true JPS60157243A (en) | 1985-08-17 |
JPH0228261B2 JPH0228261B2 (en) | 1990-06-22 |
Family
ID=11841048
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1371984A Granted JPS60157243A (en) | 1984-01-25 | 1984-01-25 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60157243A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6169844U (en) * | 1984-10-12 | 1986-05-13 | ||
JPH02114981U (en) * | 1989-03-03 | 1990-09-14 | ||
EP0438165A2 (en) * | 1990-01-18 | 1991-07-24 | Kabushiki Kaisha Toshiba | Semiconductor device parts |
US5285106A (en) * | 1990-01-18 | 1994-02-08 | Kabushiki Kaisha Toshiba | Semiconductor device parts |
WO1998052221A1 (en) * | 1997-05-09 | 1998-11-19 | Eupec Europäische Gesellschaft Für Leistungshalbleiter Mbh + Co. Kg | Power semiconductor module with ceramic substrate |
JP2014143373A (en) * | 2013-01-25 | 2014-08-07 | Mitsubishi Electric Corp | Semiconductor device and method for manufacturing semiconductor device |
DE112008003425B4 (en) | 2007-12-20 | 2023-08-31 | Aisin Aw Co., Ltd. | Process for manufacturing a semiconductor device |
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JPS5192064A (en) * | 1975-02-11 | 1976-08-12 | ||
JPS5412386A (en) * | 1977-06-28 | 1979-01-30 | Teijin Ltd | Isocarbostyril derivative |
JPS5435666A (en) * | 1977-08-25 | 1979-03-15 | Fujitsu Ltd | Timing extraction system |
JPS56145850U (en) * | 1980-04-02 | 1981-11-04 | ||
JPS57177547A (en) * | 1981-04-08 | 1982-11-01 | Thomson Csf | Case for middle output semiconductor element and method of producing same |
JPS587346A (en) * | 1981-07-07 | 1983-01-17 | 株式会社東海理化電機製作所 | Plastic laminate |
-
1984
- 1984-01-25 JP JP1371984A patent/JPS60157243A/en active Granted
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5192064A (en) * | 1975-02-11 | 1976-08-12 | ||
JPS5412386A (en) * | 1977-06-28 | 1979-01-30 | Teijin Ltd | Isocarbostyril derivative |
JPS5435666A (en) * | 1977-08-25 | 1979-03-15 | Fujitsu Ltd | Timing extraction system |
JPS56145850U (en) * | 1980-04-02 | 1981-11-04 | ||
JPS57177547A (en) * | 1981-04-08 | 1982-11-01 | Thomson Csf | Case for middle output semiconductor element and method of producing same |
JPS587346A (en) * | 1981-07-07 | 1983-01-17 | 株式会社東海理化電機製作所 | Plastic laminate |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6169844U (en) * | 1984-10-12 | 1986-05-13 | ||
JPH0342685Y2 (en) * | 1984-10-12 | 1991-09-06 | ||
JPH02114981U (en) * | 1989-03-03 | 1990-09-14 | ||
JPH0611537Y2 (en) * | 1989-03-03 | 1994-03-23 | 新電元工業株式会社 | Resin-sealed electronic circuit device |
EP0438165A2 (en) * | 1990-01-18 | 1991-07-24 | Kabushiki Kaisha Toshiba | Semiconductor device parts |
US5285106A (en) * | 1990-01-18 | 1994-02-08 | Kabushiki Kaisha Toshiba | Semiconductor device parts |
WO1998052221A1 (en) * | 1997-05-09 | 1998-11-19 | Eupec Europäische Gesellschaft Für Leistungshalbleiter Mbh + Co. Kg | Power semiconductor module with ceramic substrate |
DE112008003425B4 (en) | 2007-12-20 | 2023-08-31 | Aisin Aw Co., Ltd. | Process for manufacturing a semiconductor device |
JP2014143373A (en) * | 2013-01-25 | 2014-08-07 | Mitsubishi Electric Corp | Semiconductor device and method for manufacturing semiconductor device |
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JPH0228261B2 (en) | 1990-06-22 |
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