KR20220110673A - Semiconductor package and fabricating method thereof - Google Patents

Abstract

A semiconductor device structure and a method for manufacturing a semiconductor device are provided. As a non-limiting example, various aspects of the present invention provide various semiconductor package structures including a thin and fine pitch redistribution structure, and methods for manufacturing the same. The semiconductor device of the present invention includes: a front redistribution structure; a semiconductor die; a laminated component interconnect structure; an encapsulating material; and a rear redistribution structure.

Description

Semiconductor package and its manufacturing method TECHNICAL FIELD

This application is filed on January 29, 2013, and is entitled "Semiconductor Device and Method of Manufacturing Semiconductor Device" in US Patent Application Serial Nos. 13/753,120; U.S. Patent Application No. 13/863,457, filed April 16, 2013, and entitled "Semiconductor Device and Method of Manufacturing Same;" U.S. Patent Application Serial No. 14/083,779, filed November 19, 2013, and entitled "Semiconductor Device with Deep Wells Without Through Silicon Vias;" U.S. Patent Application No. 14/218,265, filed March 18, 2014, and entitled "Semiconductor Device and Method of Making the Same"; U.S. Patent Application No. 14/313,724, filed June 24, 2014, and entitled "Semiconductor Device and Method of Manufacturing Same;" US Patent Application No. 14/444,450, filed July 28, 2014, and entitled "Semiconductor Device With Thin Redistribution Layers;" US Patent Application Serial No. 14/524,443, filed October 27, 2014, and entitled "Semiconductor Device with Reduced Thickness;" US Patent Application No. 14/532,532, filed on November 4, 2014, and entitled "Interposer, Method of Manufacturing Same, Semiconductor Package Using Same, and Method of Manufacturing Semiconductor Package;" US Patent Application Serial No. 14/546,484, filed November 18, 2014, and entitled “Semiconductor Device with Reduced Warpage;” and U.S. Patent Application No. 14/671,095, filed March 27, 2015, entitled “Semiconductor Device and Method of Manufacturing Same;” The entire contents of each of which are herein incorporated by reference.

Current semiconductor packages and methods for forming semiconductor packages are unsuitable, for example, resulting in excessive cost, reduced reliability, or too large package size. Additional limitations and disadvantages of conventional and traditional approaches will become apparent to those skilled in the art through a comparison of the present invention with such approaches as described in the remainder of this application with reference to the drawings.

Various aspects of the present invention provide a semiconductor device structure and a method for manufacturing a semiconductor device. As non-limiting examples, various aspects of the present disclosure provide various semiconductor package structures including a thin fine-pitch redistribution structure, and methods for manufacturing the same.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain various principles of the invention.
1A-1J are cross-sectional views illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present invention.
2 is a flow diagram of an exemplary method of manufacturing a semiconductor package in accordance with various aspects of the present invention.
3A and 3B are cross-sectional views illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present invention.
4A-4D are cross-sectional views illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present disclosure.
5A-5F are cross-sectional views illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present invention.
6A-6D are cross-sectional views illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present invention.
7A-7L are cross-sectional views illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present invention.
8 is a flow diagram of an exemplary method of manufacturing a semiconductor package in accordance with various aspects of the present invention.
9 is a cross-sectional view illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present disclosure.
10A-10B, cross-sectional views illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present invention.
11A-11D are cross-sectional views illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present disclosure.
12A-12B are cross-sectional views illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present invention.
13 is a cross-sectional view illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present disclosure.
14 is a cross-sectional view illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present disclosure.
15 is a cross-sectional view illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present disclosure.
16 is a cross-sectional view illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present disclosure.

The following discussion presents various aspects of the invention by providing examples of these. These examples are non-limiting, and thus, the scope of the various aspects of the invention need not be limited by any specific features of the examples provided. In the description below, the phrases "example", "example (e.g.)" and "exemplary" are generally synonymous with "by way of example and without limitation", "such as and not limitation", and the like.

As used herein, “and/or” means one or more of the lists linked to “and/or”. For example, "x and/or y" means any element of a set of three elements {(x), (y), (x, y). In other words, “x and/or y” means “one or both of x and y”. As another example, "x, y, and/or z" is a set of seven elements {(x), (y), (z), (x, y), (x, z), (y, z), ( x, y, z)} means any element. In other words, “x, y and/or z” means “one or more of x, y and z.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used herein, the singular form is intended to include the plural form unless the content clearly dictates otherwise. As used herein, "comprises", "includes", "comprising", "including", "has", "have" , “having” and the like refer to features, integers, steps, operations, components, and/or parts, and to features, integers, steps, operations, components, parts. It will be understood that this does not exclude the presence or addition of one or more of these and/or groups thereof.

Although the terms first, second, etc. may be used herein to describe various elements, it will be understood that these elements should not be limited to these terms. These terms are used to distinguish one component from another. Thus, for example, a first component, a first component, or a first section to be described below may be referred to as a second component, a second component, or a second section without departing from the teachings of the present invention. Similarly, various spatial terms such as "upper", "lower", "side", etc. may be used to distinguish one component from another in a relative manner. However, the parts may be positioned in other ways, for example, with their “top” side facing horizontally and their “side” side facing vertically, without departing from the teachings of the present invention. It should be understood that the semiconductor device may be positioned sideways for viewing.

Various aspects of the present invention provide a semiconductor device or package and a method of forming (or manufacturing) the same, which reduces cost, increases reliability, and/or increases manufacturing performance of the semiconductor device.

These and other aspects of the invention will be described or will become apparent from the following description of various exemplary embodiments. To enable those skilled in the art to readily practice the various aspects, various aspects of the present invention will now be described with reference to the accompanying drawings.

1A-1J are cross-sectional views illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present invention. The structures shown in Figures 1a-1j are the structures shown in Figures 3a-3b, 4a-4d, 5a-5f, 6a-6d, 7a-7l, 9, 10a-10b, 11a-11d, 12a-12b, 13, 14, 15, and 16 may share any or all features with similar structures. 2 is a flow diagram of an exemplary method 200 of manufacturing a semiconductor package, in accordance with various aspects of the present invention. 1A-1J depict an exemplary semiconductor package at various steps (or blocks) of method 200 of FIG. 2 , for example. 1A-1J and 2 are discussed together. It should be noted that the order of the exemplary blocks of method 200 may be varied without departing from the scope of the present invention.

Exemplary method 200 may include, at block 205 , preparing a logic wafer for processing (e.g., packaging). Block 205 may include, in a non-limiting manner presented herein, preparing a logic wafer for processing in any of a variety of manners.

For example, block 205 may include receiving a logic wafer, such as from a shipping supplier, an upstream process on a manufacturing floor, or the like. A logic wafer may include, for example, a semiconductor wafer comprising a plurality of active semiconductor dies. A semiconductor die may include, for example, a processor die, a memory die, a programmable logic die, an application specific integrated circuit die (ASIC), a general die, and the like.

Block 205 may include, for example, forming conductive interconnect structures over a logic wafer. Such conductive interconnect structures may include, for example, conductive pads, lands, bumps or balls, conductive pillars, and the like. The forming step may include, for example, attaching preformed interconnect structures to a logic wafer, plating interconnect structures on the logic wafer, and the like.

As an exemplary embodiment, the conductive structures may include conductive pillars comprising copper and/or nickel, and may include a solder cap (e.g., tin and/or silver). For example, the conductive structures may include conductive pillars, and the conductive pillars may include: (a) (i) a titanium-tungsten (TiW) layer formed by sputtering (which may be referred to as a "seed layer"), and (ii) a kappa (Cu) layer on the titanium-tungsten layer formed by sputtering; Nickel formed on the kappa pillars having an under bump metal (“UBM”), (b) a kappa pillar formed on the UBM by electroplating, and (c) a solder layer formed on the kappa pillar or a solder layer formed on the nickel layer. floor.

Further, as an exemplary embodiment, the conductive structures may include lead and/or lead-free wafer bumps. For example, lead-free wafer bumps (or interconnect structures) may be formed, at least in part, by a process as follows. (a) (i) formation of titanium (Ti) or titanium-tungsten (TiW) by sputtering, (ii) formation of a kappa (Cu) layer on titanium or titanium-tungsten by sputtering, (iii) and electroplating Formation of under bump metal (UBM) by forming nickel (Ni) on the kappa layer by (b) forming a lead-free solder material on the nickel layer of the UBM structure by electrolytic plating, A composition of silver (Ag) having 1 wt% to 4 wt% and the remainder of the composition by weight being tin (Sn).

Block 205 may include, for example, performing partial or complete thinning (e.g., grinding, etching, etc.) of the logic wafer. Block 205 may also include, for example, dicing the logic wafer into separate dies or into die sets for side attachment. Block 205 may also include receiving the logic wafer from an upstream manufacturing station or proximate to a manufacturing facility, or from another geographic location, or the like. The logic wafer, for example, may already be prepared or additional preparation steps may be performed.

In general, block 205 may include preparing a logic wafer for processing (e.g., for packaging). Accordingly, the scope of the present invention should not be limited by the characteristics of a particular type of logic wafer and/or die process.

Exemplary method 200 includes, at block 210 , preparing a carrier, substrate, or wafer. The prepared (or received) wafer may be referred to as a redistribution structure wafer or RD wafer.

The RD wafer may include, for example, an interposer wafer, a wafer of a package substrate, and the like. The RD wafer may include, for example, a redistribution structure formed on a semiconductor (e.g., silicon) wafer (e.g., on a die-by-die basis). An RD wafer may include, for example, electrical pathways as well as electronic devices (e.g., semiconductor devices). An RD wafer may also include, for example, passive electronic devices as well as active semiconductor devices. For example, an RD wafer may include one or more conductive layers or traces formed or connected (e.g., directly or indirectly) on a substrate or carrier. Examples of a carrier or substrate may include a semiconductor (e.g., silicon) wafer or glass substrate. Examples of processes used to form conductive layers (e.g., kappa, aluminum, tungsten, etc.) on a semiconductor wafer include using semiconductor wafer fabrication processes, which also include back end of line (BEOL) herein. ) can be referred to as a process. As an exemplary embodiment, the conductive layers may be deposited on or along the substrate using a sputtering and/or electrolytic plating process. The conductive layers may be referred to as redistribution layers. The redistribution layers may be used to route an electrical signal between two or more electrical connection structures or to route electrical connection structures in a wide or narrow pitch.

As an illustrative embodiment, various regions of a redistribution structure (e.g., interconnect structures (e.g., lands, traces, etc.)) that may be attached to (electronic devices) are of sub-micron pitch (or center-to-center). spacing) and/or with a pitch of less than 2 microns. In various other embodiments, pitches of 2-5 microns may be used.

As an exemplary embodiment, the silicon wafer on which the redistribution structure is formed may include a lower grade of silicon than may be suitably used to form a semiconductor die that is ultimately attached to the redistribution structure. As another example, the silicon wafer may be a silicon wafer recovered from a failed semiconductor device wafer fabrication process. As a further exemplary embodiment, the silicon wafer may include a layer of silicon that is thinner than may be suitably used to form a semiconductor die that is ultimately attached to the redistribution structure. Block 210 may also include receiving the RD wafer from an upstream manufacturing station or proximate to the manufacturing facility, or from another geographic location, or the like. The RD wafer, for example, may already be prepared or additional preparation steps may be performed.

1A provides an exemplary diagram of various aspects of block 210 . Referring to FIG. 1A , the RD wafer 100A includes, for example, a support layer 105 (e.g., a silicon or other semiconductor layer, a glass layer, etc.). The redistribution (RD) structure 110 may be formed on the support layer 105 . The RD structure 110 may include, for example, a base dielectric layer 111 , a first dielectric layer 113 , first conductive traces 112 , a second dielectric layer 116 , second conductive traces 115 , and interconnect structures 117 .

The base dielectric layer 111 may be over the support layer 105 , for example. The base dielectric layer 111 may include, for example, an oxide film, a nitride film, or the like. The base dielectric layer 111 may be formed to a standard specification and/or may be natural, for example. The dielectric layer 111 may be referred to as a passivation layer. The dielectric layer 111 may be or include, for example, a silicon dioxide layer formed using a low pressure chemical vapor deposition (LPCVD) process.

The RD wafer 100A may also include, for example, first conductive traces 112 and a first dielectric layer 113 . The first conductive traces 112 may include, for example, a deposited conductive metal (eg, kappa, aluminum, tungsten, etc.). The conductive traces 112 may be formed by sputtering and/or electrolytic plating. Conductive traces 112 may be formed, for example, with a sub-micron or sub-two-micron pitch (or center-to-center spacing). The first dielectric layer 113 may include, for example, an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In various embodiments, the dielectric layer 113 may be formed prior to the first conductive traces 112 , eg, formed with openings in which the first conductive traces 112 or portions thereof are formed. Notice that the area is filled. As an exemplary embodiment, for example kappa conductive traces, a dual damascene process may be used to deposit the traces.

As another assembly, the first dielectric layer 113 may include an organic dielectric material. For example, the first dielectric layer 113 may include bismaleimidetriazine (BT), phenolic resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), epoxy, and equivalents thereof. and compounds thereof, but embodiments of the present invention are not limited thereto. The organic dielectric material may be formed in any of a variety of ways, for example, chemical vapor deposition (CVD). As another such assembly, the first conductive traces 112 may be, for example, a 2-5 micron pitch (or center-to-center spacing).

The RD wafer 100A may also include, for example, second conductive traces 115 and a second dielectric layer 116 . The second conductive traces 115 may include, for example, a deposited conductive material (e.g., kappa, etc.). The second conductive traces 115 may be connected to each of the first conductive traces 112 through, for example, respective conductive vias 114 (e.g., in the first dielectric layer 113 ). . The second dielectric layer 116 may include, for example, an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). As another assembly, the second dielectric layer 116 may include an organic dielectric material. For example, the second dielectric layer 116 may include bismaleimidetriazine (BT), phenolic resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), epoxy, and equivalents thereof. and compounds thereof, but embodiments of the present invention are not limited thereto. The second dielectric layer 116 may be formed using, for example, a CVD process, but the scope of the present invention is not limited thereto.

Although two sets of dielectric layers and conductive traces are shown in FIG. 1A , it should be understood that the RD structure 110 of the RD wafer 100A may include any number of such layers and traces. For example, RD structure 110 may include only one dielectric layer and/or one set of conductive traces, three sets of dielectric layers and/or conductive traces, and/or the like.

In conjunction with the logic wafer preparation step at block 205 , block 210 includes interconnect structures (e.g., conductive bumps, conductive balls, conductive pillars, conductive lands or pads) on the surface of RD structure 110 . etc.) may be included. An example of such interconnect structures 117 , in which RD structure 110 includes interconnect structures 117 , is shown in FIG. 1A , which is formed on the front (or top) side of RD structure 110 . and electrically connected to respective second conductive traces 115 through conductive vias in the second dielectric layer 116 . These interconnect structures 117 may be used, for example, to connect the RD structure 110 to various electronic components (e.g., active semiconductor components or die, passive components, etc.).

The interconnect structures 117 may include, for example, any of a variety of conductive materials (e.g., one or a combination of kappa, nickel, gold, etc.). The interconnect structures 117 may also include, for example, solder.

In general, block 210 includes preparing a redistribution structure wafer (RD wafer). Accordingly, the scope of the present invention should not be limited to the features of any particular manner of carrying out such preparations.

The exemplary method 200 includes, at block 215 , forming interconnect structures (e.g., through mold via (TMV) interconnect structures) on the RD wafer. Block 215 includes forming such interconnect structures in any of a variety of ways.

The interconnect structures may include any of a variety of features. For example, interconnect structures include solder balls or bumps, multi-ball solder columns, elongated solder balls, metal (e.g., kappa) core balls with a solder layer formed along the metal core, plated pillar structures (e.g., kappa pillars, etc.), wire structures (e.g., wire bonding wires), and the like.

The interconnect structures may have any of a variety of dimensions. For example, the interconnect structures may extend from the RD wafer to a height less than the height of electronic components connected to the RD wafer (e.g., at block 220 ). Also for example, interconnect structures may extend from the RD wafer to a height greater than or equal to the height of electronic components connected to the RD wafer. The importance of these relative heights will become apparent in the discussion herein (e.g., in the discussion of mold thinning, package stacking, top substrate attachment, top redistribution structure formation, etc.). The interconnect structures may also be formed at various pitches (center-to-center spacing), for example. For example, interconnect structures (e.g., conductive posts or pillars) may be plated and/or bonded to 150-250 micron pitch or less. Also for example, interconnect structures (e.g., stretched and/or metal filled solder structures) may be attached at a pitch of 250-350 microns or less. Additionally, for example, interconnect structures (e.g., solder balls) can be attached with a pitch of 350-450 microns or less.

Block 215 includes attaching the interconnect structures in any of a variety of ways. For example, block 215 may include reflowing and attaching interconnect structures on the RD wafer, plating the interconnect structures on the RD wafer, wire bonding the interconnect structures on the RD wafer, conductive attaching the performed interconnect structures to the RD wafer with epoxy; and the like.

1B provides various aspects of block 215, for example, aspects of forming an interconnect structure. As an exemplary assembly 100B, interconnect structures 121 (e.g., solder balls) are connected to an RD structure 110 of an RD wafer 100A (e.g., reflow attach, solder ball drop process). attachment, etc.).

Although two rows of interconnect structures 121 are shown, various embodiments may include a single column, three columns, or any number of columns. As discussed herein, various exemplary embodiments may not have such interconnect structures 121 and thus block 215 may be included in exemplary method 200 .

Note that although in the exemplary method 200, block 215 is performed after the wafer molding operation in block 230, interconnect structures may instead be formed after the wafer molding operation (e.g., in the mold material). After forming the opening vias, such openings are filled with conductive materials). Also note that block 215 may be performed at block 220 after the die attach operation as shown in FIG. 2 , for example, instead of before die attach.

In general, block 215 includes forming interconnect structures on the RD wafer. Accordingly, the scope of the present invention should not be limited by the features of a particular type of interconnect structure or by the features of any particular manner of forming such interconnect structures.

Exemplary method 200 may include, at block 220 , attaching one or more semiconductor dies to an RD structure (e.g., of an RD wafer). Block 220 includes attaching a die to the RD structure in any of a variety of ways, including non-limiting examples provided herein.

A semiconductor die may include features of any of the various types of semiconductor die. For example, semiconductor dies include processor dies, memory dies, application specific integrated circuit dies, general logic dies, active semiconductor components, and the like. Note that passive components may also be attached at block 220 .

Block 220 may include attaching a semiconductor die (e.g., as prepared in block 205) in any of a variety of ways. For example, block 220 may include attaching the semiconductor die using mass reflow, thermocompression bonding (TCB), conductive epoxy, or the like.

1B provides an exemplary diagram of various aspects of block 220 , eg, die attach aspects. For example, a first die 125 (eg, cut from the logic wafer prepared in block 205 ) is electrically and mechanically attached to the redistribution structure 110 . Similarly, a second die 126 (e.g., cut from the logic wafer prepared in block 205 ) is electrically and mechanically attached to the redistribution structure 110 . For example, as described at block 205, a logic wafer (or a die thereof) may have various interconnect structures (e.g., conductive pads, lands, bumps, balls, wafer bumps, etc.) formed on its surface. conductive pillars, etc.). These structures are shown generally at 119 in FIG. 1B. Block 220 may, for example, connect such interconnect structures to redistribution structure 110 using any of a variety of attachment processes (e.g., mass reflow, thermocompression bonding (TCB), conductive epoxy, etc.) It may include the step of electrically and mechanically attaching to the.

The first die 125 and the second die 126 include any of a variety of die characteristics. As an example scenario, the first die 125 may include a processor die and the second die 126 may include a memory die. As another example scenario, the first die 125 may include a processor die, and the second die 126 may include a co-processor die. As another example scenario, the first die 125 may include a sensor die, and the second die 126 may include a sensor processing die. Although assembly 100B is shown with two dies 125 and 126 in FIG. 1B, any number of dies is possible. For example, it may be only one die, three dies, four dies, or four or more dies.

Additionally, although the first die 125 and the second die 126 are shown attached to the redistribution structure 110 laterally relative to each other, they may also be arranged in a vertical assembly. Various non-limiting examples of such structures are shown and discussed herein (e.g., die-on-die stacking, die attach to opposite substrate sides, etc.). Also, although first die 125 and second die 126 are shown with generally similar dimensions, such die 125 and 126 may have different respective characteristics (e.g., die height, footprint, connection pitch, etc.). may include

Although the first die 125 and the second die 126 are shown generally at a constant pitch, this need not be the case. For example, in the region of the first die footprint immediately adjacent to the second die 126 , most or all of the contacts 119 of the first die 125 and/or the second directly adjacent to the first die 125 . Most of the second dies 126 in the area of the die footprint may have a substantially thinner pitch than most or all other contacts 119 . For example, the first 5, 10, or n rows of the first die 125 closest to the second die (and/or the second die 126 closest to the first die 125) may have a 30 micron pitch. while other contacts 119 may generally have a pitch of 80 microns and/or 200 microns. The RD structure 110 may thus have corresponding contact structures and/or traces at a corresponding pitch.

Generally, block 220 includes attaching one or more semiconductor dies to a redistribution structure (e.g., a redistribution wafer). Accordingly, the scope of the present invention should not be limited by the features of any particular die, or by the features of any particular multi-die layout, or by the features of any particular manner of attaching such a die. .

Exemplary method 200 may include underfilling, at block 225 , the semiconductor die and/or other components attached to the RD structure at block 220 . Block 225 may include performing such underfilling in any of a variety of ways, as non-limiting examples described herein.

For example, after the die attach step at block 220 , block 225 may include underfilling the semiconductor die using a capillary underfill. For example, the underfill may include a tack-enhancing polymeric material capable of sufficiently flowing between the RD wafer and the pre-attached die by capillary action.

Also for example, block 225 can be used to attach a non-conductive paste (NCP) and/or a non-conductive film (NCF) or tape while a die is attached at block 220 (e.g., using a thermocompression bonding process). may include underfilling the semiconductor die using For example, such underfill material may be deposited (e.g., printed, sprayed, etc.) prior to attachment of the semiconductor die.

Like all blocks shown in example method 200 , block 225 can be performed anywhere in the method 200 flow as long as the space between the die and the redistribution structure is accessible.

Underfilling may also occur in other blocks of the example method 200 . For example, underfilling may be performed as part of the wafer molding block 230 (e.g., using a molded underfill).

1B provides an exemplary diagram of various aspects of block 225 , eg, underfilling aspects. The underfill 128 is positioned between the first semiconductor die 125 and the redistribution structure 110 and between the second semiconductor die 126 and the redistribution structure 110 , for example, surrounding the contacts 119 . do.

Although the underfill 128 is shown generally flat, the underfill may rise and form a fillet on the side of the semiconductor die and/or other components. As one example scenario, at least one-quarter or at least one-half of the die side surface may be covered with an underfill material. As another example scenario, one or more or all of the side surfaces may be covered with an underfill material. Also, for example, a significant portion of the space directly between semiconductor dies, between semiconductor dies and other components, and/or between other components may be filled with underfill material. For example, at least one-half or all of the space between laterally adjacent semiconductor dies, between the die and other components, and/or between other components may be filled with the underfill material. As one exemplary embodiment, the underfill 128 may cover the entire redistribution structure 110 of the RD wafer. As such an exemplary embodiment, if the RD wafer is later cut, such a cut may cut through the underfill 128 .

Generally, block 225 includes underfilling the semiconductor die and/or other components attached to the RD structure in block 220 . Accordingly, the scope of the present invention should not be limited to the features of any particular type of underfill or to any particular manner of carrying out such underfilling.

Exemplary method 200 includes, at block 230 , molding an RD wafer (e.g., or RD structure). Block 230 includes molding the RD wafer in any of a variety of ways, with non-limiting examples described herein.

For example, block 230 may follow the interconnect structures formed in block 215 (e.g., conductive balls, ellipsoid), along the top surface of the RD wafer, along the die and/or other components attached in block 220 . fields, columns or pillars (e.g., plated pillars, wires or foreign bonding wires, etc.), an underfill formed in block 225, and the like.

Block 230 may include, for example, using compression molding (e.g., using liquid, powder and/or film) or vacuum molding. Also, for example, block 230 may include using a transfer molding process (e.g., a wafer level transfer molding process).

The molding material may include, for example, any of a variety of features. For example, the molding material (e.g., epoxy molding compound (EMC), epoxy resin molding compound, etc.) may have a relatively high modulus, for example to provide wafer support in subsequent processing. . Also, for example, the molding material may include a relatively low modulus to provide wafer flexibility in subsequent processing.

As described herein, for example, with respect to block 225 , the molding process of block 230 may provide an underfill between the die and the RD wafer. As an example of this, there may be a uniformity of material between the mold material and the molded underfill material for molding the semiconductor die.

1C provides an exemplary diagram of various aspects of block 230, eg, a molding process. For example, the molded assembly 100C may be a top surface of the interconnect structures 121 , the first semiconductor die 125 , the second semiconductor die 126 , the underfill 128 , and the redistribution structure 110 . is shown with mold material 130 covering it. Although the mold material 130 , also referred to herein as an encapsulant, is shown completely covering the sides and tops of the first semiconductor die 125 and the second semiconductor die 126 , this need not be the case. For example, block 230 may include using a film assist or die seal molding technique to expose the top of the die from the mold material.

Molding material 130 generally directly contacts or covers areas of die 125 , 126 that are not covered, for example, with underfill 128 . As one exemplary scenario where at least a first area of the sides of the dies 125 and 126 is covered by the underfill 128 , the mold material 130 directly contacts or has a second area of the sides of the dies 125 and 126 . can be covered Mold material 130 fills the space between, for example, dies 125 and 126 (e.g., at least one region of the space not already filled with underfill 128 ).

In general, block 230 may include molding the RD wafer. Accordingly, the scope of the present invention should not be limited to the features of any particular molding material, structure, and/or technique.

Exemplary method 200 may include, at block 235 , grinding (or thinning) the mold material applied at block 230 . Block 235 may include grinding (or thinning) the mold material in any of a variety of ways, including non-limiting examples described herein.

Block 235 may include, for example, mechanically grinding the mold material to thin the mold material. Such thinning may, for example, leave over molded die and/or interconnect structures, or such thinning may expose one or more dies and/or one or more interconnect structures.

Block 235 may include, for example, grinding components other than the mold compound. For example, block 235 may include grinding the top sides (e.g., backsides or inactive sides) of the die attached at block 220 . Block 235 may also include, for example, grinding the interconnect structures formed in block 215 . Also, in scenarios where the underfill provided at block 225 or block 230 extends sufficiently upward, block 235 may also include grinding such underfill material. Such grinding may result, for example, in a flat plane on top of the ground material.

Block 235 may be skipped, for example, in a scenario where the height of the mold material was originally formed to a desired thickness.

1D provides an exemplary diagram of various aspects of block 235 , eg, mold grinding aspects. Assembly 100D is shown with mold material 130 (e.g., with respect to mold material 130 shown in FIG. 1C ) thinned to expose top surfaces of dies 125 and 126 . In this example, the dies 125 and 126 may also be ground (or thinned).

Although the top surface of the mold material is over the interconnect structure 121 as shown in FIG. 1D , and thus the interconnect structure 121 has not been ground, the interconnect structure 121 may also be ground. This exemplary embodiment has a flat top surface all in common at this stage including, for example, the top surface of the dies 125 and 126 , the top surface of the mold material 130 , and the top surface of the interconnect structures 121 . makes

As described herein, the mold material 130 may remain covering the dies 125 and 126 in an overmold shape. For example, the mold material 130 may not be ground, or the mold material 130 may not be ground to a height exposing the dies 125 and 126 .

In general, block 235 includes grinding (or thinning) the mold material applied in block 230 . Accordingly, the scope of the present invention should not be limited by the characteristics of any particular amount or type of grinding (or thinning).

Exemplary method 200 may include, at block 240 , removing the mold material applied at block 230 . Block 240 may include removing the mold material in any of a variety of ways, including non-limiting examples described herein.

As discussed herein, the mold material may cover the interconnect structures formed in block 215 . If the mold material covers the interconnect structures and the interconnect structures need to be exposed (e.g., for subsequent package attachment, top side redistribution layer formation, top side laminate substrate attachment, electrical connection, heat sink connection, electromagnetic shield connection, etc.) ), block 240 may include removing the mold material to reveal the connecting structures.

Block 240 may include exposing the interconnect structures through the mold material using, for example, a laser ablation technique. Also for example, block 240 may include steps using soft beam drilling, mechanical drilling, chemical drilling, or the like.

1D provides an exemplary diagram of various aspects of block 240 , eg, removal aspects. For example, assembly 100D is shown with removed vias 140 extending through mold material 130 to interconnect structures 121 . Although removed vias 140 are shown with vertical sidewalls, it should be understood that vias 140 may include any of a variety of shapes. For example, the sidewalls may be beveled (e.g., having a larger opening in the top face of the mold material 130 than in the interconnect structure 121 ).

Although block 240 is shown in FIG. 2 as being immediately after wafer molding at block 230 and mold grinding at block 235 , block 240 is performed after any point in method 200 . can be

Generally, block 240 may include removing the mold material from block 230 (e.g., to expose the interconnect structures formed at block 215 ). Accordingly, the scope of the present invention should not be limited by the features of any particular manner of performing such removal or by the features of any particular removed via structures.

Exemplary method 200 may include, at block 245 , attaching a molded RD wafer (e.g., top or mold side thereof) to a wafer support structure. Block 245 may include attaching the molded RD wafer to the wafer support structure in any of a variety of ways, including non-limiting examples described herein.

The wafer support structure may include, for example, a wafer or fixture formed of silicon, glass, or various other materials (e.g., dielectric materials). Block 245 may include attaching the molded RD wafer to the wafer support structure using, for example, an adhesive, a vacuum fixture, or the like. Note that, as shown and described herein, a redistribution structure is formed on the top side (or backside) of the die and mold material prior to attachment of the wafer support structure.

1E provides an exemplary diagram of various aspects of block 245 , for example, wafer support attachment aspects. A wafer support structure 150 is attached to the top side of the mold material 130 and the dies 125 and 126 . Wafer support structure 150 may be adhered, for example, with an adhesive, which may also be formed in contact surfaces with vias 140 and interconnect structures 121 . Note that in an assembly in which the tops of the dies 125 , 126 are covered with the molding material 130 , the wafer support structure 150 is directly connected only to the top of the mold material 130 .

In general, block 245 may include attaching a molded RD wafer (e.g., top or mold side thereof) to a wafer support structure. Accordingly, the scope of the present invention should not be limited by the features of any particular type of wafer support structure or by the features of any particular manner of attaching the wafer support structure.

Exemplary method 200 may include, at block 250 , removing the support layer from the RD wafer. Block 250 may include removing the support layer in any of a variety of ways, such as non-limiting examples described herein.

As discussed herein, the RD wafer may include a support layer on which the RD structure has been formed and/or transferred. The support layer may comprise, for example, a semiconductor material (e.g., silicon). As an exemplary scenario in which the support layer includes a layer of a silicon wafer, block 250 removes silicon (e.g., all silicon from the RD wafer, most of the silicon from the RD wafer, for example at least 90% or 95%, etc.) ) may include the step of removing For example, block 250 may include mechanically grinding a majority of the silicon, followed by a dry or wet chemical etch to remove the remaining portion (or a majority of the remaining portion). As an exemplary scenario in which a support layer is loosely attached to an RD structure formed (or displaced) thereon, block 250 includes separating or peeling to separate the support layer from the RD structure.

1F provides an exemplary diagram of various aspects of block 250 , for example, support layer removal aspects. For example, the support layer 105 (shown in FIG. 1E ) is removed from the RD structure 110 . As an example shown, RD structure 110 may still include a base dielectric layer 111 (e.g., oxide, nitride, etc.) as discussed herein.

In general, block 250 may include removing the support layer from the RD wafer. Accordingly, the scope of the present invention should not be limited to features of any particular type of wafer material or features of any particular manner of wafer material removal.

The exemplary method 200 may include, at block 255 , forming or patterning a first redistribution layer (RDL) dielectric layer to etch the oxide film of the RD structure. Block 255 includes forming and patterning the first RDL dielectric layer in any of a variety of ways, non-limiting examples described herein.

As examples generally discussed herein, the RD structure of an RD wafer is typically formed over an oxide (or nitride or other dielectric) film. To form a metal-to-metal attachment structure in the RD structure regions of the oxide film covering the traces (or pads or lands) of the RD structure, the oxide film may be removed, for example, by etching. have. Note that the oxide film need not be removed or completely removed as long as it has acceptable conductivity.

The first RDL dielectric layer may include, for example, polyimide or polybenzoxazole (PBO). The first RDL dielectric layer may include, for example, a laminate film or other materials. The first RDL dielectric layer may include, for example, an organic material. However, in various exemplary embodiments, the first RDL dielectric layer may include an inorganic material.

As an exemplary embodiment, the first RDL dielectric layer may comprise an organic material (e.g., polyimide, PBO, etc.) formed on the first side of the base dielectric layer of the RD structure, which may comprise an oxide or nitride film or other dielectric material. can

For example, the first RDL dielectric layer may be used as a mask to etch a base dielectric layer such as, for example, an oxide or nitride (e.g., at block 260). Also, for example, after etching, the first RDL dielectric layer may remain for use in, for example, forming a conductive RDL thereon.

As another exemplary scenario (not shown), a temporary mask layer (e.g., a temporary photoresist layer) may be used. For example, after etching, the temporary mask layer can be removed and replaced with a permanent RDL dielectric layer.

1G provides an exemplary diagram of various aspects of block 255 . For example, a first RDL dielectric layer 171 is formed and patterned over the base dielectric layer 111 . The patterned first RDL dielectric layer 171 may be formed by, for example, the base dielectric layer 111 may be etched (e.g., at block 260 ) and where the first traces (or regions thereof) will be formed. which may (e.g., at block 265 ) include vias 172 through the first RDL dielectric layer 171 .

Generally, block 255 includes forming and patterning a first dielectric layer (e.g., a first RDL dielectric layer), for example, over a base dielectric layer. Accordingly, the scope of the present invention should not be limited by the characteristics of a particular dielectric layer or by the features of a particular method of forming the dielectric layer.

Exemplary method 200 includes, at block 260, etching a base dielectric layer (e.g., oxide, nitride, etc.), such as unmasked regions thereof, from, for example, the RD structure. Block 260 may include performing etching in any of a variety of ways, with non-limiting examples described herein.

For example, block 260 is a dry etch process to etch through regions of the base dielectric layer (e.g., oxide, nitride, etc.) exposed by vias through the first dielectric layer, which function as a mask for etching. (or alternatively, a wet etching process).

1G provides an exemplary diagram of various aspects of block 260 , for example, an aspect of etching a dielectric layer. For example, regions of the base dielectric layer 111 shown below the first conductive traces 112 in FIG. 1F are removed from FIG. 1G. This enables, for example, a metal-to-metal contact between the first conductive traces 112 and the first RDL traces at block 265 .

In general, it includes etching block 260, eg, a base dielectric layer. Accordingly, the scope of the present invention should not be limited by any particular manner of performing such etching.

The example method 200 may include, at block 265 , forming first redistribution layer (RDL) traces. Block 265 may include forming the first RDL traces in any of a variety of ways, such as non-limiting examples described herein.

As discussed herein, a first RDL dielectric layer (e.g., formed at block 255) may be used for etching (e.g., at block 260) and then left for formation of first RDL traces. . Alternatively, the first RDL dielectric layer may be formed and patterned after an etching process. As another alternative embodiment discussed herein, the etch process for the base dielectric layer may be skipped (e.g., sufficient for the base dielectric layer (e.g., thin oxide or nitride) to serve adequately as a conductive path between the metal traces. in an embodiment with conductivity).

Block 265 includes forming first RDL traces attached to the first conductive traces of the RD structure exposed through the patterned first RDL dielectric layer. The first RDL traces may also be formed over the first RDL dielectric layer. Block 265 may include forming the first RDL traces in any of a variety of ways, for example, by plating, although the scope of the invention is contemplated by the features of any particular manner of forming such traces. should not be limited.

The first RDL traces may include any of a variety of materials (e.g., kappa, gold, nickel, etc.). The first RDL traces may include, for example, any of a variety of dimensional characteristics. For example, a typical pitch for RDL traces may be, for example, 5 microns. As an exemplary embodiment, the first RDL traces are, for example, center-to-center on an order of magnitude greater than or equal to the pitch at which the various traces of the RD structure of the RD wafer are formed (e.g., sub-micron pitch, approximately 0.5 micron pitch, etc.). It may be formed with a central pitch.

1G and 1H provide exemplary diagrams of various aspects of block 265 , eg, aspects of RDL trace formation. For example, the first region 181 of the first RDL traces may be formed in the vias 172 of the first RDL dielectric layer 171 and the second region of the RD structure 110 exposed by the vias 172 . 1 makes contact with conductive traces 112 . Also, for example, the second region 182 of the first RDL traces may be formed on the first RDL dielectric layer 171 .

In general, block 265 may include forming first redistribution layer (RDL) traces. Accordingly, the scope of the present invention should not be limited to features of any particular RDL traces or features of any particular manner of forming such RDL traces.

The exemplary method 200, at block 270, forms a second RDL dielectric layer over the first RDL traces (e.g., formed at block 265) and the first RDL dielectric layer (e.g., formed at block 255), It may include patterning. Block 270 may include forming and patterning the second dielectric layer in any of a variety of ways, including non-limiting examples described herein.

For example, block 270 may share any or all features of block 255 . The second RDL dielectric layer may be formed using, for example, the same material as the first RDL dielectric layer formed at block 255 .

The second RDL dielectric layer may comprise, for example, a polyimide or polybenzoxazole (PBO) material. The second RDL dielectric layer may, for example, generally comprise an organic material. As various exemplary embodiments, however, the first RDL dielectric layer may include an inorganic material.

1H provides an exemplary diagram of various aspects of block 270 . For example, a second RDL dielectric layer 183 is formed over the first RDL traces 181 , 182 and over the first RDL dielectric layer 171 . As shown in FIG. 1H , vias 184 may be made with the first RDL traces 182 exposed by such vias 184 through which a conductive contact may be made with the second RDL dielectric layer 183 . is formed in

Generally, block 270 includes forming and/or patterning a second RDL dielectric layer. Accordingly, the scope of the present invention should not be limited by the characteristics of any dielectric layer or by the characteristics of any particular manner of forming the dielectric layer.

The example method 200 includes, at block 275 , forming second redistribution layer (RDL) traces. Block 275 includes forming the second RDL traces in any of a variety of ways, such as non-limiting examples described herein. Block 275 may share any or all features of block 265 , for example.

Block 275 forms second RDL traces attached to exposed first RDL traces (e.g., formed at block 265) through vias in the patterned second RDL dielectric layer (e.g., formed at block 270). includes Second RDL traces may also be formed over the second RDL dielectric layer. Block 275 may include forming the second RDL traces in any of a variety of ways, for example by plating, although the scope of the invention should not be limited to features in any particular manner. .

Along with the first RDL traces, the second RDL traces may comprise any of a variety of materials (e.g., kappa, etc.). Further, the second RDL traces may include, for example, any of a variety of dimensional characteristics.

1H and 1I provide illustrative views of various aspects of block 275 . For example, second RDL traces 191 may be formed in those vias 184 in the second RDL dielectric layer 183 to contact the first RDL traces 181 exposed through the vias 184 . have. In addition, the second RDL traces 191 may be formed on the second RDL dielectric layer 183 .

In general, block 275 may include forming second redistribution layer (RDL) traces. Accordingly, the scope of the present invention should not be limited by the features of any particular RDL traces or by the features of the particular manner of forming such RDL traces.

The exemplary method 200, at block 280, forms a third RDL dielectric layer over the second RDL traces (e.g., formed at block 275) and a second RDL dielectric layer (e.g., formed at block 270) and It may include patterning. Block 280 may include forming and patterning a third dielectric layer in any manner, including non-limiting examples described herein.

For example, block 280 may share any or all features of blocks 270 and 255 . The third RDL dielectric layer is formed, for example, using the same material as the first RDL dielectric layer formed at block 255 (and/or after removal of the etch and temporary mask layer at block 260), and/or block 270; It may be formed using the same material as the second RDL dielectric layer formed in .

The third RDL dielectric layer may include, for example, polyimide or polybenzoxazole (PBO). The third RDL dielectric layer may, for example, generally comprise an organic material. As various exemplary embodiments, however, the third RDL dielectric layer may include an inorganic material.

1I provides an exemplary diagram of various aspects of block 280 . For example, the third RDL dielectric layer 185 may be formed over the second RDL traces 191 and over the second RDL dielectric layer 183 . As shown in FIG. 1I , vias may be formed in the third RDL dielectric layer 185 by making conductive contacts with the second RDL traces 191 exposed by those vias.

In general, block 280 may include forming and/or patterning a third RDL dielectric layer. Accordingly, the scope of the present invention should not be limited by the characteristics of any particular dielectric layer or by the features of any particular manner in which the dielectric layer is made.

The example method 200 may include, at block 285 , forming interconnect structures over the second RDL traces and/or over the third RDL dielectric layer. Block 285 may include forming interconnect structures in any of a variety of ways, including non-limiting examples described herein.

Block 285 may include, for example, forming an underbump metal on regions of the second RDL traces exposed through vias in the third dielectric layer. Block 285 may then include, for example, attaching conductive bumps or balls to the underbump metal. Other interconnect structures may of course be used, examples of which are described herein (e.g., conductive posts or pillars, solder balls, solder bumps, etc.).

1I provides an exemplary diagram of various aspects of block 285 , for example, aspects of forming an interconnect structure. For example, interconnect structures 192 are attached to second RDL traces 191 through vias formed in third RDL dielectric layer 185 . Note that although interconnect structures 192 are shown smaller than interconnect structures 121, the present invention is not so limited. For example, interconnect structures 192 may be the same size as interconnect structures 121 or may be larger than interconnect structures 121 . Also, the interconnect structures 192 may be of the same type as the interconnect structures 121 or different types.

The redistribution layer(s) formed in blocks 225-285, which may also be referred to as a front side redistribution layer (RDL), is generally a fan-out assembly (e.g., die 125,126). 1 ), this is, for example, a fan-in where interconnect structure 192 does not generally extend outside of the footprint of dies 125 , 126 . ) may be formed as an assembly. Non-limiting examples of such assemblies are described herein.

In general, block 285 may include forming interconnect structures over the second RDL traces and/or over the third RDL dielectric layer, for example. Accordingly, the scope of the present invention should not be limited by the characteristics of any particular interconnect structures or by any particular manner of forming the interconnect structures.

Exemplary method 200 may include, at block 290 , debonding (or detaching) the wafer support structure attached at block 245 . Block 290 may include performing such debonding in any of a variety of ways, in non-limiting aspects described herein.

For example, as an example scenario where a wafer support structure is attached with an adhesive, the adhesive can be released (e.g., using heat and/or force). Also, for example, a chemical separating agent may be used. As another example scenario where the wafer support structure is attached using vacuum force, the vacuum force may be released. Note that as a scenario involving adhesives or other members for a wafer support attachment structure, block 285 may include cleaning residues from the electrical assembly and/or from the wafer support structure after debonding.

1I and 1J provide illustrative views of various aspects of block 290 . For example, the wafer support structure 150 shown in FIG. 1I is removed from FIG. 1J .

In general, block 290 includes debonding the wafer support structure. Accordingly, the scope of the present invention should not be limited by any particular type of features of the wafer support structure or by any particular manner of debonding the wafer support structure.

Exemplary method 200 includes, at block 295 , cutting the wafer. Block 295 includes cutting the wafer in any of a variety of ways, including non-limiting examples described herein.

The discussion here has generally focused on the processing of a single die of an RD wafer. Such a focus on a single die of an RD wafer is for the sake of clarity only. It should be understood that all process steps discussed herein may be performed on an entire wafer. For example, each and other views of the figures presented herein in FIGS. 1A-1J may be replicated tens or hundreds of times on a single wafer. For example, there may be no separation between one of the illustrated assemblies and an adjacent assembly of the wafer until separation.

Block 295 may include, for example, cutting (e.g., mechanical punch-cutting, mechanical saw-cutting, laser cutting, soft beam cutting, plasma cutting, etc.) from the wafer into individual packages. The result of such cutting may be, for example, the package shown in FIG. 1J . For example, the cut may include side surfaces of a package that include coplanar side surfaces of multiple parts of the package. For example, any or all of the side surfaces of mold material 130 , RD structure 110 dielectric layers, various RDL dielectric layers, underfill 128 , etc. may be coplanar.

In general, block 295 may include cutting the wafer. Accordingly, the scope of the present invention should not be limited by the features of any particular manner of cutting the wafer.

1 and 2 illustrate various exemplary method aspects and variations thereof. Other exemplary method aspects will be described with reference to additional drawings.

As discussed herein in the discussion of FIGS. 1 and 2 , block 235 may include grinding (or otherwise thinning) the mold material 130 to expose one or more dies 125 , 126 .

As also discussed, at block 235 mold grinding (or thinning) need not be performed or may be performed to the extent that the tops of dies 125 , 126 covered with mold material 130 still remain. An example is provided in FIG. 3 . As shown in FIG. 3A , mold material 130 covers the top of semiconductor die 125 , 126 . Note that interconnect structures 121 may be shorter or larger than dies 125 and 126 . Continuing the comparison, the resulting package 300B may appear as shown in FIG. 3B , rather than the resulting package 100J having an appearance as shown in FIG. 1J .

Also, as discussed herein in the discussion of FIGS. 1 and 2 , block 215 for forming the TMV interconnect structures, and block 240 for removing the TMV mold may be skipped. An example is provided in FIG. 4 . As shown in FIG. 4A , as opposed to block 215 and FIG. 1B , there are no TMV interconnect structures 121 formed. As shown in FIG. 4B , in contrast to block 230 and FIG. 1C , the mold material 130 does not cover the interconnect structures.

Continuing the comparison, as described herein, mold grinding (or thinning) may be performed at block 235 to the extent exposing tops of one or more semiconductor dies 125 , 126 from mold material 130 . 4C provides an exemplary diagram of such a process. In general, assembly 400C of FIG. 4C is similar to assembly 100J of FIG. 1J , except for interconnect structures 121 and removed vias exposing the interconnect structures through mold material 130 .

Also, for example, as described herein, mold grinding (or thinning) at block 235 may be skipped or performed to the extent leaving the tops of dies 125 , 126 covered with mold material 130 . 4D provides an exemplary diagram of such a process. In general, assembly 400D of FIG. 4D excludes interconnect structures 121 and removed vias exposing the interconnect structures through mold material 130 , with mold material 130 covering dies 125 and 126 . Similar to assembly 100J of FIG. 1J.

As another example, as described herein in the discussion of block 215 , the TMV interconnect structures may include any of a variety of structures, for example conductive pillars (e.g., plated posts or pillars, vertical wires, etc.). can 5A provides an exemplary view of conductive pillars 521 attached to RD structure 110 . The conductive pillars 521 may be plated over the RD structure 110 , for example. Conductive pillars 521 also include, for example, wires attached to RD structure 110 (e.g., wire-bond attachment, soldering, etc.) and extending in a vertical direction (e.g., wire-bond wires). can do. The conductive pillars 521 may be RD from the RD structure 110 to a height equal to the height of the one or more dies 125 , 126 , or less than the height of the dies 125 , 126 , for example, from the RD structure 110 . It may extend from structure 110 . As an exemplary embodiment, the pillars may have a height of 200 microns or more with a center-to-center pitch of 100-150 microns. Note that any number of columns of pillars 521 may be formed. In general, assembly 500A of FIG. 5A is similar to assembly 100B of FIG. 1B with conductive pillars 521 as interconnecting structures instead of conductive balls 121 .

Continuing for example, FIG. 5B shows RD structure 110 covered with mold material 130 , conductive pillars 521 , semiconductor dies 125 , 126 , and underfill 128 . Molding may be performed, for example, according to block 230 of example method 200 . In general, assembly 500B of FIG. 5B is similar to assembly 100C of FIG. 1C with conductive pillars 521 as interconnecting structures instead of conductive balls 121 .

Continuing the example, FIG. 5C shows the mold material 130 thinned (e.g., ground) to a desired thickness. Thinning may be performed, for example, according to block 235 of example method 200 . Note that, for example, the conductive pillars 521 and/or the semiconductor die 125 and 126 may also be thinned. Assembly 500D of FIG. 5D generally has conductive pillars 521 as interconnecting structures instead of conductive balls 121 , and also has no vias 140 removed in FIG. 1D assembly 100D of FIG. 1D . ) is similar to For example, thinning of the mold material 130 may expose the top ends of the conductive pillars 521 . However, if the thinning of the mold material 130 does not expose the top portions of the conductive pillars 521 , a mold removal operation (e.g., according to block 240 ) may be performed. Although the tops of the semiconductor dies 125 and 126 are shown exposed as an assembly, the tops need not be exposed. For example, the pillars 521 may be erected larger than the semiconductor dies 125 and 126 . This exemplary configuration allows, for example, mold material 130 to cover the backside surfaces of semiconductor die 125 , 126 while pillars 521 are exposed and/or protrude from mold material 130 . , which may, for example, protect semiconductor dies 125 and 126, prevent or reduce warpage, and the like.

In an exemplary embodiment in which the pillars 521 are formed with a smaller height than the dies 125 and 126 , the thinning first grinds the mold material 130 and then the mold material 130 until the pillars 521 are exposed. ) and the back (or inactive) sides of the dies 125 and 126 . Here, thinning may stop or continue grinding of mold material 130 , die 125 , 126 , and pillars 521 , for example.

Continuing the example, assembly 500C shown in FIG. 5C may be further processed to form a redistribution layer (RDL) 532 over mold material 130 and dies 125 and 126 . 5D shows an example of such a process. The redistribution layer 532 may also be referred to herein as a backside redistribution (RDL) layer 532 . Although such backside RDL formation is not explicitly shown in one of the blocks of the exemplary method 200, such operations may occur, for example, after block 235, which is a mold grinding operation, and after a wafer support structure attachment (e.g., block). at 235 , at block 240 , at block 245 , or in between any such blocks) before block 245 .

As shown in FIG. 5D , a first backside dielectric layer 533 may be formed and patterned over the mold material 130 and the dies 125 , 126 . The first backside dielectric layer 533 may be formed and patterned, for example, in the same or similar manner as the first RDL dielectric layer 171 formed in block 260, albeit on a different surface. For example, the first backside dielectric layer 533 may be formed over the mold material 130 and directly over the exposed backside surfaces of the semiconductor dies 125 and 126 (e.g., dies 125 and 126) in a mold covering the backside surfaces of the dies 125 and 126 . may be formed over the material 130 , and vias 534 may be formed (e.g., by etching, removing, etc.) in the first backside dielectric layer 533 to expose at least the top of the conductive pillars 521 . . In an exemplary configuration in which mold material 130 covers the backside surfaces of semiconductor dies 125, 126, a first backside dielectric layer 533 may still be formed, but need not be (e.g., backside traces discussed below) Note that 535 may be formed directly on top of mold material 130 rather than on top of first backside dielectric layer 533 ).

Backside traces 535 may be formed on the first backside dielectric layer 533 and inside the vias 534 of the first backside dielectric layer 533 . The backside traces 535 may thus be electrically connected to the conductive pillars 521 . Backside traces 535 may be formed, for example, in the same or similar manner as the first RDL traces formed in block 265 . At least some, but not all of the backside traces 535 may extend, for example, from the conductive pillars 521 to a location directly over the semiconductor die 125 , 126 . At least some of the backside traces 535 may also extend, for example, from the conductive pillars 521 to a region other than directly over the semiconductor die 125 , 126 .

A second backside dielectric layer 536 may be formed and patterned over the first backside dielectric layer 533 and the backside traces 535 . Second backside dielectric layer 536 may be formed and patterned, for example, in the same or similar manner as second RDL dielectric layer 183 formed in block 270, albeit on a different surface. For example, a second backside dielectric layer 536 may be formed over the first backside dielectric layer 533 and over the backside traces 535 and vias 537 connect the contact regions of the backside traces 535 . It may be formed (e.g., by etching, removing, etc.) in the second backside dielectric layer 536 to expose it.

Backside interconnect pads 538 (e.g., ball contact pads) may be formed over the second backside dielectric layer 536 and/or inside the vias 537 of the second backside dielectric layer 536 . Backside interconnect pads 538 are thus electrically connected to backside traces 535 . The backside interconnect pads 538 may be formed, for example, in the same or similar manner as the second RDL traces formed in block 275 . Backside interconnect pads 538 may be formed, for example, by formation of metal contact pads and/or under bump metal (e.g., to improve adhesion following backside traces 535 by interconnect structures). can be formed by the formation of

Although the backside RDL layer 532 is shown as two backside dielectric layers 533,536 and one layer of backside traces 535, it should be understood that any number of dielectric and/or trace layers may be formed.

5E, after the backside RDL layer 532 is formed, the wafer support structure 150 uses vacuum force, directly, with an intervening adhesive layer, the backside RDL layer 532 (e.g.) etc.) can be attached. Wafer support structure 150 may be attached, for example, in the same or similar manner as wafer support structure 150 attached at block 245 . For example, FIG. 5E shows a diagram of a wafer support structure 150 in a manner similar to that of FIG. show attachment.

5F , the support layer 105 (shown in FIG. 5E ) may be removed from the RD wafer, and a frontside redistribution layer is placed on the side of the RD structure 110 opposite the dies 125 and 126 . may be formed, interconnect structure 192 may be formed, and wafer support structure 150 may be removed.

For example, the support layer 105 may be removed in a manner similar to or similar to that discussed herein with respect to block 250 and FIGS. 1E-1F . Also for example, the frontside redistribution layer may be formed in a manner similar to or similar to that discussed herein with respect to blocks 255 - 280 and FIGS. 1G-1H . Also, for example, interconnect structures 192 may be formed in the same or similar manner as discussed herein with respect to block 285 and FIG. 1I . Also, for example, the wafer support structure 150 may be removed in a manner similar to or similar to that discussed herein with respect to block 290 and FIG. 1J .

As another exemplary embodiment, a substrate (e.g., laminate substrate, package substrate, etc.) may be attached over the semiconductor die 125 , 126 , for example, instead of or in addition to the backside RDL discussed herein with respect to FIG. 5 . have. For example, as shown in FIG. 6A , interconnect structures 621 may be formed at a height that will extend to about the height of dies 125 and 126 . For example, in the example scenario where the backside substrate has its own interconnect structures or additional interconnect structures are used between interconnect structures 621 and the backside substrate, this height need not necessarily exist. Note that there is no Interconnect structures 621 may be attached, for example, in a manner similar to or as discussed herein with respect to block 215 and FIG. 1B .

Continuing the example, as shown in FIG. 6B , assembly 600B can be molded and the mold can be thinned if necessary. Such molding and/or thinning may be performed, for example, in a manner similar to or similar to that discussed herein with respect to blocks 230 and 235, and FIGS. 1C and 1D.

As shown in FIG. 6C , a wafer support structure 150 may be attached, the support layer 105 may be removed, and a frontside RDL may be formed. For example, wafer support structure 150 may be attached in a manner similar to or similar to that discussed herein with respect to block 245 and FIG. 1E . Also, for example, the support layer 105 may be removed in a manner similar to or similar to that discussed herein with respect to block 250 and FIG. 1F . Also, for example, the frontside RDL may be formed in a manner similar to or similar to that discussed herein with respect to blocks 225-280 and FIGS. 1G-1H.

As shown in FIG. 6D , interconnect structure 192 may be attached, wafer support structure 150 may be removed, and backside substrate 632 may be attached. For example, interconnect structures 192 may be attached in a manner similar to or similar to that discussed herein with respect to block 285 and FIG. 1I . Also, for example, the wafer support structure 150 may be removed in a manner similar to or similar to that discussed herein with respect to block 290 and FIG. 1J . Also for example, backside substrate 632 may be electrically attached to interconnect structures 621 and/or mechanically attached to mold material 130 and/or die 125 , 126 . Backside substrate 632 may be attached, for example, in wafer (or panel) form and/or in standalone package form, and may be attached, for example, prior to a cutting process (e.g., as discussed in block 295). Or it can be attached later.

The exemplary methods and assemblies shown in Figures 1-7 and discussed herein have been described by way of non-limiting examples merely to illustrate various aspects of the present invention. Such methods and assemblies may also share any or all features with the methods and assemblies shown and discussed in the following commonly pending US patent applications: filed Jan. 29, 2013; US Patent Application Serial No. 13/753,120, entitled "Semiconductor Device and Method of Manufacturing Semiconductor Device;" U.S. Patent Application No. 13/863,457, filed April 16, 2013, and entitled "Semiconductor Device and Method of Manufacturing Same;" US Patent Application Serial No. 14/083,779, filed on Nov. 19, 2013, and entitled "Semiconductor Device with Deep Wells Without Through Silicon Vias;" U.S. Patent Application No. 14/218,265, filed March 18, 2014, and entitled "Semiconductor Device and Method of Making the Same"; U.S. Patent Application No. 14/313,724, filed June 24, 2014, and entitled "Semiconductor Device and Method of Manufacturing Same;" US Patent Application No. 14/444,450, filed July 28, 2014, and entitled "Semiconductor Device With Thin Redistribution Layers;" US Patent Application Serial No. 14/524,443, filed October 27, 2014, and entitled "Semiconductor Device with Reduced Thickness;" US Patent Application No. 14/532,532, filed on November 4, 2014, and entitled "Interposer, Method of Manufacturing Same, Semiconductor Package Using Same, and Method of Manufacturing Semiconductor Package;" U.S. Patent Application Serial No. 14/546,484, filed November 18, 2014, and entitled "Semiconductor Device with Reduced Warpage;" and U.S. Patent Application Serial No. 14/671,095, filed March 27, 2015, entitled “Semiconductor Device and Method of Manufacturing Same;” The entire contents of each of which are herein incorporated by reference.

Any or all of the semiconductor packages discussed herein may, but need not, be attached to the package substrate. Various non-limiting examples of such semiconductor device packages and their methods will now be discussed.

7A-7L are cross-sectional views illustrating an exemplary semiconductor package and an exemplary method of manufacturing the semiconductor package, in accordance with various aspects of the present disclosure. The structures shown in FIGS. 7A-7L are, for example, FIGS. 1A-1J, 3A-3B, 4A-4D, 5A-5F, 6A-6D, 9, 10a-10b, 11a-11d, 12a-12b, 13 , , and 14 may share any or all features of similar structures. 8 is a flow diagram of an exemplary method 800 of manufacturing a semiconductor package in accordance with various aspects of the present invention. Exemplary method 800 may share any or all features of, for example, exemplary method 200 shown in FIG. 2 and discussed herein and any methods discussed herein. 7A-7L may illustrate an example semiconductor package at various stages (or blocks) of the production method 800 of FIG. 8 , for example. 7A-7L and 8 will now be discussed together.

Exemplary method 800 may include, at block 805 , preparing a logic wafer for processing (e.g., for packaging). Block 805 may include preparing the logic wafer for processing in any of a variety of ways, such as non-limiting examples described herein. Block 805 may share any or all features of block 205 of example method 200 shown in FIG. 2 and discussed herein, for example.

Exemplary method 800 may include, at block 810 , preparing a redistribution structure wafer (RD wafer). Block 810 includes preparing the RD wafer for processing in various manners, including non-limiting examples provided herein. Block 810 may share any or all features of block 210 of example method 200 shown in FIG. 2 and discussed herein, for example.

7A provides an exemplary diagram of various aspects of block 810 . Referring to FIG. 7A , the RD wafer 700A may include, for example, a support layer 705 (e.g., a silicon layer). A redistribution (RD) structure 710 may be formed on the support layer 105 . RD structure 710 includes, for example, base dielectric layer 711 , first dielectric layer 713 , first conductive traces 712 , second dielectric layer 716 , second conductive traces 715 , and interconnect structures 717 .

The base dielectric layer 711 may be over the support layer 705 , for example. The base dielectric layer 711 may include, for example, an oxide film, a nitride film, or the like. Base dielectric layer 711 may be formed to a standard specification and/or may be natural, for example.

The RD wafer 700A may also include first conductive traces 712 and a first dielectric layer 713 . The first conductive traces 712 may include, for example, a deposited conductive metal (eg, kappa). The first dielectric layer 713 may include, for example, an inorganic dielectric material (e.g., a silicon oxide film, a silicon nitride film, etc.). As another assembly, the first dielectric layer 713 may include an organic dielectric material.

RD wafer 700A may also include, for example, second conductive traces 715 and a second dielectric layer 716 . The second conductive traces 715 may include, for example, a deposited conductive metal (eg, kappa). Second conductive traces 715 may be connected to respective first conductive traces 712 through, for example, respective conductive vias 714 (e.g., in first dielectric layer 713 ). . The second dielectric layer 716 may include, for example, an inorganic material (e.g., a silicon oxide film, a silicon nitride film, etc.). As another assembly, the second dielectric layer 716 may include an organic dielectric material.

Although two sets of dielectric layers and conductive traces are shown in FIG. 7A , it should be understood that the RD structure 710 of the RD wafer 700A may include any number of such layers and traces. For example, the RD structure 710 may include only one dielectric layer and/or a set of conductive traces, three sets of dielectric layers and/or conductive traces, and/or the like.

In conjunction with the logic wafer preparation step in block 205 , block 210 includes interconnect structures (e.g., conductive bumps, conductive balls, conductive pillars, conductive lands or pads) on the surface of RD structure 710 . etc.) may be included. An example of such interconnect structures 717 , where RD structure 710 includes interconnect structures 717 , is shown in FIG. 7A , which is formed on the front (or top) side of RD structure 710 . and electrically connected to respective second conductive traces 715 through conductive vias in the second dielectric layer 716 . These interconnect structures 717 may be used, for example, to connect the RD structure 710 to various electronic components (eg, active semiconductor components or die, passive components, etc.).

Interconnect structures 717 may include, for example, any of a variety of conductive materials (e.g., one or a combination of kappa, nickel, gold, etc.). Interconnect structures 717 may also include, for example, solder.

In general, block 810 includes preparing a redistribution structure wafer (RD wafer). Accordingly, the scope of the present invention should not be limited to the features of any particular manner of carrying out such preparations.

Exemplary method 800 may include, at block 820 , attaching one or more semiconductor dies to an RD structure (e.g., of an RD wafer). Block 820 may include attaching the die to the RD structure in any of a variety of ways, including non-limiting examples provided herein. Block 820 may share any or all features of example method 200 shown in FIG. 2 and discussed herein, for example.

7B provides an illustrative view of various aspects of block 820 , eg, a die attach structure. For example, a first die 725 (e.g., which may have been cut from the prepared logic wafer at block 805 ) may be electrically and mechanically attached to the redistribution structure 710 . Similarly, a second die 726 (e.g., may have been cut from the prepared logic wafer at block 805 ) may be electrically and mechanically attached to the redistribution structure 710 .

The first die 725 and the second die 726 may include any of a variety of die features. As an example scenario, the first die 725 may include a processor die and the second die 726 may include a memory die. As another example scenario, the first die 725 may include a processor die, and the second die 726 may include a co-processor die. As another example scenario, the first die 725 may include a sensor die, and the second die 726 may include a sensor processing die. Although assembly 700B is shown with two dies 725 and 726 in FIG. 7B , any number of dies may be used. For example, it may be only one die, three dies, four dies, or four or more dies.

Additionally, although the first die 725 and the second die 726 are shown attached to the redistribution structure 710 laterally relative to each other, they may also be arranged in a vertical assembly. Various non-limiting examples of such structures are shown and discussed herein (e.g., die-on-die stacking, die attach to opposite substrate side, etc.). Also, although first die 725 and second die 726 are shown with generally similar dimensions, such dies 725 and 726 have different respective characteristics (e.g., die height, footprint, connection pitch, etc.). may include

Although the first die 725 and the second die 726 are shown generally at a constant pitch, this need not be the case. For example, most or all of the contacts of the first die 725 in the region of the first die footprint immediately adjacent the second die 726 and/or the second die footprint immediately adjacent the first die 125 . Most of the second dies 126 in the region of may have a substantially thinner pitch than most or all other contacts. For example, the first 5, 10, or n rows of the first die 725 closest to the second die (and/or the second die 726 closest to the first die 725) may have a 30 micron pitch. while other contacts may generally have a pitch of 80 microns and/or 200 microns. The RD structure 710 may thus have corresponding contact structures and/or traces at a corresponding pitch.

Generally, block 820 includes attaching one or more semiconductor dies to a redistribution structure (e.g., a redistribution wafer). Accordingly, the scope of the present invention should not be limited by the features of any particular die, or by the features of any particular multi-die layout, or by the features of any particular manner of attaching such a die. .

The example method 800 may include underfilling the semiconductor die and/or other components attached to the RD structure at block 820 at block 825 . Block 825 may include performing such underfilling in any of a variety of ways, as non-limiting examples described herein. Block 825 may share any or all features of block 225 of example method 200 shown in FIG. 2 and discussed herein, for example.

7B provides an exemplary diagram of various aspects of block 825 , eg, underfilling aspects. The underfill 728 is positioned between the first semiconductor die 725 and the redistribution structure 710 and between the second semiconductor die 726 and the redistribution structure 710 .

Although the underfill 728 is shown generally flat, the underfill may rise and form a fillet on the side of the semiconductor die and/or other components. As one example scenario, at least one-quarter or at least one-half of the die side surface may be covered with an underfill material. As another example scenario, one or more or all of the side surfaces may be covered with an underfill material. Also, for example, a significant portion of the direct space between semiconductor dies, between semiconductor dies and other components, and/or between other components may be filled with underfill material. For example, at least one-half or all of the space between laterally adjacent semiconductor dies, between the die and other components, and/or between other components may be filled with the underfill material. As one exemplary embodiment, the underfill 728 may cover the entire redistribution structure 710 of the RD wafer. As such an exemplary embodiment, if the RD wafer is later cut, such a cut may cut through the underfill 728 .

Generally, block 825 includes underfilling the semiconductor die and/or other components attached to the RD structure in block 820 . Accordingly, the scope of the present invention should not be limited to the features of any particular type of underfill or to any particular manner of carrying out such underfilling.

Exemplary method 800 includes, at block 830 , molding an RD wafer (e.g., or RD structure). Block 830 includes molding the RD wafer in any of a variety of ways, with non-limiting examples described herein. Block 830 may share any or all features of block 230 of example method 200 shown in FIG. 2 and discussed herein, for example.

7C provides an illustrative view of various aspects of block 830, eg, a molding process. For example, the molded assembly 700C may include a mold material 730 covering the top surface of the first semiconductor die 725 , the second semiconductor die 726 , the underfill 728 , and the redistribution structure 710 ; are shown together. Although the mold material 730, also referred to herein as an encapsulant, is shown completely covering the sides and tops of the first semiconductor die 725 and the second semiconductor die 726, this need not be the case. For example, block 830 may include using a film assist or die seal molding technique to expose the top of the die from the mold material.

Molding material 730 generally directly contacts or covers areas of die 725 , 726 that are not covered, for example, with underfill 728 . As one exemplary scenario in which at least a first area of the sides of the dies 725 and 726 is covered by an underfill 728 , the mold material 730 directly contacts or has a second area of the sides of the dies 725 and 726 . can be covered Mold material 730 fills the space between, for example, dies 725 and 726 (e.g., at least one region of the space not already filled with underfill 728 ).

In general, block 830 may include molding the RD wafer. Accordingly, the scope of the present invention should not be limited to the features of any particular molding material, structure, and/or technique.

Exemplary method 800 may include, at block 835 , grinding (or thinning) the mold material applied at block 830 . Block 835 may include grinding (or thinning) the mold material in any of a variety of ways, including non-limiting examples described herein. Block 835 may share any or all features of block 235 of example method 200 shown in FIG. 2 and discussed herein, for example.

7D provides an exemplary diagram of various aspects of block 835 , eg, mold grinding aspects. Assembly 700D is shown with mold material 730 (e.g., with respect to mold material 730 shown in FIG. 7C) thinned to expose top surfaces of dies 725 and 726. In this example, the dies 725 and 726 may also be ground (or thinned).

As described herein, the mold material 730 may remain covering the dies 725 and 726 with an over mold assembly. For example, the mold material 730 may not be ground, or the mold material 730 may not be ground to a height exposing the dies 725 and 726 .

In general, block 835 includes grinding (or thinning) the mold material applied in block 830 . Accordingly, the scope of the present invention should not be limited by the characteristics of any particular amount or type of grinding (or thinning).

Exemplary method 800 may include, at block 845 , attaching a molded RD wafer (e.g., top or mold side thereof) to a wafer support structure. Block 845 may include attaching the molded RD wafer to the wafer support structure in any of a variety of ways, including non-limiting examples provided herein. Block 845 may share any or all features of block 245 of example method 200 shown in FIG. 2 and discussed herein, for example.

7E provides an exemplary view of various aspects of block 845 , for example, wafer support attachment aspects. A wafer support structure 750 is attached to the top side of the mold material 730 and the dies 725 and 726 . The wafer support structure 750 may be adhered, for example, with an adhesive. Note that in an assembly in which the tops of the dies 725 and 726 are covered with the molding material 730 , the wafer support structure 750 is directly connected only to the top of the mold material 730 .

In general, block 845 may include attaching a molded RD wafer (e.g., top or mold side thereof) to a wafer support structure. Accordingly, the scope of the present invention should not be limited by the features of any particular type of wafer support structure or by the features of any particular manner of attaching the wafer support structure.

Exemplary method 800 may include, at block 850 , removing the support layer from the RD wafer. Block 850 may include removing the support layer in any of a variety of ways, such as non-limiting examples described herein. Block 850 may share any or all features of block 250 of example method 200 shown in FIG. 2 and discussed herein, for example.

As discussed herein, the RD wafer may include a support layer on which the RD structure has been formed and/or transferred. The support layer may comprise, for example, a semiconductor material (e.g., silicon). As an exemplary scenario in which the support layer includes a layer of a silicon wafer, block 850 may remove most of the silicon (e.g., all silicon from the RD wafer, e.g., at least 90% or 95% of the silicon from the RD wafer, etc.). ) may include the step of removing For example, block 850 includes mechanically grinding a majority of the silicon, followed by a dry or wet chemical etch to remove the remaining portion (or a majority of the remaining portion). As an exemplary scenario in which a support layer is loosely attached to an RD structure formed (or displaced) thereon, block 850 includes separating or peeling to separate the support layer from the RD structure.

7F provides an exemplary diagram of various aspects of block 850 , for example, support layer removal aspects. For example, the support layer 705 (shown in FIG. 7E ) is removed from the RD structure 710 . As an example shown, RD structure 710 may still include a base dielectric layer 711 (e.g., oxide, nitride, etc.) as discussed herein.

In general, block 850 may include removing the support layer from the RD wafer. Accordingly, the scope of the present invention should not be limited to features of any particular type of wafer material or features of any particular manner of wafer material removal.

Exemplary method 800 may include, at block 855 , forming or patterning a first redistribution layer (RDL) dielectric layer to etch the oxide film of the RD structure. Block 855 includes forming and patterning the first RDL dielectric layer in any of a variety of ways, non-limiting examples described herein. Block 855 may share any or all features of block 255 of example method 200 shown in FIG. 2 and described herein, for example.

7G provides an exemplary diagram of various aspects of block 855 . For example, a first RDL dielectric layer 771 is formed and patterned over the base dielectric layer 711 . The patterned first RDL dielectric layer 771 may be formed by, for example, the base dielectric layer 711 may be etched (e.g., at block 860 ) and where the first traces (or regions thereof) will be formed. Vias 772 through the first RDL dielectric layer 771 may be included (e.g., at block 865 ).

Generally, block 855 includes forming and patterning a first dielectric layer (e.g., a first RDL dielectric layer), eg, over a base dielectric layer. Accordingly, the scope of the present invention should not be limited by the characteristics of a particular dielectric layer or by the features of a particular method of forming the dielectric layer.

Exemplary method 800 includes, at block 860, etching a base dielectric layer (e.g., oxide, nitride, etc.), such as unmasked regions thereof, from, for example, the RD structure. Block 860 may include performing etching in any of a variety of ways, with non-limiting examples described herein. Block 860 may share any or all features of block 260 of example method 200 shown in FIG. 2 and discussed herein, for example.

7G provides an exemplary diagram of various aspects of block 860 . For example, regions of the base dielectric layer 711 shown below the first conductive traces 712 in FIG. 7F are removed from FIG. 7G. This enables, for example, a metal-to-metal contact between the first conductive traces 712 and the first RDL traces at block 865 .

In general, block 860 includes, for example, etching the base dielectric layer. Accordingly, the scope of the present invention should not be limited by any particular manner of performing such etching.

The example method 800 may include, at block 865 , forming redistribution layer (RDL) traces. Block 865 may include forming RDL traces in any of a variety of ways, such as non-limiting examples described herein. Block 865 may share any or all features of block 265 of example method 200 shown in FIG. 2 and discussed herein, for example.

7G and 7H provide exemplary diagrams of various aspects of block 865 , eg, aspects of RDL trace formation. For example, a first region 781 of the RDL traces may be formed in the vias 772 of the RDL dielectric layer 771 and the first conductivity of the RD structure 710 exposed by the vias 772 . contacts traces 712 . Also, for example, the second region 782 of the first RDL traces may be formed on the first RDL dielectric layer 771 .

In general, block 865 may include forming redistribution layer (RDL) traces. Accordingly, the scope of the present invention should not be limited to features of any particular RDL traces or features of any particular manner of forming such RDL traces.

Note that although exemplary method 800 illustrates the formation of one RDL dielectric layer at block 855 and one RDL trace layer at block 865, these blocks may be repeated as many times as desired.

The example method 800 may include, at block 885 , forming interconnect structures over the RDL traces. Block 885 may include forming interconnect structures in any of a variety of ways, with non-limiting examples described herein. For example, block 885 may share any or all features of block 285 of example method 200 shown in FIG. 2 and discussed herein.

Block 885 may include, for example, conductive pillars (e.g., metal pillars, kappa pillars, solder capped pillars, etc.) and/or conductive bumps (e.g., solder bumps, etc.) over the RDL traces. ) may include the step of forming For example, block 885 may include plating conductive pillars, positioning or pasting conductive bumps.

7I provides an exemplary diagram of various aspects of block 885 , for example, bump forming aspects. For example, interconnect structures 792 (e.g., shown as solder capped metal pillars, eg, kappa pillars) are attached to the RDL traces 782 .

The redistribution layer(s) formed in blocks 855-885, which may also be referred to as a front side redistribution layer (RDL), is generally a fan-in assembly (e.g., generally a die) 725 and 726 (extending inward of the footprint of 725, 726), this may be the case, for example, in that at least some regions of interconnect structure 792 generally extend outwardly of the footprint of die 725, 726. It may also be formed as a fan-out assembly. Non-limiting examples of such assemblies are described herein.

In general, block 885 may include forming interconnect structures over the RDL traces and/or over the RDL dielectric layer, for example. Accordingly, the scope of the present invention should not be limited by the characteristics of any particular interconnect structures or by any particular manner of forming the interconnect structures.

Exemplary method 800 may include, at block 890 , debonding (or detaching) the wafer support structure attached at block 845 . Block 890 may include performing such debonding in any of a variety of ways, in non-limiting aspects described herein. For example, block 890 may share any or all features of block 290 of example method 200 shown in FIG. 2 and discussed herein.

7H and 7I provide exemplary views of various aspects of block 890 . For example, the wafer support structure 750 shown in FIG. 7H is removed in FIG. 7I.

In general, block 890 includes debonding the wafer support structure. Accordingly, the scope of the present invention should not be limited by any particular type of features of the wafer support structure or in any particular manner of debonding the wafer support structure.

Exemplary method 800 includes, at block 895 , cutting the wafer. Block 895 includes cutting the wafer in any of a variety of ways, including non-limiting examples described herein. Block 895 may share any or all features of block 295 of example method 200 shown in FIG. 2 and discussed herein.

The discussion here has generally focused on the discussing processing of a single die of an RD wafer. Such a focus on a single die of an RD wafer is for the sake of clarity only. It should be understood that all process steps (blocks) discussed herein may be performed over the entire wafer. For example, each and other views of the figures provided herein in FIGS. 7A-7L may be replicated tens or hundreds of times on a single wafer. For example, there may be no separation between one of the device assemblies shown and an adjacent device assembly of the wafer until separation.

Block 895 may include, for example, cutting (e.g., mechanical punch-cutting, mechanical saw-cutting, laser cutting, soft beam cutting, plasma cutting, etc.) from the wafer into individual packages. The result of such cutting may be, for example, the package shown in FIG. 7I . For example, the cut may include side surfaces of a package that include coplanar side surfaces of multiple parts of the package. For example, any or all of the side surfaces of mold material 730 , RD structure 710 dielectric layers, RDL dielectric layers 771 , underfill 728 , etc. may be coplanar.

In general, block 895 may include cutting the wafer. Accordingly, the scope of the present invention should not be limited by the features of any particular manner of cutting the wafer.

Exemplary method 800 includes, at block 896 , preparing a substrate, or wafer, or panel thereof for attachment of assembly 700I. Block 896 may include preparing the substrate in any of a variety of ways, including non-limiting examples described herein. Block 896 may share any or all features of blocks 205 and 210 of example method 200 shown in FIG. 2 and discussed herein, for example.

A substrate may include, for example, characteristics of any of a variety of substrates. For example, the substrate may include a package substrate, a motherboard substrate, a laminate substrate, a molded substrate, a semiconductor substrate, a glass substrate, and the like. Block 896 may include, for example, front side and/or backside surfaces for electrical and/or mechanical attachment. Block 896 may, for example, leave a panel, such as a substrate in the form of a panel, at this step and later cut individual packages, or cut individual substrates from the panel at this step.

Block 896 may also include receiving the substrate from a manufacturing station adjacent or upstream of the manufacturing facility, from another geographic location, or the like.

7J provides an exemplary diagram of various aspects of block 896 . For example, assembly 700J includes an exemplary substrate 793 ready for attachment.

In general, block 896 may include preparing a substrate, or wafer, or panel thereof for attachment of assembly 700I. Accordingly, the scope of the various aspects of the invention should not be limited by the features of a particular substrate or by the features of any particular manner of preparing the substrate.

Exemplary method 800 includes, at block 897 , attaching the assembly to the substrate. Block 897 may include attaching an assembly (e.g., assembly 700I or other assembly exaggerated in FIG. 7I ) in any of a variety of ways, including non-limiting examples described herein. Block 897 may share any or all features of block 220 of example method 200 shown in FIG. 2 and discussed herein, for example.

An assembly may include any of a variety of assemblies, non-limiting examples described herein, eg, features of all figures and/or related discussions herein. Block 897 may include attaching the assembly in any of a variety of ways. For example, block 897 may include attaching the assembly to the substrate using mass reflow, thermocompression bonding (TCB), conductive epoxy, or the like.

7J provides an exemplary view of various aspects of block 897 , eg, assembly attachment aspects. For example, assembly 700I shown in FIG. 7I is attached to substrate 793 .

Although not shown in FIG. 7J , in various exemplary embodiments (e.g., as shown in FIGS. 7K and 71), interconnect structures, e.g., through-mold interconnect structures, are formed by substrate 793 may be formed above. In these exemplary embodiments, although directed to forming interconnect structures over the substrate 793 , block 897 is a block ( ) of the exemplary method 200 shown in FIG. 2 and discussed herein. 215) may share any or all features. Note that such interconnect structures may be performed before or after attachment of the assembly, or may be performed before or after underfilling at block 898 .

In general, block 897 includes attaching the assembly to the substrate. Accordingly, the scope of the present invention should not be limited to any particular assembly, features of the substrate, or manner of attaching the assembly to the substrate.

Exemplary method 800 may include, at block 898 , underfilling the assembly over the substrate. Block 898 can include any of a variety of ways of underfilling, including non-limiting examples described herein. Block 898 may share any or all features of block 825 and/or block 225 of example method 200 shown in FIG. 2 and discussed herein, for example.

For example, after attaching the assembly at block 897 , block 898 may include underfilling the assembly using a capillary underfill. For example, the underfill may include a tack-reinforcing polymeric material capable of sufficiently flowing between the assembly and the substrate by capillary action.

Also for example, block 897 can be configured to use a non-conductive paste (NCP) and/or a non-conductive film (NCF) or tape while the assembly is attached at block 897 (e.g., using a thermocompression bonding process). may include underfilling the semiconductor die using For example, such underfill material may be deposited (e.g., printed, sprayed, etc.) prior to attachment of the assembly.

Like all blocks shown in example method 800, block 898 can be performed in any method 800 flow as long as the space between the assembly and the substrate is accessible.

Underfilling may also occur in other blocks of example method 800 . For example, underfilling may be performed as part of the substrate molding block 899 (e.g., using a molded underfill).

7K provides an exemplary diagram of various aspects of block 898, eg, underfilling aspects. An underfill 794 is positioned between the assembly 700I and the substrate 793 .

Although underfill 794 is shown generally flat, the underfill may rise and form fillets on the sides of assembly 700I and/or other components. As one example scenario, at least one-quarter or at least one-half of the side surface of assembly 700I may be covered with an underfill material. As another example scenario, one or more or all of the side surfaces of assembly 700I may be covered with an underfill material. Also, for example, a significant portion of the space directly between assembly 700I and other components and/or between other components (shown in the various figures) may be filled with underfill material 794 . For example, at least one-half or all of the space between assembly 700I and laterally adjacent components may be filled with an underfill material.

As shown in FIG. 7J , assembly 700J includes a first underfill 728 between the dies 725 and 726 and the RDL structure 710 , and a second underfill 728 between the RD structure 710 and the substrate 793 . 794) may be included. Such underfills 728 and 794 may be different, for example. For example, in an exemplary scenario in which the distance between the dies 725 and 726 and the RD structure 710 is less than the distance between the RD structure 710 and the substrate 793 , the first underfill 728 is the second underfill (794) may generally include a smaller filler size (or higher viscosity). In other words, the second underfill 794 is less expensive than the first underfill 728 .

Also, each of the underfilling processes performed in blocks 898 and 825 may be different. For example, block 898 may include the use of a non-conductive paste (NCP) underfill scheme, while block 825 may include the use of a capillary underfill scheme.

As another example, blocks 825 and 898 may include concurrently performed in the same underfilling process, eg, after block 897 . Also, as discussed herein, a molded underfill may also be used. As such an example scenario, it may include performing underfilling in either or both of blocks 825 and/or 898 during the substrate molding process. For example, block 898 may be performed at block 899 as a mold underfill process, while block 825 may include performing a capillary underfill process.

In general, block 898 may include underfilling the assembly and/or components attached to the substrate at block 897 . Furthermore, the scope of the present invention should not be limited by any particular type of underfill or by any particular manner of performing underfilling.

Exemplary method 800 may include, at block 899 , molding the substrate. Block 899 may include performing such molding in any of a variety of ways, including non-limiting examples described herein. Block 899 may share any or all features of block 830 and/or block 230 of example method 200 shown in FIG. 2 and discussed herein, for example.

For example, block 899, if formed over a substrate (e.g., conductive balls, ellipsoids, columns or pillars (e.g., plated pillars, wires or wire bond wires, etc.), etc.), sub molding along the top surface of the straight, along the assembly attached at block 897, along the TMV interconnect structures.

Block 899 may include, for example, using transfer molding, compression molding, or the like. Block 899 may include, for example, using a panel-molding process in which multiple substrates are connected to form a panel and molded together, or block 899 may include molding the substrates individually. may include. In a panel-molding scenario, after panel molding, block 899 may include performing a cutting process whereby the individual substrates are separated from the substrates.

The molding material may include, for example, any of a variety of features. For example, a molding material (e.g., an epoxy molding compound (EMC), an epoxy resin molding compound, etc.) may comprise a relatively high modulus, eg, to provide package support in subsequent processing. Also, for example, the molding material may include a relatively low modulus to provide package flexibility in subsequent processing.

Block 899 may include, for example, using a mold material different from the mold material used in block 830 . For example, block 899 may use a mold material having a lower modulus than the mold material used in block 830 . As such a scenario, the more robust regions of the assembly may be relatively stronger than the surrounding regions, provided that they are for absorption of various forces.

As an example scenario in which mold material 735 of assembly 700K and mold material 730 of assembly 700I are formed at different and/or different stages and/or formed using different types of processes, block ( 899 (or other block) may include preparing the mold material 730 for adhesion to the mold material 735 . For example, the mold material 730 may be physically or chemically etched. Mold material 730 may be etched with plasma, for example. Also, for example, grooves, indentations, protrusions, or other physical features may be formed in the mold material 730 . Also, for example, an adhesive may be placed on the mold material 730 .

Block 899 may use, for example, a different type of molding process than that used in block 830 . As an exemplary scenario, block 899 may use a transfer molding process, while block 830 may use a compression molding process. As such an exemplary scenario, block 830 may use a mold material specifically adapted for compression molding, and block 899 may use a mold material specifically adapted for transfer molding. Such mold materials may, for example, have distinctly different material properties (flow properties, curing properties, hardness properties, particle size properties, chemical compound properties).

As described herein, for example, with respect to block 898 , the molding process of block 899 may provide an underfill between assembly 700I and substrate 793 and/or die ( An underfill may be provided between 725 and 726 and the RD structure 710 . As such, the material uniformity between the molded underfill material encapsulating the substrate 793 and assembly 700I and/or the mold material encapsulating the RD structure 710 and the semiconductor dies 725 and 726 is there may be

7K provides an exemplary diagram of various aspects of block 899 , eg, molding aspects. For example, a molded assembly 700K is shown with interconnect structures 795 and mold material 735 covering assembly 700I. Although mold material 735 , which may be referred to herein as an encapsulant, is shown leaving the top of assembly 700I exposed, this need not be the case. For example, block 899 does not require a thinning (or grinding) operation to completely cover assembly 700I and then expose the top of assembly 700I.

Mold material 735 may generally directly contact and cover areas of assembly 700I that are not covered, for example, with underfill 794 . For example, in a scenario where at least a first area of the sides of assembly 700I is covered with underfill 794 , mold material 735 may directly contact and cover a second area of the sides of assembly 700I. Further, the mold material 735 may extend to the edge of the substrate 793 in a lateral direction and thus may include a side surface that is coplanar with the substrate 793 . Such an assembly may be formed, for example, in a panel-molding manner, and then singulation to separate the packages from the panel may be performed.

In general, block 899 includes molding the substrate. Accordingly, the scope of the present invention should not be limited to any particular molding material, structure, and/or technique.

Exemplary method 800 includes forming interconnect structures on the substrate at block 886 , for example on the side of the substrate on the opposite side to which the assembly is attached at block 897 . . The interconnect structures may include features of any of the various types of interconnect structures, for example structures used to connect a semiconductor package to another package or motherboard. For example, the interconnect structures may include conductive balls (e.g., solder balls) or bumps, conductive posts, and the like.

7K provides an exemplary diagram of various aspects of block 886, eg, aspects of forming interconnections. For example, interconnect structures 792 are shown attached to lands 791 of substrate 793 .

In general, block 886 includes forming interconnect structures on the substrate. Accordingly, the scope of the present invention should not be limited by the characteristics of or in any particular manner of forming such structures.

As discussed herein, underfill 728 may cover at least one of the sides of die 725 , 726 , and/or underfill 794 may cover at least one of the sides of assembly 700I. have. 7L provides an illustrative example of such an application. For example, assembly 700I is shown with underfill 728 contacting one of the sides of die 725 and 726 . As discussed herein, during the cutting process, the underfill 728 may be cut and a flat side including the side surface of the RDL structure 710 , the side surface of the mold material 730 and the side surface of the underfill 728 . An assembly 700I comprising a surface is formed.

Assembly 700L, which may also be referred to as a package, includes a region of one of the sides of assembly 700I (e.g., sides of RD structure 710 , sides of underfill 728 , and sides of mold material 730 ). ) are shown with an underfill 794 in contact. Note that, as discussed herein, the underfill 794 may include a molded underfill that, in various embodiments, is the same material as the mold material 735 . Mold material 735 is shown encapsulating substrate 793 , interconnect structures 795 , underfill 794 , and assembly 700I. Although in the exemplary embodiment, the tops of assembly 700I and interconnect structures 795 are exposed from mold material 735, this need not be the case.

7 and 8 illustrate various exemplary method aspects and variations thereof. Other exemplary method aspects will now be described with reference to additional drawings.

As discussed herein in the discussion of FIGS. 7 and 8 , block 835 may include grinding (or other thinning) the mold material 730 to expose one or more dies 725 , 726 . An example is provided in FIG. 7D .

As also discussed, at block 835 mold grinding (or thinning) need not be performed or may be performed to the extent that it still leaves the tops of dies 725 and 726 covered with mold material 730 . An example is provided in FIG. 9 , in which mold material 735 covers the tops of dies 725 and 726 of assembly 700I.

Also, as discussed herein, interconnect structures may be formed over the substrate, for example with respect to block 897 and FIGS. 7K and 71 , in various exemplary embodiments. An example is provided in FIG. 9 . For example, although the tops of interconnect structures 795 are initially covered by mold material 735 , vias 940 are removed from mold material 735 to reveal interconnect structures 795 . is formed

Also, in various exemplary embodiments, the TMV interconnect structures need not be formed over the substrate, as discussed herein in the discussion of FIGS. 7 and 8 . An example is provided in FIG. 10A . As shown in FIG. 10A , as opposed to FIG. 7K , there are no TMV interconnect structures 795 formed. Also, as shown in FIG. 10A , in contrast to the block in FIG. 1K , the mold material 735 does not cover the interconnect structures.

Also, for example, as described herein, mold grinding (or thinning) of block 899 is skipped or covered with mold material 735 of assembly 700I and/or of at least one die 725, 726. It can be done to the extent that it leaves the top. 10A provides an exemplary diagram of such a process. In general, assembly 1000A of FIG. 10A is similar to assembly 700K of FIG. 7K , with mold material 735 covering assembly 700I without interconnect structures 795 .

Also, as described herein, mold grinding (or thinning) at block 899 may result in assembly 700I and/or die of assembly from mold material 735 (and/or mold material 730). 725,726) to the extent of exposing one or more tops. 10B provides an exemplary diagram of such a process. In general, assembly 1000B of FIG. 10B is similar to assembly 700K of FIG. 7K , except for interconnect structures 795 .

As another example, as described herein in the discussion of block 897 , the TMV interconnect structures may include any of a variety of structures, eg, conductive pillars (e.g., plated posts or pillars, vertical wires, etc.). can 11A provides an exemplary view of conductive pillars 1121 attached to a substrate 793 . The conductive pillars 1121 may be formed by plating on the substrate 793 , for example. The conductive pillars 1121 also include, for example, wires attached to the substrate 793 (e.g., wire-bond attachment, soldering, etc.) and extending in the vertical direction (e.g., wire-bond wires). can do. The conductive pillars 1121 may be, for example, from the substrate 793 to a height greater than the height of the dies 725 and 726 , equal to the height of one or more dies 725 , 726 , or less than the height of the dies 725 , 726 . can be extended Note that any number of columns of pillars 1121 may be formed. In general, assembly 1100A of FIG. 11A is similar to assembly 700K (except mold compound 735) of FIG. 7K with conductive pillars 1121 instead of conductive balls 795 extending as interconnect structures. do.

Continuing the example, FIG. 11B shows a substrate 793 covered with mold material 735 , conductive pillars 1121 , assembly 700I (e.g., semiconductor dies 725 and 726 ), and an underfill 794 . shows Molding may be performed, for example, according to block 899 of example method 800 . In general, assembly 1100B of FIG. 11B has conductive pillars 1121 instead of conductive balls 795 extending as interconnect structures, and a mold that is not thinned or not thinned enough to expose assembly 700I. Similar to assembly 700K of FIG. 7K with material 735 .

Still continuing the example, FIG. 11C shows the mold material 735 thinned (e.g., ground) to a desired thickness. Thinning may be performed, for example, according to block 899 of example method 800 . Note that, for example, conductive pillars 1121 and/or assembly 700I (e.g., including mold material 730 and/or semiconductor die 725, 726) may be thinned. For example, thinning of the mold material 735 may expose the upper ends of the conductive pillars 1121 . However, if the mold material 735 does not expose the upper ends of the conductive pillars 1121 , a mold removal operation may be performed. Note that although assembly 1100C is shown with the tops of semiconductor die 725 and 726 of assembly 700I exposed, the tops need not be exposed.

In general, assembly 1100C of FIG. 11C is similar to assembly 700K of FIG. 7K with conductive pillars 1121 instead of conductive balls 795 extending as interconnect structures.

Continuing the example, assembly 1100C shown in FIG. 11C includes redistribution layers along mold material 735 and assembly 700I (e.g., including mold material 730 and/or semiconductor dies 725 and 726). An additional process of forming (RDL) 1132 may be performed. 11D shows an example of such a process. The redistribution layer 1132 may also be referred to herein as a backside redistribution (RDL) layer 1132 . Although this backside RDL formation is not explicitly shown in one of the blocks of the exemplary method 800 , such an operation is, for example, after a mold grinding operation (if performed) block 899 , It can be performed in any blocks.

11D, a first backside dielectric layer 1133 is to be formed and patterned over mold material 735 and assembly 700I (e.g., including mold material 730 and/or semiconductor dies 725, 726). can First backside dielectric layer 1133 may be formed and patterned, for example, in the same or similar manner as RDL dielectric layer 771 formed in block 855, albeit on a different surface. For example, first backside dielectric layer 1133 over mold material 735 and/or over assembly 700I (e.g., including mold material 730 and/or semiconductor dies 725 and 726), for example a die Directly over the exposed backside surfaces of 725 , 726 , over mold material 730 or 735 covering the backside surfaces of die 725 , 726 , and vias 1134 at least a top of conductive pillars 1121 . may be formed on the first backside dielectric layer 1133 (e.g., by etching, ablation) to expose them.

Backside traces 1135 may be formed over the first backside dielectric layer 1133 and inside the vias 1134 of the first backside dielectric layer 1133 . Backside traces 1135 may thus be electrically connected to conductive pillars 1121 . Backside traces 1135 may be formed, for example, in the same manner as or similar to RDL traces 782 formed at block 865 . At least some, but not all, of the backside traces 1135 are, for example, the region immediately above the assembly 700I (e.g., the mold material 730 and/or the semiconductor die 725 , 726 ) from the conductive pillars 1121 . can be extended up to At least some of the backside traces 1135 are also not located directly above the assembly 700I (e.g., the mold material 730 and/or the semiconductor die 725, 726), for example, from the conductive pillars 1121. area can be extended.

A second backside dielectric layer 1136 may be formed and patterned over the first backside dielectric layer 1133 and the backside traces 1135 . Second backside dielectric layer 1136 may be formed and patterned, for example, in the same or similar manner as RDL dielectric layer 771 formed in block 855, albeit on a different surface. For example, a second backside dielectric layer 1136 may be formed over the first backside dielectric layer 1133 and over the backside traces 1135 , and vias 1137 are the contacts of the backside traces 1135 . A second backside dielectric layer 1136 may be formed (e.g., by etching, ablation, etc.) to expose regions.

Backside interconnect pads 1138 (e.g., ball contact pads, lands, terminals, etc.) are formed over the second backside dielectric layer 1136 and/or in the vias 1137 of the second backside dielectric layer 1136 . can be Backside interconnect pads 1138 may thus be electrically connected to backside traces 1135 . Backside interconnect pads 1138 may be formed, for example, in the same or similar manner as the RDL traces formed in block 865 . The backside interconnect pads 1138, thus, form metal contact pads and/or improve subsequent adhesion to the backside traces 1135 by under bump metal (e.g., other interconnect structures). ) can be formed by forming

Although the backside RDL layer 1132 is shown as two backside dielectric layers 1133, 1136 and one layer of backside traces 1135, it should be understood that any number of dielectric and/or trace layers may be formed. .

Although not shown in FIG. 11D , interconnect structures are attached to the substrate 793 , for example, as discussed herein with respect to block 886 and FIG. 7K , for example, assembly 700I and mold material 735 . ) on the opposite side of the substrate 793 .

As another illustrative embodiment, a substrate (e.g., laminate substrate, package substrate, etc.) may be used, for example, instead of or in addition to the backside RDL discussed herein with respect to FIGS. 11A-11D , assembly 700I (e.g., semiconductor). dies 725 and 726 , and mold material 730 ) and mold material 735 .

For example, as shown in FIG. 12A , interconnect structures 795 can be formed with a height that extends at least to the height of assembly 700I. Note that this height need not necessarily be, for example, in a scenario where the backside substrate has its own interconnect structure or additional interconnect structures are used between interconnect structures 795 and the backside substrate. do it. Interconnect structures 795 may be attached, for example, in a manner similar to or similar to that discussed herein with respect to block 897 and FIG. 7K .

Continuing the example, as shown in FIG. 12A , assembly 1200A can be molded with mold material 735 and can be thinned if desired. Such molding and/or thinning may be performed, for example, in a manner as or similar to that discussed herein with respect to block 899, and FIG. 7K.

As shown in FIG. 12B , a backside substrate 1232 may be attached. For example, backside substrate 1232 is electrically connected to interconnect structures 795 and/or mold material 735 and/or assembly 700I (e.g., mold material 730 and/or semiconductor dies 725 and 726). The backside substrate 1232 may be attached, for example, in the form of a panel and/or in a single package, and may be attached, for example, before or after singulation.

As discussed herein, after assembly 700I is attached to substrate 793 , substrate 793 and/or assembly 700I may be covered with a mold material. Alternatively, or in addition, the substrate 793 and/or assembly 700I may be covered by a lid or stiffener. 13 provides an illustrative example. 13 generally shows assembly 700J of FIG. 7J with the addition of a lid 1310 (or stiffener).

Lid 1310 includes, for example, metal and provides electromagnetic shielding and/or heat dissipation. For example, lid 1310 may be electrically connected to a ground trace on substrate 793 to provide shielding. Lid 1310 may be connected to substrate 793 with, for example, solder and/or conductive epoxy. Although not shown, a thermal interface material may be formed in the gap 1315 between the assembly 700I and the lid 1310 .

Although most of the examples shown and discussed herein generally only show assembly 700I attached to substrate 793 , other components (e.g., active and/or passive components) are attached to substrate 793 . It can also be attached. For example, as shown in FIG. 14 , a semiconductor die 1427 may be attached to a substrate 793 (e.g., by flip chip bonding, wire bonding, etc.). A semiconductor die 1427 is attached to the substrate 793 in a horizontally adjacent manner to assembly 700I. After this attachment, any of the packaging structures discussed herein (e.g., interconnect structures, moldings, lids, etc.) may be formed.

As another exemplary embodiment, other components may be connected to the upper side of assembly 700I, in a vertical stacking assembly. 15 shows an example of such an assembly 1500C. A third die 1527 and a fourth die 1528 (e.g., inactive sides) may be attached to the top of the assembly 700I. Such attachment can be effected, for example, using an adhesive. The bond pads on the active sides of the third die 1527 and the fourth die 1528 may then be wire bonded to the substrate 793 . In a scenario where RDLs and/or substrates are attached along assembly 700I, a third die 1527 and/or a fourth die 1528 may be flip-chip attached to such RDLs and/or substrates. Note that you can After such attachment, any of the packaging structures discussed herein (e.g., interconnect structures, moldings, lids, etc.) may be formed.

As another exemplary embodiment, other components may be connected to the bottom of the substrate. 16 shows an example of such an assembly. A third die 1699 is attached to the bottom side of the substrate 793 , for example between gaps between interconnect structures on the bottom side of the substrate 793 . After this attachment, any of the packaging structures discussed herein (e.g., interconnect structures, moldings, lids, etc.) may be formed.

The exemplary methods and assemblies shown in Figures 8-16 and discussed herein are merely non-limiting examples shown to illustrate various aspects of the present invention. Such methods and assemblies may share any or all features of the methods and assemblies shown and discussed in the following common pending US patent applications: filed Jan. 29, 2013, "Semiconductor Device and U.S. Patent Application Serial No. 13/753,120, entitled "Method of Manufacturing Semiconductor Device;" U.S. Patent Application No. 13/863,457, filed April 16, 2013, and entitled "Semiconductor Device and Method of Manufacturing Same;" U.S. Patent Application Serial No. 14/083,779, filed November 19, 2013, and entitled "Semiconductor Device with Deep Wells Without Through Silicon Vias;" U.S. Patent Application No. 14/218,265, filed March 18, 2014, and entitled "Semiconductor Device and Method of Making the Same"; U.S. Patent Application No. 14/313,724, filed June 24, 2014, and entitled "Semiconductor Device and Method of Manufacturing Same;" US Patent Application No. 14/444,450, filed July 28, 2014, and entitled "Semiconductor Device With Thin Redistribution Layers;" US Patent Application Serial No. 14/524,443, filed October 27, 2014, and entitled "Semiconductor Device with Reduced Thickness;" US Patent Application No. 14/532,532, filed on November 4, 2014, and entitled "Interposer, Method of Manufacturing Same, Semiconductor Package Using Same, and Method of Manufacturing Semiconductor Package;" U.S. Patent Application Serial No. 14/546,484, filed November 18, 2014, and entitled "Semiconductor Device with Reduced Warpage;" and U.S. Patent Application Serial No. 14/671,095, filed March 27, 2015, entitled “Semiconductor Device and Method of Manufacturing Same;” The entire contents of each of which are herein incorporated by reference.

The discussion herein includes numerous illustrative figures showing various regions of a semiconductor package assembly. For illustrative clarity, such drawings do not depict all aspects of each illustrative assembly. Any example assemblies described herein share any or all features of any or all assemblies described herein. For example and without limitation, any example assemblies shown and discussed with respect to FIGS. 1-7, or regions thereof, may be coupled to any example assemblies discussed with respect to FIGS. 8-16. Conversely, any assemblies shown and discussed with respect to FIGS. 8-16 may be coupled to the assemblies shown and discussed with respect to FIGS. 1-7.

In summary, various aspects of the present invention provide a semiconductor device or package structure and a method of manufacturing the same. While this has been described with reference to specific embodiments and examples, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from the scope of the present invention. Accordingly, it is intended that the invention not be limited to the particular example(s) disclosed, but that the invention will include all examples falling within the scope of the appended claims.

Claims (30)

a front redistribution structure (“FSRDS”) comprising a first FSRDS dielectric layer;
a semiconductor die comprising a front die side and a back die side, the front die side coupled to a top side of the front redistribution structure;
a stacked part interconnect structure comprising an upper side and a lower side, wherein a lower side of the stacked part interconnect structure is coupled to an upper side of the front redistribution structure, the upper side of the stacked part interconnect structure vertically at least as high as a rear die side extended - ;
an encapsulating material on the upper side of the front redistribution structure and laterally surrounding the semiconductor die; and
a rear redistribution structure (“BSRDS”), wherein the rear redistribution structure includes:
a first BSRDS dielectric layer on the top side of the encapsulating material;
a first BSRDS conductive via extending completely through the first BSRDS dielectric layer and coupled to a top side of the stacked component interconnect structure;
a first BSRDS trace on a top side of the first BSRDS dielectric layer;
a second BSRDS dielectric layer on a top side of the first BSRDS dielectric layer, the second BSRDS dielectric layer covering side sides of the first BSRDS trace and a top side of the first BSRDS trace;
a second BSRDS conductive via coupled to the top side of the first BSRDS trace and extending vertically from the top side of the first BSRDS trace to the top side of the second BSRDS dielectric layer; and
and a top side component connection pad coupled to a second BSRDS conductive via. According to claim 1,
and the first BSRDS conductive via comprises a single metal layer extending completely through the first BSRDS dielectric layer. 3. The method of claim 2,
and the first BSRDS conductive via runs only in a substantially vertical direction through the first BSRDS dielectric layer. According to claim 1,
the front redistribution structure includes a second FSRDS dielectric layer and a third FSRDS dielectric layer; and
wherein each of the first FSRDS dielectric layer, the second FSRDS dielectric layer, and the third FSRDS dielectric layer laterally surrounds the plurality of conductive layers. According to claim 1,
The front redistribution structure is:
bottom FSRDS dielectric layer; and
a ball contact comprising a plated pad layer embedded in an underlying FSRDS dielectric layer; and
and a lower side of the plated pad layer is higher than a lower side of the lower FSRDS dielectric layer. a first FSRDS dielectric layer;
a second FSRDS dielectric layer; and
a third FSRDS dielectric layer;
Each of the first FSRDS dielectric layer, the second FSRDS dielectric layer, and the third FSRDS dielectric layer includes a front surface redistribution structure (“FSRDS”) that laterally surrounds a plurality of FSRDS conductive layers;
a first semiconductor die comprising a front die side and a back die side, the front die side coupled to a top side of the front redistribution structure;
a first laminated part interconnect structure comprising an upper side and a lower side, wherein a lower side of the first laminated part interconnect structure is coupled to an upper side of the front redistribution structure, and wherein the upper side of the first laminated part interconnect structure is at least a rear surface vertically extended as high as the side of the die - ;
a second laminated part interconnect structure comprising an upper side and a lower side, wherein a lower side of the second laminated part interconnect structure is coupled to an upper side of the front redistribution structure, and wherein the upper side of the second laminated part interconnect structure is at least a rear surface vertically extended as high as the side of the die - ;
an encapsulating material on a top side of the front redistribution structure and laterally surrounding the first semiconductor die; and
a rear redistribution structure (“BSRDS”), wherein the rear redistribution structure includes:
a first BSRDS dielectric layer on the top side of the encapsulating material;
a first BSRDS conductive via extending completely through the first BSRDS dielectric layer and coupled to a top side of the first stacked component interconnect structure;
a first BSRDS trace on a top side of the first BSRDS dielectric layer;
a second BSRDS dielectric layer on a top side of the first BSRDS dielectric layer, the second BSRDS dielectric layer covering side sides of the first BSRDS trace and a top side of the first BSRDS trace; and
a top via extending through the second BSRDS dielectric layer from a top side of the second BSRDS dielectric layer to a top side of the first BSRDS trace. 7. The method of claim 6,
A semiconductor device comprising: a second semiconductor die; wherein the first and second semiconductor dies are laterally positioned between the first and second stacked component interconnect structures. 8. The method of claim 7,
A semiconductor device comprising an underfill positioned directly between the first and second semiconductor dies. 7. The method of claim 6,
A semiconductor device comprising: an underfill having a side side that is coplanar with a side side of the front redistribution structure. providing a front surface redistribution structure (“FSRDS”) comprising a first FSRDS dielectric layer;
providing a semiconductor die comprising a front die side and a back die side, the front die side coupled to a top side of the front redistribution structure;
providing a laminated part interconnect structure comprising an upper side and a lower side, wherein a lower side of the laminated part interconnect structure is coupled to an upper side of the front redistribution structure, wherein the upper side of the laminated part interconnect structure is at least as large as a rear die side vertically extended high - ;
providing an encapsulating material on the upper side of the front redistribution structure and laterally surrounding the semiconductor die; and
Provide a rear redistribution structure (“BSRDS”), wherein the rear redistribution structure includes:
a first BSRDS dielectric layer on the top side of the encapsulating material;
a first BSRDS conductive via extending completely through the first BSRDS dielectric layer and coupled to a top side of the stacked component interconnect structure;
a first BSRDS trace on a top side of the first BSRDS dielectric layer;
a second BSRDS dielectric layer on a top side of the first BSRDS dielectric layer, the second BSRDS dielectric layer covering side sides of the first BSRDS trace and a top side of the first BSRDS trace;
a second BSRDS conductive via coupled to the top side of the first BSRDS trace and extending vertically from the top side of the first BSRDS trace to the top side of the second BSRDS dielectric layer; and
and a top side component connection pad coupled to a second BSRDS conductive via. 11. The method of claim 10,
A method of manufacturing a semiconductor device, wherein the first BSRDS dielectric layer is free of any buried traces running in the horizontal direction. 11. The method of claim 10,
the front redistribution structure includes a second FSRDS dielectric layer and a third FSRDS dielectric layer; and
wherein each of the first FSRDS dielectric layer, the second FSRDS dielectric layer, and the third FSRDS dielectric layer laterally surrounds the plurality of conductive layers. upper FSRDS side;
lower FSRDS side;
side FSRDS side between upper FSRDS side and lower FSRDS side;
a first FSRDS dielectric layer; and
a front surface redistribution structure (“FSRDS”) comprising a first FSRDS conductive layer comprising a first FSRDS conductive trace;
a semiconductor die comprising a front die side and a back die side, the front die side coupled toward the top FSRDS side, the semiconductor die comprising a conductive pad electrically coupled to the first FSRDS conductive layer;
Stacked Component Interconnect Structure (“SCIS”) comprising an upper SCIS side and a lower SCIS side, the lower SCIS side being coupled to the upper FSRDS side and electrically coupled to the first FSRDS conductive layer, the upper SCIS side being at least a rear die side vertically extended as high as - ;
An encapsulating material on the upper FSRDS side and laterally surrounding the semiconductor die, the encapsulating material comprising:
upper encapsulating material side;
a lower encapsulating material side facing the front redistribution structure; and
a side encapsulating material side between the upper encapsulating material side and the lower encapsulating material side; and
a rear redistribution structure (“BSRDS”), wherein the rear redistribution structure includes:
upper BSRDS side;
lower BSRDS side joined to upper SCIS side;
a first BSRDS dielectric layer on the back die side and the top encapsulation material side; and
a first BSRDS conductive layer comprising a first BSRDS conductive trace electrically coupled to the stacked component interconnect structure;
wherein the front redistribution structure comprises a build-up redistribution structure and the back redistribution structure comprises a laminate substrate. 14. The method of claim 13,
The laminated component interconnect structure comprises a copper-core solder structure. 14. The method of claim 13,
The laminated component interconnect structure comprises an elongated conductive ball. 14. The method of claim 13,
the laminated part interconnect structure includes a core of a first metal surrounded by a second metal; and
The encapsulating material laterally surrounds the entire core. 14. The method of claim 13,
wherein the back die side is exposed from the encapsulating material. 14. The method of claim 13,
the rear redistribution structure includes a side BSRDS side between the upper BSRDS side and the lower BSRDS side; and
wherein the side FSRDS side, the side encapsulation material side, and the side BSRDS side are coplanar. 14. The method of claim 13,
A semiconductor device comprising an underfill material positioned directly vertically between the semiconductor die and the front surface redistribution structure. a first FSRDS side;
a second FSRDS side opposite the first FSRDS side;
a side FSRDS side between the first FSRDS side and the second FSRDS side;
a first FSRDS dielectric layer; and
a first side redistribution structure (“FSRDS”) comprising a first FSRDS conductive layer comprising a first FSRDS conductive trace;
a semiconductor die comprising a first die side and a second die side opposite the first die side, the second die side facing the first FSRDS side and coupled to the first FSRDS side;
A stacked part interconnect structure (“SCIS”) comprising a first SCIS side and a second SCIS side opposite the first SCIS side, the second SCIS side being coupled to the first FSRDS side and electrically connected to the first FSRDS conductive layer coupled, vertically across the entire semiconductor die - ;
an encapsulating material on the first FSRDS side and laterally surrounding the semiconductor die, the encapsulating material comprising:
a first encapsulating material side;
a second encapsulating material side opposite the first encapsulating material side and facing the first side redistribution structure; and
a side encapsulating material side between the first encapsulating material side and the second encapsulating material side; and
a second side redistribution structure (“SSRDS”), wherein the second side redistribution structure comprises:
a first SSRDS side;
a second SSRDS side facing the first SSRDS side and coupled to the first SCIS side;
a side SSRDS side between the first SSRDS side and the second SSRDS side;
a first SSRDS dielectric layer; and
a first SSRDS conductive layer comprising a first SSRDS conductive trace electrically coupled to the stacked component interconnect structure;
one of the first side redistribution structure and the second side redistribution structure includes a build-up redistribution structure; and
and the other of the first side redistribution structure and the second side redistribution structure comprises a laminate substrate. 21. The method of claim 20,
and the second side redistribution structure comprises a laminate substrate. 21. The method of claim 20,
wherein the semiconductor die includes a die pad on a second die side. The semiconductor device of claim 20 , wherein the side FSRDS side, the side encapsulation material side, and the side SSRDS side are coplanar. 21. The method of claim 20,
The laminated component interconnect structure comprises a copper-core solder structure. 21. The method of claim 20,
A semiconductor device comprising: an underfill material positioned directly vertically between the semiconductor die and the first side redistribution structure. 21. The method of claim 20,
and the second SSRDS side is mechanically attached to the first die side. a first FSRDS side;
a second FSRDS side opposite the first FSRDS side;
a side FSRDS side between the first FSRDS side and the second FSRDS side;
a first FSRDS dielectric layer; and
providing a first lateral redistribution structure (“FSRDS”) comprising; a first FSRDS conductive layer comprising a first FSRDS conductive trace;
providing a semiconductor die comprising a first die side and a second die side opposite the first die side, the second die side facing the first FSRDS side and coupled to the first FSRDS side;
providing a laminated part interconnect structure (“SCIS”) comprising a first SCIS side and a second SCIS side opposite the first SCIS side, the second SCIS side coupled to the first FSRDS side and a first FSRDS conductive layer is electrically coupled to the - and vertically traverses the entire semiconductor die;
An encapsulating material is provided on the first FSRDS side and laterally surrounding the semiconductor die, the encapsulating material comprising:
a first encapsulating material side;
a second encapsulating material side opposite the first encapsulating material side and facing the first side redistribution structure; and
a side encapsulating material side between the first encapsulating material side and the second encapsulating material side; and
A second side redistribution structure (“SSRDS”) is provided, wherein the second side redistribution structure comprises:
a first SSRDS side;
a second SSRDS side facing the first SSRDS side and coupled to the first SCIS side;
a side SSRDS side between the first SSRDS side and the second SSRDS side;
a first SSRDS dielectric layer; and
a first SSRDS conductive layer comprising a first SSRDS conductive trace electrically coupled to the stacked component interconnect structure;
one of the first side redistribution structure and the second side redistribution structure includes a build-up redistribution structure; and
and the other of the first side redistribution structure and the second side redistribution structure comprises a laminate substrate. 28. The method of claim 27,
and the second side redistribution structure comprises a laminate substrate. 28. The method of claim 27,
A method of manufacturing a semiconductor device, comprising: forming a side FSRDS side surface, a side encapsulating material side surface, and a side SSRDS side side to be flush. 28. The method of claim 27,
A method of manufacturing a semiconductor device, comprising providing an underfill material directly between the semiconductor die and the first lateral redistribution structure.

Images