CN105097720B - The forming method of encapsulating structure - Google Patents

The forming method of encapsulating structure Download PDF

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Publication number
CN105097720B
CN105097720B CN201510372267.8A CN201510372267A CN105097720B CN 105097720 B CN105097720 B CN 105097720B CN 201510372267 A CN201510372267 A CN 201510372267A CN 105097720 B CN105097720 B CN 105097720B
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connecting key
chip
carrier
layer
encapsulating structure
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CN105097720A (en
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石磊
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Tongfu Microelectronics Co Ltd
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Tongfu Microelectronics Co Ltd
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A kind of forming method of encapsulating structure, including：The carrier with chip region is provided, carrier has the 3rd surface and the 4th surface；The slot through carrier is formed in carrier；The chip with first surface and second surface is fixed on the 3rd surface of support core section, the first surface of chip and the 3rd surface of carrier interfix；The fixed connecting key for including conductor wire, first end and the second end in slot, the first end of connecting key and the second end expose conductor wire, the first end of connecting key is located in slot, the first end of connecting key protrudes from or is flush to the 4th surface of carrier, and the second end of connecting key is flush to the functional areas surface of chip；The plastic packaging layer for surrounding chip and connecting key is formed on the 3rd surface of carrier；The wiring layer again and the first soldered ball electrically connected with the second end of connecting key and the functional areas of chip is formed in plastic packaging layer surface.The forming method of the encapsulating structure is simple, process costs reduce, the encapsulating structure accurate size formed and diminution.

Description

The forming method of encapsulating structure
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of encapsulating structure.
Background technology
In the prior art, chip is that the side of (Wire Bonding) is bonded by metal lead wire with the connection of external circuit Formula realization, i.e. Wire Bonding Technology.As the feature size downsizing of chip and the integrated level of integrated circuit improve, wire bonding skill The art no longer growth requirement of applicable technology.
In order to improve the integrated level of chip package, Stacked Die Packaging (stacked die package) technology gradually into For the main flow of technology development.Stacked Die Packaging technology, also known as three-dimensional packaging technology, specifically stacked in same packaging body The encapsulation technology of at least two chips.Stacked Die Packaging technology can realize the Large Copacity of semiconductor devices, multi-functional, small chi The technical need such as very little, inexpensive, therefore laminated chips technology is flourished in recent years.
By taking the memory using stacked package technology as an example, compared to the memory for not using Stack Technology, using heap The memory of folded encapsulation technology can possess more than twice of memory capacity.In addition, more can be effective using stacked package technology Ground utilizes the area, USB flash disk, SD card more applied to big memory space etc. of chip.
Stacked chips encapsulation technology can be realized by multiple technologies means, such as routing technique, silicon hole (through silicon via, abbreviation TSV) technology or plastic packaging through hole (through molding via, abbreviation TMV) skill Art.
However, above-mentioned technological means still faces various technique limitations and cost limitation, further subtract moreover, being faced with The problem of thin encapsulating structure thickness.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of forming method of encapsulating structure, the forming method letter of the encapsulating structure Single, process costs reduce, the encapsulating structure accurate size formed and diminution.
To solve the above problems, the present invention provides a kind of forming method of encapsulating structure, including：Carrier, the load are provided Body has chip region, and the carrier has relative the 3rd surface and the 4th surface；If in the carrier formed one or Dry slot, the slot run through the carrier；The 3rd surface fixed chip in the support core section, the chip have Relative first surface and second surface, the second surface of the chip include functional areas, the first surface and load of the chip 3rd surface of body interfixes；Key is fixedly connected with the slot, the connecting key includes conductor wire, the connecting key bag Including first end and the second end, the first end of the connecting key and the second end expose the conductor wire, and the first of the connecting key End is in the slot, and the first end of the connecting key protrudes from or be flush to the 4th surface of the carrier, the company The second end for connecing key is flush to the functional areas surface of the chip；Plastic packaging layer, the modeling are formed on the 3rd surface of the carrier Sealing surrounds the chip and connecting key, the surface of the plastic packaging layer expose the second end and the function of chip of the connecting key Area surface；Wiring layer again, second end and chip of the wiring layer again with the connecting key are formed in the plastic packaging layer surface Functional areas electrical connection；The first soldered ball is formed in the layer surface that connects up again.
Optionally, in addition to：Before being fixedly connected with key in the slot, first is covered on the 4th surface of the carrier Tack coat, first tack coat close one end of the slot；Fixed in the slot after the connecting key, the company The first end for connecing key is located at first tie layer surface；After plastic packaging layer is formed, first tack coat is removed.
Optionally, the connecting key also includes the protective layer positioned at the conductor wire sidewall surfaces, the protective layer exposure Go out the conductor wire at the connecting key first end and the second end.
Optionally, the forming step of the connecting key includes：Initial conduction line is provided, the initial conduction line has the 3rd End and the 4th end；Initial protective layers are formed in the sidewall surfaces of the initial conduction line, form initial connecting key, the initial guarantor Sheath exposes the 3rd end and the 4th end of the initial conduction line；Cut along perpendicular to the direction of the initial conduction line side wall The initial protective layers and initial conduction line, form some sections of conductor wires and the protective layer positioned at conductor wire sidewall surfaces.
Optionally, the formation process of the initial protective layers include chemical vapor deposition method, physical gas-phase deposition, Atom layer deposition process, spraying coating process or Shooting Technique.
Optionally, the material of the protective layer is insulating materials.
Optionally, the insulating materials is organic insulation or inorganic insulating material；The organic insulation includes Polyvinyl chloride；The inorganic insulating material includes the one or more in silica, silicon nitride and silicon oxynitride.
Optionally, the first end size of the connecting key is identical with the second end size；The conduction of the connecting key first end Linear dimension is identical with the conductive linear dimension at the second end.
Optionally, the connecting key first end to the second end distance be 40 microns~400 microns.
Optionally, the material of the conductor wire is copper, tungsten, aluminium, gold or silver.
Optionally, in addition to：After the plastic packaging layer is formed, formed on the conductor wire surface of the connecting key first end Second soldered ball.
Optionally, in addition to：After the plastic packaging layer is formed, the 4th surface of the carrier and the connecting key are entered Row planarization, untill the plastic packaging layer surface is exposed, the plastic packaging layer exposes the 5th end of the connecting key；Institute After stating flatening process, the second soldered ball is formed on the conductor wire surface at the end of connecting key the 5th.
Optionally, the technique planarized to the 4th surface of the carrier and the connecting key is chemically mechanical polishing Technique.
Optionally, in addition to：Packaging body is provided, the packaging body has the 5th surface, the 5th surface of the packaging body Expose conductive structure；The chip is overlapped with the packaging body, and by welding procedure make second soldered ball with The conductive structure is connected with each other.
Optionally, there are one or several slots in the carrier around each chip region.
Optionally, the slot is located at the first end of the opening size more than or equal to the connecting key on the surface of carrier the 3rd Size；The side wall of the slot is perpendicular to the 3rd surface of the carrier.
Optionally, the functional areas surface of the chip exposes pad；The bond pad surface has projection, the projection Top surface protrudes from the second surface of the chip；The plastic packaging layer exposes the top surface of the projection, the projection Top surface be the chip functional areas surface.
Optionally, in addition to：Before the wiring layer again is formed, in the plastic packaging layer surface the first insulating barrier of formation, If with the conductor wire and chip functions area surface for exposing the end of connecting key second respectively in first insulating barrier Dry first through hole；In the first through hole and the surface of insulating layer of part first forms the wiring layer again.
Optionally, in addition to：Before first soldered ball is formed, the second insulation is formed in the layer surface that connects up again Layer, second insulating barrier is interior to have the second through hole for exposing partly again wiring layer；Described in being formed in second through hole First soldered ball.
Compared with prior art, technical scheme has advantages below：
There is the slot around chip region, and the slot runs through in the forming method of the present invention, in the carrier The carrier.The slot is used to be fixedly connected with key so that the connecting key is located at chip circumference, and the chip is fixed on load 3rd surface of body chip region.Because the first end of the connecting key is located in the slot, thus the connecting key with it is described Contact between carrier is stable, and in subsequent technique, the connecting key is not susceptible to displacement, so as to ensure that the connecting key with Relative position between chip is accurate, is advantageous to avoid the position between the functional areas of wiring layer and connecting key or chip again Shift, and then ensure that the electrical connection between the wiring layer again being subsequently formed and the connecting key and chip functions area is steady It is fixed.The connecting key includes conductor wire, and the first end of the connecting key and the second end expose conductor wire；Due to by described in After the first end of connecting key is fixed in slot, the second end of the connecting key can be flush to the functional surfaces of the chip, Therefore, after the carrier surface forms and exposes the plastic packaging floor in chip functions area, the second end of the connecting key also can It is flush to the plastic packaging layer surface so that the conductor wire can be through in the slot of carrier from the plastic packaging layer surface, with This realizes electrical connection of the chip first surface to second surface.The 4th surface for being additionally, since the carrier exposes the company The first end of key is connect, then subsequently directly can carry out back segment in the first end surfaces of the surface of carrier the 4th and the connecting key Technique, such as soldered ball is formed, thus, it is possible to simplify processing step.Because the connecting key is fixed in the slot of carrier, avoid It the step of subsequently processing plastic packaging layer, can simplify the formation process of encapsulating structure.To sum up, the encapsulating structure Forming method processing step is simplified, process costs reduce, technology difficulty reduces, and the size of the encapsulating structure formed is more Accurately, be advantageous to reduce the size of encapsulating structure.
Further, before being fixedly connected with key in the slot, the first tack coat is covered on the 4th surface of the carrier, First tack coat closes one end of the slot.After key is fixedly connected with the slot, the of the connecting key One end can be located at first tie layer surface, and first tack coat can be used in avoiding the connecting key perpendicular to load It is subjected to displacement on the direction on the surface of body the 3rd, ensures that the position of the connecting key consolidates during plastic packaging layer is formed with this.
Further, the connecting key also includes the protective layer positioned at the conductor wire sidewall surfaces.The protective layer is not only The conductor wire can be protected when connecting key is inserted in slot, additionally it is possible to increase the cross sectional dimensions of connecting key；By institute When stating in connecting key insertion slot, the connecting key is easier to be aligned, and advantageously ensures that position of the connecting key relative to chip Put accurate.
Further, the first end of the connecting key is identical with the size at the second end, and the side wall of the size perpendicular to The 3rd surface of carrier ground, when the connecting key inserts the slot, be advantageous to make the fixation between the connecting key and carrier It is more stable, it can avoid during plastic packaging layer is formed, the connecting key is subjected to displacement, so as to ensure that connecting key and core Relative position between piece is accurate.
Brief description of the drawings
Fig. 1 is that through-silicon via structure is introduced in encapsulating structure to realize the cross-sectional view of chip chamber conducting；
Fig. 2 is that plastic packaging through-hole structure is introduced in encapsulating structure to realize the cross-sectional view of chip chamber conducting；
Fig. 3 to Figure 17 is the structural representation of the forming process of the encapsulating structure of one embodiment of the invention；
Figure 18 to Figure 19 is the structural representation of the forming process of the encapsulating structure of another embodiment of the present invention.
Embodiment
As stated in the Background Art, existing stacked chips encapsulation technology faces technique limitation and cost limitation, for technology Popularization and application cause limitation, moreover, stacked chips encapsulation technology is also faced with that encapsulating structure thickness is further being thinned The problem of, to further improve the integrated level of chip, reduce size.
Stacked chips encapsulation technology can pass through silicon hole (through silicon via, abbreviation TSV) technology or plastic packaging Through hole (through molding via, abbreviation TMV) technology is realized.However, either silicon hole technology or plastic packaging through hole Technology, it is respectively provided with certain defect.
Fig. 1 is refer to, Fig. 1 is that through-silicon via structure is introduced in encapsulating structure to realize that the cross-section structure of chip chamber conducting shows It is intended to, including：Carrier 100；The chip 101 on the surface of carrier 100 is fixed on, the chip 101 includes relative non-functional face 102 And functional surfaces 103, the non-functional face 102 of the chip 101 are in contact with the surface of carrier 100, the functional surfaces of the chip 101 103 surfaces have pad 104；Through the conductive plunger 105 of the chip 101, one end and the weldering of the conductive plunger 105 Disk 104 electrically connects；Plastic packaging layer 106 positioned at the surface of carrier 100, the plastic packaging layer 106 surround the chip 101, and institute State plastic packaging layer 106 and expose the pad 104；Positioned at wiring layer 107 again on the surface of plastic packaging layer 106, the wiring layer again 107 electrically connect with the pad 104；Soldered ball 108 positioned at the surface of wiring layer again 107.
Wherein, the conductive plunger 105 is generally formed before cutting forms independent chip 101；The conductive plunger 105 forming step includes：Substrate is provided, the substrate has functional surfaces, and the substrate includes some chip regions；Using quarter Etching technique forms through hole in the chip region of the substrate from the functional surfaces；Formed in the side wall and lower surface of the through hole Insulating barrier (does not indicate)；Surface of insulating layer in the through hole forms conductive plunger 105；It is relative with functional surfaces from the substrate Surface is polished, until exposing an end position of the conductive plunger 105；After the glossing, described in cutting Substrate, some chip regions are made to form independent chip 101.
However, it is necessary to form through hole in substrate during the conductive plunger 105 is formed, and the through hole Depth is the thickness of chip 101 that is formed, therefore the depth of the through hole is deeper, and the depth-to-width ratio of the through hole is higher, therefore, right Form that the etching technics requirement of the through hole is higher, and the difficulty of the etching technics is larger.Moreover, subsequently need in the through hole Interior filling conductive material is to form conductive plunger 105, and the depth-to-width ratio of the through hole is higher, the filling difficulty of the conductive material It is larger, it is higher for the technological requirement of formation conductive plunger 105.In addition, realize the etching technics and profundity of above-mentioned high-aspect-ratio The wide process costs than through hole filling are higher.To sum up, because the technology difficulty of through-silicon via structure is higher, technique is complex, and Process costs are higher, and being applied to stacked chips encapsulation for silicon hole technology causes limitation.
In order to reduce technology difficulty, a kind of plastic packaging through hole technology is had also been proposed.Fig. 2 is refer to, Fig. 2 is in encapsulating structure Plastic packaging through-hole structure is introduced to realize the cross-sectional view of chip chamber conducting, including：Carrier 110；It is fixed on the table of carrier 110 The chip 111 in face, the chip 111 include relative non-functional face 112 and functional surfaces 113, the chip 111 it is non-functional Face 112 is in contact with the surface of carrier 110, and the surface of functional surfaces 113 of the chip 111 has pad 114；Positioned at the carrier The plastic packaging layer 115 on 110 surfaces, the plastic packaging layer 115 surrounds the chip 111, and the plastic packaging layer 115 exposes the pad 114；Through the conductive plunger 116 of the plastic packaging layer 115；Positioned at wiring layer 117 again on the surface of plastic packaging layer 115, it is described again Wiring layer 117 electrically connects with the pad 114 and conductive plunger 116；Soldered ball 118 positioned at the surface of wiring layer again 117.
Wherein, the forming step of the conductive plunger 116 includes：Formed using etching technics in the plastic packaging layer 115 It is through to the through hole on the surface of carrier 110；Conductive plunger 116 is formed in the through hole.
However, because the thickness of the plastic packaging layer 115 is the thickness of the chip 111, and the through hole runs through the modeling Sealing 115, therefore the depth of the through hole is deeper, the depth-to-width ratio of the through hole is higher；Etching technics to forming the through hole With higher required precision, the difficulty of the etching technics is larger.Secondly as follow-up need to fill in the through hole to lead Electric material is to form conductive plunger 116, and the depth-to-width ratio of the through hole is higher, cause to fill the difficulty of the conductive material compared with Greatly.It is additionally, since the conductive plunger 116 to be formed at around the chip 111, therefore, it is necessary to is accurately set to described conductive slotting 116 positions relative to chip are filled in, it is therefore, higher for positioning accuracy request when forming the through hole.To sum up, though using Plastic packaging through hole technology realizes that stacked chips encapsulate, and is still faced with that complex process, technology difficulty are higher and cost is higher Problem.
In order to solve the above problems, the present invention provides a kind of forming method of encapsulating structure, including：Carrier is provided, it is described Carrier has chip region, and the carrier has relative the 3rd surface and the 4th surface；In the carrier formed one or Several slots, the slot run through the carrier；The 3rd surface fixed chip in the support core section, the chip tool Have relative a first surface and second surface, the second surface of the chip includes functional areas, the first surface of the chip with 3rd surface of carrier interfixes；Key is fixedly connected with the slot, the connecting key includes conductor wire, the connecting key Including first end and the second end, the first end of the connecting key and the second end expose the conductor wire, and the of the connecting key One end is located in the slot, and the first end of the connecting key protrudes from or be flush to the 4th surface of the carrier, described Second end of connecting key is flush to the functional areas surface of the chip；Plastic packaging layer is formed on the 3rd surface of the carrier, it is described Plastic packaging layer surrounds the chip and connecting key, the surface of the plastic packaging layer expose the second end and the work(of chip of the connecting key Can area surface；Wiring layer again, second end and core of the wiring layer again with the connecting key are formed in the plastic packaging layer surface The functional areas electrical connection of piece；The first soldered ball is formed in the layer surface that connects up again.
Wherein, there is the slot around chip region, and the slot runs through the carrier in the carrier.It is described to insert Groove is used to be fixedly connected with key so that the connecting key is located at chip circumference, and the chip is fixed on the 3rd of support core section Surface.Because the first end of the connecting key is located in the slot, therefore the contact between the connecting key and the carrier Stable, in subsequent technique, the connecting key is not susceptible to displacement, relative between the connecting key and chip so as to ensure that Position is accurate, is advantageous to avoid the position between the functional areas of wiring layer and connecting key or chip again from shifting, and then It ensure that the electrical connection between the wiring layer again being subsequently formed and the connecting key and chip functions area is stable.The connecting key Including conductor wire, and the first end of the connecting key and the second end expose conductor wire；Due to by the first of the connecting key After end is fixed in slot, the second end of the connecting key can be flush to the functional surfaces of the chip, therefore, in the load Body surface face is formed after the plastic packaging floor for exposing chip functions area, and the second end of the connecting key can also be flush to the plastic packaging Layer surface so that the conductor wire can be through in the slot of carrier from the plastic packaging layer surface, and chip first is realized with this Surface to second surface electrical connection.The 4th surface for being additionally, since the carrier exposes the first end of the connecting key, then Subsequently last part technology directly can be carried out in the first end surfaces of the surface of carrier the 4th and the connecting key, such as form weldering Ball, thus, it is possible to simplify processing step.Because the connecting key is fixed in the slot of carrier, avoids and subsequently plastic packaging layer is entered It the step of row processing, can simplify the formation process of encapsulating structure.To sum up, the forming method processing step of the encapsulating structure Simplified, process costs reduce, technology difficulty reduces, and the size of the encapsulating structure formed is more accurate, is advantageous to reduce The size of encapsulating structure.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.
Fig. 3 to Figure 17 is the structural representation of the forming process of the encapsulating structure of one embodiment of the invention.
It refer to Fig. 3, there is provided carrier 200, the carrier 200 has chip region 201, and the carrier 200 has relatively The 3rd surface 203 and the 4th surface 204.
The carrier 200 provides workbench for subsequent technique, for the plastic packaging layer for carrying chip He being subsequently formed.
In the present embodiment, the carrier 200 is rigid substrate, and the rigid substrate is glass substrate, semiconductor substrate Or polymeric substrates.The rigid substrate has higher hardness, is not susceptible to deformation, supporting-core piece is enough in subsequent technique With plastic packaging layer.In another embodiment, the carrier 200 can also be PCB substrate or metal substrate.
3rd surface 203 of the carrier 200 is used to fix with chip；The chip 200 of the carrier 200 is used to fix The region of chip.The quantity of chip region 201 in the carrier 200 is more than or equal to 1；When the quantity of the chip region 201 is big When 1, the region between adjacent core section 201 can be used in cutting, and make some chip regions 201 separate.
In the present embodiment, connector is subsequently formed in carrier 200, and the slot is used to be fixedly connected with key, therefore institute Stating carrier 200 needs have sufficiently large hardness, to ensure that the connecting key described in subsequent technique will not be subjected to displacement.
Fig. 4 and Fig. 5 are refer to, Fig. 4 is cross-sectional views of the Fig. 5 along AA ' directions, is formed in the carrier 200 One or several slots 202, the slot 202 run through the carrier 200.
The slot 202 is subsequently used for being fixedly connected key, and the connecting key is used to realizing the first surface of chip to second The electrical connection on surface.
In the present embodiment, one or several slots are formed in the carrier 200 around each chip region 201 202.Moreover, there is some slots 202, and the subsequent fixed chip surface in the surface of carrier 200 around a chip region 201 During with some pads, the position of some slots 202 can be mutually corresponding with some pads.In the present embodiment, in a core The surrounding of section 201 forms 4 slots 202.
The forming step of the slot 202 includes：Mask layer, the mask layer exposure are formed on the surface of carrier 200 The subregion gone out around chip region 201；Using the mask layer as mask, the carrier 200 is etched, until running through the support plate 200, slot 202 is formed in the carrier 200；After the slot 202 is formed, the mask layer is removed.
In one embodiment, the mask layer is patterned photoresist layer, and the mask layer uses coating process and light Developing process is carved to be formed.In another embodiment, the material of the mask layer is silicon nitride, silicon oxynitride, titanium nitride, tantalum nitride With the one or more in amorphous carbon；The mask layer using patterned photoresist layer as mask etching by being formed.
The technique for etching the carrier 200 is anisotropic dry etch process.In the present embodiment, what is formed inserts The side wall of groove 202 is perpendicular to the 3rd surface 203 of carrier 200.In other embodiments, the side wall of the slot 202 can also The 3rd surface 203 of the ground is favoured, and the slot 202 is located at the opening size on the 3rd surface 203 less than or equal to the 4th The opening size on surface 204.
The 3rd surface 203 that the connecting key subsequently set is located at support plate 200 is additionally, since, the slot 202 is located at the 3rd The opening size on surface 203 is more than or equal to the first end size of the connecting key, so that the first end of the connecting key can Insert the size 202.
In the present embodiment, after the slot 202 is formed, in addition to：On the 4th surface 204 of the carrier 200 The first tack coat 205 is covered, first tack coat 205 closes one end of the slot 202.The slot 202 is through described The thickness of carrier 200, after slot 202 is inserted in follow-up connecting key, connecting key will not be perpendicular to the table of support plate 200 the 3rd It is subjected to displacement on the direction on the surface 204 of face 203 and the 4th, it is necessary to be located at the slot 202 using first tack coat 205 Closure of openings at 4th surface 204, the connecting key is carried with first tack coat 205.First tack coat 205 Material to have sticking material, first tack coat 205 can be adhered to the 4th surface 204 of the support plate 200.
Fig. 6 is refer to, the fixed chip 210 of the 3rd surface 203 in the chip region 201 of carrier 200, the chip 210 With relative first surface 211 and second surface 212, the second surface 212 of the chip 210 includes functional areas, the core The first surface 211 of piece 210 interfixes with the 3rd surface 203 of carrier 200.
The first surface 211 of the chip 210 is fixed on the surface of carrier 200 by the second tack coat (not shown). The material of second tack coat is UV glue or other cohesive materials.
In one embodiment, tack coat is adhered in the first surface 211 of the chip 210, then the tack coat is adhered to In the 3rd surface 203 of carrier 200, to realize the bonding between chip 210 and carrier 200.And the first table of the chip 210 Face 211 does not have functional areas, i.e., the first surface 210 of described chip 210 is not exposed from electric connection structure, by chip 210 first Surface 211 is fixed on after the surface of carrier 200, can expose the functional areas of the second surface 212 of chip 210.
In another embodiment, additionally it is possible to need the correspondence position of fixed chip 210 to be formed on the surface of the carrier 200 Second tack coat, then the first surface 211 of the chip 210 is adhered to second tie layer surface, fix chip 210 In the surface of carrier 200.
The chip 210 can be sensor chip, logic circuit chip, storage chip etc..The table of chip 210 second Can have transistor, passive device (such as resistance, electric capacity and inductance etc.), memory device, sensing in the functional areas in face 212 One or more of device, electric interconnection structure.
The forming step of the chip 210 includes：Substrate is provided, the substrate has some chip regions, the substrate bag Relative first surface and second surface are included, there are functional areas in the chip region of the substrate second surface；The substrate is entered Row cutting, is separated from each other some chip regions, forms independent chip 210.
In the present embodiment, the functional areas surface of the chip 210 exposes pad；The bond pad surface has projection 213, the top surface of the projection 213 protrudes from the second surface 212 of the chip 210, the top surface of the projection 213 The functional areas surface of i.e. described chip 210.The material of the projection 213 includes copper, gold or tin, and the projection 213 has default Thickness.The projection 213 can be realized with the circuit in functional areas or device and electrically connected.The projection 213 is used for subsequently setting The connecting key electrical connection put, so as to realize the electrical connection between the functional areas of chip 210 and other chips or external circuit.At this In embodiment, the functional areas surface of the chip 210 is the top surface of the projection 213.In other embodiments, the work( Energy area can also be sensor region, have sensor in the sensor region, and the sensor is used to obtain external environment condition In information.
Fig. 7 is refer to, key 220 is fixedly connected with the slot 202 (as shown in Figure 6), the connecting key 220 includes leading Electric wire 223, the connecting key 220 include the end 222 of first end 221 and second, the first end 221 and second of the connecting key 220 End 222 exposes the conductor wire 223, and the first end 221 of the connecting key 220 is located in the slot 202, and the connection The first end 221 of key 220 protrudes from or is flush to the 4th surface 204 of the carrier 200, the second end of the connecting key 220 222 are flush to the functional areas surface of the chip 210.
Because the slot 202 penetrates the carrier 200, and the 4th surface 204 of the carrier 200 is stained with first and glued Tie layer 205, after the connecting key 220 is inserted into slot 202 from the 3rd surface 203 of the carrier 200, the connecting key 220 are fixed in the slot 202 and are located at the surface of the first tack coat 205；Institute is made by first tack coat 205 State connecting key 220 fixing on the direction on the surface of carrier 200, avoid the connecting key 220 perpendicular to the carrier It is subjected to displacement on the direction on 200 surfaces.
The opening size that the slot 202 is located at the 3rd surface 203 is more than or equal to the first end 221 of connecting key 220 Size, the first end 221 of the connecting key 220 is inserted into the slot 202 and interfixed with the carrier 200.
In one embodiment, the slot 202 is located at the opening size on the 3rd surface 203 more than the connecting key 220 The size of first end 221, and the side wall of the slot 202 is perpendicular to the 3rd surface 203 of carrier 200, by the connecting key 220 After inserting in the slot 202, additionally it is possible in the fill insulant of slot 202, make the connecting key 220 and carrier Combination between 200 is more firm.
In another embodiment, the slot 202 is located at the opening size on the 3rd surface 203 and is equal to the connecting key 220 First end 221 size, the first end 221 of the connecting key 220 can be mutual by the first tack coat 205 and support plate 200 It is fixed.
By forming slot 202 in the carrier 200, and key 220 is fixedly connected with the slot 202, can made Combination between the connecting key 220 and carrier 200 is more firm, and the connecting key can be reduced in subsequent technique 220 displacement, make relative position between the connecting key 220 and chip 210 and distance more accurate with this, after can avoiding Shift, advantageously ensure that follow-up between the continuous wiring layer again and the connecting key 220 or the projection 213 of chip 210 formed Formed wiring layer again can between the connecting key and projection 213 electrical connection properties it is good.
It is additionally, since the slot 202 and runs through the carrier 200, in the slot 202 after insertion connecting key 220, 4th surface 204 of the carrier 200 can expose the first end 221 of the connecting key 220, then subsequently can be directly to institute The first end 221 of connecting key 220 exposed is handled, and thinned step is carried out to the surface 204 of carrier the 4th so as to reduce, Processing step can be simplified with this and save cost.
In the present embodiment, the functional areas surface of the chip 210 is the top surface of the projection 213, and in slot It is fixedly connected in 202 after the first end 221 of key 220, the surface of the second end 222 of connecting key 220 is flush to the chip 210 Functional areas surface, i.e., the surface of the second end 222 of described connecting key 220 are flush to the top surface of the projection 213.
Because the carrier 200 around a chip region 201 is interior formed with one or several slots 202, then in a core The surrounding of piece 210 fixes one or several connecting keys 220；When the quantity of connecting key 220 around a chip 210 is more than 1, institute The quantity for stating connecting key 220 can be consistent with the quantity of projection 213 on the surface of chip 210, and the position of the connecting key 220 and institute The position of projection 213 for stating the surface of chip 210 is corresponding.
The end 222 of first end 221 and second of the connecting key 220 exposes conductor wire 223, by the connecting key 220 First end 221 and after being fixed in slot 202, the 4th surface 204 of the carrier 200 exposes the connecting key 220 The conductor wire 223 of first end 221, and the surface of conductor wire 223 that second end 222 exposes is flush to the projection 213 Top surface.Subsequently after plastic packaging layer surface forms wiring layer again, the wiring layer again can realize that second end 222 is sudden and violent Electrical connection between the conductor wire 223 and projection 213 that expose, is electrically connected so that projection 213 can be realized to the surface of carrier 200 Connect.
Because the connecting key 220 is directly fixed in slot 202, avoids and be subsequently formed plastic packaging layer and then entering Row routing technique or the forming step for carrying out plastic packaging through-hole structure, can simplify processing step, and reduce technology difficulty, from And cost can be reduced.Moreover, the connecting key 220 is directly fixed in slot 202 so that the connecting key 220 relative to The position of chip 210 is more accurate, avoids during plastic packaging through-hole structure is formed, caused error during etching through hole Problem.In addition, the second end 222 of the connecting key 220 is flush to the top surface of the projection 213, the then modeling being subsequently formed The surface of sealing can be flush to the bond pad surface；Compared in routing technique, plastic packaging layer surface needs to be higher than chip surface The problem of, the modeling seal coat thickness that the present embodiment is subsequently formed is relatively thin, is advantageous to the thickness of thinned formed encapsulating structure.
In the present embodiment, the distance at 221 to the second end of first end 222 of connecting key 220 is 40 microns~400 micro- Rice；The distance at 221 to the second end of first end 222 of connecting key 220 is more than the thickness of the chip 210, the chip 210 Thickness is distance of the top surface of projection 213 to the first surface 211 of chip 210.Thus, it is possible to ensure be subsequently formed After plastic packaging layer, the plastic packaging layer surface can flush with the top surface of pad 221, while the plastic packaging layer can expose company Connect the second end 222 of key 220.
The material of the conductor wire 223 is conductive material, and the conductor wire 223 is used to realize chip 210 from first surface 211 to second surface 212 conducting；It is copper, tungsten, aluminium, gold or silver that the conductive material, which includes,.
In the present embodiment, the connecting key 220 also includes the protective layer 224 positioned at the sidewall surfaces of conductor wire 223, The protective layer 224 exposes the conductor wire 223 at the first end 221 of connecting key 220 and the second end 222.
In another embodiment, the connecting key can not also include the protective layer, and only have the conductor wire.
The material of the protective layer 224 is insulating materials.The insulating materials is organic insulation or inorganic insulation material Material；The organic insulation includes polyvinyl chloride or resin；The resin includes epoxy resin, polyimide resin, benzo Cyclobutane resin or polybenzoxazoles resin；The inorganic insulating material includes one in silica, silicon nitride and silicon oxynitride Kind is a variety of.
The protective layer 224 can not only be when connecting key 220 be fixed in the slot 202 of carrier 200, for protecting The surface of the conductor wire 223 can increase the sectional dimension of the connecting key 220 from damage, so as to connect Key 220 is more easy to be aligned when inserting in the slot 202, and the connecting key 220 for making to be fixed on the surface of carrier 200 is relative to chip 210 Position it is more accurate.
In the present embodiment, the size of first end 221 of the connecting key 220 is identical with the size of the second end 222.The connection The size of conductor wire 223 of the first end 221 of key 220 is identical with the size of conductor wire 223 at the second end 222.Wherein, the conductor wire 223 a diameter of 30 microns~150 microns, the thickness of the protective layer 224 is 10 nanometers~10 microns；When the conductor wire 223 Material when being copper, the minimum diameter of the conductor wire 223 is 30 microns；It is described when the material of the conductor wire 223 is aluminium The minimum diameter of conductor wire 223 is 100 microns.
In the present embodiment, the conductor wire 223 is cylinder, i.e., the section of described conductor wire 223 is circular, the company The end 222 of first end 221 and second for connecing key 220 exposes the cylindrical both ends of conductor wire 223 respectively；The connecting key 220 first ends 221 and the size of conductor wire 223 at the second end 222 are the diameter of the cylindrical conductive line 223.
In the present embodiment, the cylindrical conductor wire 223 is from the diameter of 203 first end of connecting key, 221 to the second end 222 It is identical.
In the present embodiment, the sidewall surfaces of conductor wire 223 are also covered with protective layer 224, and the protective layer 224 Thickness is homogeneous, so as to after the Surface coating protective layer 224 of conductor wire 223, the connecting key 220 from first end 221 to The size at the second end 222 is still identical.
In other embodiments, the size at the second end of the connecting key can also be less than the size of the first end.
The forming step of the connecting key is illustrated below with reference to accompanying drawing.
It refer to Fig. 8, there is provided initial conduction line 300, the initial conduction line 300 have the 3rd end 303 and the 4th end 304。
The initial conduction line 300 forms conductor wire 223 (as shown in Figure 7) for cutting.The initial conduction line 300 Material is conductive material；It is copper, tungsten, aluminium, gold or silver that the conductive material, which includes,.
In the present embodiment, the initial conduction line 300 is cylinder, i.e., the section of described initial conduction line 300 is circle Shape；And size of the initial conduction line 300 from the end 304 of the 3rd end 303 to the 4th is identical, i.e., described cylindrical conductor wire 300 diameter from the end 304 of the 3rd end 303 to the 4th is identical.
Fig. 9 is refer to, initial protective layers 301 is formed in the sidewall surfaces of the initial conduction line 300, forms initial connection Key 302, the initial protective layers 301 expose the 3rd end 303 and the 4th end 304 of the initial conduction line 300.
The material of the initial protective layers 301 is insulating materials；The insulating materials is organic insulation or inorganic exhausted Edge material.The formation process of the initial protective layers 301 includes chemical vapor deposition method, physical gas-phase deposition, atom Layer depositing operation, spraying coating process or Shooting Technique.
In one embodiment, when the material of the initial protective layers 301 is organic insulation, the organic insulation Including polyvinyl chloride or resin；The resin includes epoxy resin, polyimide resin, benzocyclobutane olefine resin or polyphenyl and disliked Azoles resin；The formation process of the initial protective layers 301 can be spraying coating process or Shooting Technique.
In another embodiment, the material of the initial protective layers 301 is inorganic insulating material, the inorganic insulating material Including the one or more in silica, silicon nitride and silicon oxynitride；The formation process of the initial protective layers 301 being capable of chemistry Gas-phase deposition, physical gas-phase deposition, atom layer deposition process；And the technique for forming the initial protective layers 301 needs There is good covering power and uniformity, formed initial protective layers 301 is evenly covered on described first The surface of beginning conductor wire 300.
Figure 10 is refer to, it is described initial along being cut perpendicular to the direction of initial conduction line 300 (as shown in Figure 9) side wall Protective layer 301 (as shown in Figure 9) and initial conduction line 300, form some sections of conductor wires 223 and positioned at the side wall of conductor wire 223 The protective layer 224 on surface.
In the present embodiment, the sidewall surfaces of the initial conduction line 300 are around the axis B (as shown in Figure 7) Surface, the axis B are the central shaft by the 3rd end 303 and the 4th end 304 in the initial conduction line 300；Along perpendicular to The direction cutting of the side wall of initial conduction line 300 is along perpendicular to the axis B direction cutting initial protective layers 301 and just Beginning conductor wire 300.
The cutting technique can be laser cutting parameter.After cutting technique, the initial protective layers 301 and just Beginning conductor wire 300 forms some discrete connecting keys 220.
Figure 11 is refer to, forms plastic packaging layer 230 on the 3rd surface 203 of the carrier 200, the plastic packaging layer 230 surrounds The chip 210 and connecting key 220, the surface of the plastic packaging layer 230 expose the second end 222 and the core of the connecting key 220 The functional areas surface of piece 210.
In the present embodiment, after plastic packaging layer 230 is formed, first tack coat 205 (as shown in Figure 7) is removed.By It is cohesive material in the material of first tack coat 205, directly can peels off first tack coat 205；Peeling off institute After stating the first tack coat 205, the surface of first end 221 on the 4th surface 204 and connecting key 220 to the carrier 200 is carried out Cleaning.
In the present embodiment, the surface of the plastic packaging layer 230 and the top table of projection 213 positioned at the second surface 212 of chip 210 Face flushes, i.e., described plastic packaging layer 230 exposes the top surface of the projection 213.Due to the second end of the connecting key 220 222 are flush to the top surface of the projection 213, so as to make the plastic packaging layer 230 expose the of the connecting key 220 Two ends 222.Electrical connection between connecting key 220 and projection 213 subsequently can be realized by forming again wiring layer.
The surface for being additionally, since the plastic packaging layer 230 flushes with the top surface of projection 213, the thickness of the plastic packaging layer 230 , the thinner thickness of the plastic packaging layer 230 identical with the thickness of chip 210 is spent, the thickness gauge of formed encapsulating structure can be made It is very little smaller.
In the present embodiment, the forming step of the plastic packaging layer 230 includes：Covering institute is formed on the surface of carrier 200 State the initial plastic packaging layer of the projection 213 on chip 210 and chip 210；The initial plastic packaging layer is polished, until exposure Untill the top surface for going out the projection 213, the plastic packaging layer 230 is formed.
The plastic packaging layer 230 can be photosensitive dry film, non-photo-sensing dry film or capsulation material film.
In one embodiment, the plastic packaging layer 230 is photosensitive dry film, and the formation process of the initial plastic packaging layer is pasted for vacuum Membrane process.
In another implementation, the material of the plastic packaging layer 230 is capsulation material, the capsulation material include epoxy resin, It is polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, makrolon, poly- to benzene Naphthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, second Alkene-acetate ethylene copolymer, polyvinyl alcohol or other suitable polymeric materials.
The formation process of the initial plastic packaging layer includes Shooting Technique (injection molding), turns modeling technique (transfer molding) or silk-screen printing technique.The Shooting Technique includes：Mould is provided；Filling modeling in the mold Closure material, the capsulation material is set to coat the chip 210 and connecting key 220；Elevated cure, shape are carried out to the capsulation material Into plastic packaging layer 230.
In other embodiments, the material of plastic packaging layer 230 can also be other insulating materials.
Subsequently formed on the surface of plastic packaging layer 230 and electrically connected with the end 222 of connecting key 220 second and projection 213 Wiring layer again.In one embodiment, the wiring layer again can be formed directly into the surface of plastic packaging layer 230.In this implementation In example, the first insulating barrier can be formed on the surface of plastic packaging layer 230 and then is connected up again in the formation of the first surface of insulating layer Layer；Illustrated below with reference to accompanying drawing.
Figure 12 is refer to, the first insulating barrier 231 is formed on the surface of plastic packaging layer 230, is had in first insulating barrier 231 Have some the first of the conductor wire 223 for exposing the end 222 of connecting key 220 second respectively and the functional areas surface of chip 210 Through hole 232.
First insulating barrier 231 is used to protect the surface of plastic packaging layer 230；First in first insulating barrier 231 The wiring layer again that through hole 232 is used to enable to be subsequently formed electrically connects with conductor wire 223 and projection 213.
The forming step of first insulating barrier 231 includes：In the plastic packaging layer 230, connecting key 220 and the table of projection 213 Face forms the first dielectric film；First dielectric film is patterned, forms the first insulating barrier 231, and first insulation There is first through hole 232 in layer 231.
In one embodiment, the material of first insulating barrier 231 is polymeric material or inorganic insulating material；It is described poly- Compound material can be insulating resin；The inorganic insulating material can be silica, silicon nitride, one kind in silicon oxynitride or Multiple combinations.
The technique being patterned to first dielectric film includes：Using coating process and exposure imaging technique first Insulating film surface forms patterned photoresist layer；First dielectric film is etched with the photoresist layer.
The technique for etching first dielectric film is anisotropic dry etch process；The anisotropic dry method is carved The etching gas of etching technique include CH4、CHF3、CH3One or more in F, bias power are more than 100 watts, and bias voltage is more than 10 volts.
In another embodiment, the material of the first insulating barrier 231 is photoresist, and the first through hole 232 uses photoetching work Skill is formed.
Figure 13 is refer to, in the first through hole 232 (as shown in figure 12) and the surface shape of the first insulating barrier of part 231 Into wiring layer 233 again, the wiring layer again 233 and the second end 222 of the connecting key 220 and the function of chip 210 Area electrically connects.
The forming step of described wiring layer again 233 includes：In the first through hole 232 and the first insulating barrier 231 Surface forms conducting film, the full first through hole 232 of conducting film filling；Planarize the conducting film；In flatening process Afterwards, patterned layer, the patterned layer covering part conducting film are formed on the conducting film surface；Using the patterned layer as Mask, the conducting film is etched, untill the surface of the first insulating barrier 231 is exposed；After the conducting film is etched, remove The patterned layer.
The material of the conducting film includes the one or more in copper, tungsten, aluminium, titanium, tantalum, titanium nitride, tantalum nitride, silver；Carve The technique for losing the conducting film is anisotropic dry etch process or wet processing；The patterned layer can be figure The photoresist layer of change, additionally it is possible to be patterned hard mask, the material of the hard mask is silica, silicon nitride, silicon oxynitride In one kind or it is a variety of；The flatening process can be CMP process.
The wiring layer again 233 can be single layer structure or sandwich construction, the cloth again of the single layer structure or sandwich construction Line layer 233 is used to realize specific circuit function.In the present embodiment, the wiring layer again 233 is single layer structure.In other realities Apply in example, the wiring layer again can be sandwich construction, and be electrically isolated between adjacent two layers wiring layer with insulating barrier.
Figure 14 is refer to, in the second insulating barrier 234 of the surface of wiring layer again 233 formation, second insulating barrier 234 With the second through hole 235 for exposing partly again wiring layer 233.
Second insulating barrier 234 is solder mask, and second insulating barrier 234 is used for described in protective layer in wiring layer 233, And the second through hole 235 in second insulating barrier 234 is used for the position for the first soldered ball that definition is subsequently formed.
The forming step of second insulating barrier 234 includes：Formed on the surface of 233 and first insulating barrier of wiring layer 231 again Second dielectric film；Second dielectric film is patterned, forms the second insulating barrier 208, and in second insulating barrier 234 With second through hole 235.
In one embodiment, the material of second insulating barrier 234 is polymeric material or inorganic insulating material；It is described poly- Compound material can be insulating resin；The inorganic insulating material can be silica, silicon nitride, one kind in silicon oxynitride or Multiple combinations.
The technique being patterned to second dielectric film includes：Using coating process and exposure imaging technique second Insulating film surface forms patterned photoresist layer；First dielectric film is etched with the photoresist layer.
The technique for etching second dielectric film is anisotropic dry etch process；The anisotropic dry method is carved The etching gas of etching technique include CH4、CHF3、CH3One or more in F, bias power are more than 100 watts, and bias voltage is more than 10 volts.
In another embodiment, the material of the second insulating barrier 234 is photoresist, and second through hole 235 uses photoetching work Skill is formed.
Figure 15 is refer to, the surface of wiring layer again 233 in second through hole 235 (as shown in figure 14) forms described One soldered ball 236.
The material of first soldered ball 236 includes tin.The forming step of first soldered ball 236 includes：Described second The surface printing tin cream of wiring layer again 233 of the bottom of through hole 235, then high temperature reflux is carried out, under surface tension effects, form first Soldered ball 236.
In another embodiment, additionally it is possible to which first the surface printing of wiring layer 233 helps weldering to the electricity in the bottom of two through hole 235 again Agent and soldered ball particle, then high temperature reflux form the first soldered ball 236.In other embodiments, additionally it is possible in wiring layer 233 again Upper electrotinning post, then high temperature reflux form the first soldered ball 236.
In one embodiment, between the wiring layer again 233 and first soldered ball 236, additionally it is possible to which there is gold under ball Belong to structure (Under Ball Metal, abbreviation UBM)；Metal structure can include single metal layer or multiple-layer overlapped under the ball Metal level；The material of the single metal layer or more metal layers includes the one or more in copper, aluminium, nickel, cobalt, titanium, tantalum Combination.
Figure 16 is refer to, the second soldered ball 237 is formed on the surface of conductor wire 223 of the first end 221 of connecting key 220.
Formed after second soldered ball 237, that is, realize the two-sided plant ball of formed encapsulating structure, the encapsulating structure Both side surface can realize stacked package with other packaging bodies.
In another embodiment, there is tack coat between the carrier and the chip 210 and plastic packaging layer 230, formed Before second soldered ball, additionally it is possible to peel off and remove the carrier；The carrier can be glass substrate, semiconductor substrate, gather Polymer substrates, PCB substrate or metal substrate.After the removal carrier is peeled off, the first end 221 of the connecting key 220 is prominent For the surface of plastic packaging layer 230 and the first surface of chip 210.Before the carrier is peeled off, it can be thinned or not subtract The thin carrier., can be in the side wall table of connecting key 220 for protruding from the surface of plastic packaging layer 230 after the support plate is peeled off Face and the surface of first end 221 of connecting key 220 form the second soldered ball.
The material of second soldered ball 237 includes tin.The forming step of second soldered ball 237 includes：In the connection The surface printing tin cream of conductor wire 223 of the first end 221 of key 220, then carry out high temperature reflux, under surface tension effects, form the Two soldered balls 237.
In another embodiment, additionally it is possible to first helped in the surface printing of conductor wire 223 of the first end 221 of connecting key 220 Solder flux and soldered ball particle, then high temperature reflux form the second soldered ball 237.In other embodiments, additionally it is possible in the connecting key 220 The electroplating surface tin post of conductor wire 223 of first end 221, then high temperature reflux form the second soldered ball 237.
In another embodiment, Figure 17 is refer to, in addition to：Packaging body 400 is provided, the packaging body 400 has the 5th Surface 401, the 5th surface 401 of the packaging body 400 expose conductive structure 402；Make the first surface of the chip 210 211 and the surface of plastic packaging layer 230 and the 5th surface 401 of the packaging body 400 be oppositely arranged, and make described by welding procedure Two soldered balls 237 are connected with each other with the conductive structure 402.
There is chip or semiconductor devices, and the chip or semiconductor devices and the conduction in the packaging body 400 Structure electrically connects.Because the conductive structure 402 is electrically connected by the second soldered ball 237 and connecting key 220 with chip 210, so as to It can realize that the chip in packaging body 400 or semiconductor devices electrically connect with the chip 210, stacked chips encapsulation is formed with this Structure, and that formed is packaging body stacked structure (Package On Package, abbreviation POP).
To sum up, there is the slot around chip region, and the slot is through described in the present embodiment, in the carrier Carrier.The slot is used to be fixedly connected with key so that the connecting key is located at chip circumference, and the chip is fixed on support core 3rd surface of section.Because the first end of the connecting key is located in the slot, therefore the connecting key and the carrier Between contact it is stable, in subsequent technique, the connecting key is not susceptible to displacement, so as to ensure that the connecting key and chip Between relative position it is accurate, be advantageous to avoid the position between the functional areas of wiring layer and connecting key or chip again to occur Skew, and then ensure that the electrical connection between the wiring layer again being subsequently formed and the connecting key and chip functions area is stable. The connecting key includes conductor wire, and the first end of the connecting key and the second end expose conductor wire；Due to by the company Connect key first end be fixed in slot after, the second end of the connecting key can be flush to the functional surfaces of the chip, because This, after the carrier surface forms and exposes the plastic packaging floor in chip functions area, the second end of the connecting key also can be neat Put down in the plastic packaging layer surface so that the conductor wire can be through in the slot of carrier from the plastic packaging layer surface, with this Realize electrical connection of the chip first surface to second surface.The 4th surface for being additionally, since the carrier exposes the connection The first end of key, then subsequently directly it can carry out back segment work in the first end surfaces of the surface of carrier the 4th and the connecting key Skill, such as soldered ball is formed, thus, it is possible to simplify processing step.Because the connecting key is fixed in the slot of carrier, avoid It the step of subsequently handling plastic packaging layer, can simplify the formation process of encapsulating structure.To sum up, the shape of the encapsulating structure Into method processing step is simplified, process costs reduce, technology difficulty reduces, and the size of the encapsulating structure formed is more smart Really, be advantageous to reduce the size of encapsulating structure.
Figure 18 to Figure 19 is the structural representation of the forming process of the encapsulating structure of another embodiment of the present invention.
On the basis of Figure 11, Figure 18 is refer to, after the plastic packaging layer 230 is formed, to the carrier 200 (as schemed Shown in 11) the 4th surface 204 (as shown in figure 11) and the connecting key 220 planarized, until expose the plastic packaging Untill 230 surface of layer, the plastic packaging layer 230 exposes the 5th end 225 of the connecting key.
In the present embodiment, the carrier can be glass substrate, semiconductor substrate, polymeric substrates, PCB substrate or gold Belong to substrate.
The technique that the 4th surface 204 and the connecting key 220 to the carrier 200 are planarized is thrown for chemical machinery Light technique.After flatening process, the carrier 200 is removed, and makes the contraction in length of the connecting key 220, favorably In the thickness of formed encapsulating structure is thinned, the size of encapsulating structure is reduced with this, improves the integrated level of encapsulating structure.
Because the first end 221 of the connecting key 220 is inserted in slot 202, and the hardness of the carrier 200 is higher, because This described carrier 200 is not suitable for being stripped, therefore, it is necessary to is thinned from the 4th surface 204 of the carrier 200, until going Except the carrier 200.
In the present embodiment, put down to described what the 4th surface 204 of carrier 200 and the first end 221 of connecting key 220 were carried out Smooth chemical industry skill is CMP process (CMP)；The CMP process is to being exposed the surface of plastic packaging layer 230 Untill the first surface 211 of chip 210.
Figure 19 is refer to, after the flatening process, the table of conductor wire 223 at the end 225 of connecting key 220 the 5th Face forms the second soldered ball 600.
In the present embodiment, before second soldered ball 600 is formed, in addition to：Formed on the surface of plastic packaging layer 230 Wiring layer 601 again, the wiring layer again 601 are electrically connected with the second end 222 of the connecting key 220 and the functional areas of chip 210 Connect；The first soldered ball 602 is formed on the surface of wiring layer again 601.
Described in formed again before wiring layer 601, in addition to：The first insulating barrier is formed on the surface of plastic packaging layer 230 603, first insulating barrier 603 is interior to have conductor wire 223, the Yi Jixin for exposing the end 222 of connecting key 220 second respectively Some first through hole on the functional areas surface of piece 210；In the first through hole and the surface of the first insulating barrier of part 603 forms institute State wiring layer 601 again.
Before first soldered ball 602 is formed, in addition to：The second insulating barrier is formed on the surface of wiring layer again 601 604, second insulating barrier 604 is interior to have the second through hole for exposing partly again wiring layer 601；The shape in second through hole Into first soldered ball 602.
It is described the structure of wiring layer 601, the first soldered ball 602, the first insulating barrier 603 and the second insulating barrier 604, material and Formation process is identical described in embodiment with before chatting, and will not be described here.
In another embodiment, there is provided packaging body, the packaging body have the 5th surface, the 5th surface of the packaging body Expose conductive structure；The chip 210 is overlapped with the packaging body, and second soldered ball is made by welding procedure 600 are connected with each other with the conductive structure.
To sum up, in the present embodiment, before being fixedly connected with key in the slot, the covering the on the 4th surface of the carrier One tack coat, first tack coat close one end of the slot.After key is fixedly connected with the slot, the company First tie layer surface can be located at by connecing the first end of key, and first tack coat can be used in avoiding the connecting key from existing It is subjected to displacement on the direction on the surface of carrier the 3rd, is ensured with this during plastic packaging layer is formed, the connecting key Position consolidates.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute The scope of restriction is defined.

Claims (19)

  1. A kind of 1. forming method of encapsulating structure, it is characterised in that including：
    Carrier is provided, the carrier has chip region, and the carrier has relative the 3rd surface and the 4th surface；
    One or several slots are formed in the carrier, the slot runs through the carrier；
    The 3rd surface fixed chip in the support core section, the chip have relative first surface and second surface, The second surface of the chip includes functional areas, and the first surface of the chip and the 3rd surface of carrier interfix；
    Key is fixedly connected with the slot, the connecting key includes conductor wire, and the connecting key includes first end and the second end, The first end of the connecting key and the second end expose the conductor wire, and the first end of the connecting key is located in the slot, And the first end of the connecting key protrudes from or be flush to the 4th surface of the carrier, the second end of the connecting key is flush to The functional areas surface of the chip；
    Plastic packaging layer is formed on the 3rd surface of the carrier, the plastic packaging layer surrounds the chip and connecting key, the plastic packaging layer Surface expose the second end of the connecting key and the functional areas surface of chip；
    Wiring layer again, the wiring layer again and the second end of the connecting key and the work(of chip are formed in the plastic packaging layer surface Can area's electrical connection；
    The first soldered ball is formed in the layer surface that connects up again.
  2. 2. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that also include：It is fixed in the slot Before connecting key, the first tack coat is covered on the 4th surface of the carrier, first tack coat closes the one of the slot End；Fixed in the slot after the connecting key, the first end of the connecting key is located at first tie layer surface； Formed after plastic packaging layer, remove first tack coat.
  3. 3. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the connecting key is also included positioned at described The protective layer of conductor wire sidewall surfaces, the protective layer expose the conductor wire at the connecting key first end and the second end.
  4. 4. the forming method of encapsulating structure as claimed in claim 3, it is characterised in that the forming step bag of the connecting key Include：Initial conduction line is provided, the initial conduction line has the 3rd end and the 4th end；In the sidewall surfaces of the initial conduction line Initial protective layers are formed, form initial connecting key, the initial protective layers expose the 3rd end and the of the initial conduction line Four ends；The initial protective layers and initial conduction line are cut along perpendicular to the direction of the initial conduction line side wall, are formed some Section conductor wire and the protective layer positioned at conductor wire sidewall surfaces.
  5. 5. the forming method of encapsulating structure as claimed in claim 4, it is characterised in that the formation process of the initial protective layers Including chemical vapor deposition method, physical gas-phase deposition, atom layer deposition process, spraying coating process or Shooting Technique.
  6. 6. the forming method of encapsulating structure as claimed in claim 3, it is characterised in that the material of the protective layer is insulation material Material.
  7. 7. the forming method of encapsulating structure as claimed in claim 6, it is characterised in that the insulating materials is organic insulation material Material or inorganic insulating material；The organic insulation includes polyvinyl chloride；The inorganic insulating material includes silica, nitridation One or more in silicon and silicon oxynitride.
  8. 8. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the first end size of the connecting key with Second end size is identical；The conductive linear dimension phase that the conductive linear dimension that the connecting key first end exposes exposes with the second end Together.
  9. 9. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the connecting key first end to the second end Distance be 40 microns~400 microns.
  10. 10. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the material of the conductor wire be copper, Tungsten, aluminium, gold or silver.
  11. 11. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that also include：Forming the plastic packaging layer Afterwards, the second soldered ball is formed on the conductor wire surface of the connecting key first end.
  12. 12. the forming method of encapsulating structure as claimed in claim 11, it is characterised in that also include：Forming the plastic packaging After layer, the 4th surface of the carrier and the connecting key are planarized, are up to exposing the plastic packaging layer surface Only, the plastic packaging layer exposes the 5th end of the connecting key；After the flatening process, at the end of connecting key the 5th Conductor wire surface formed the second soldered ball.
  13. 13. the forming method of encapsulating structure as claimed in claim 12, it is characterised in that to the 4th surface of the carrier and The technique that the connecting key is planarized is CMP process.
  14. 14. the forming method of the encapsulating structure as described in claim 11 or 12, it is characterised in that also include：Packaging body is provided, The packaging body has the 5th surface, and the 5th surface of the packaging body exposes conductive structure；Make the chip and the envelope Dress body overlaps, and second soldered ball is connected with each other with the conductive structure by welding procedure.
  15. 15. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the load around each chip region There are one or several slots in vivo.
  16. 16. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the slot is located at the table of carrier the 3rd The opening size in face is more than or equal to the size of the first end of the connecting key；The side wall of the slot is perpendicular to the carrier 3rd surface.
  17. 17. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that the functional areas surface of the chip is sudden and violent Exposed pad；The bond pad surface has projection, and the top surface of the projection protrudes from the second surface of the chip；It is described Plastic packaging layer exposes the top surface of the projection, and the top surface of the projection is the functional areas surface of the chip.
  18. 18. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that also include：Connected up again described in formation Before layer, the first insulating barrier is formed in the plastic packaging layer surface, has in first insulating barrier and exposes the connection respectively The conductor wire at the end of key second and some first through hole on chip functions area surface；In the first through hole and part One surface of insulating layer forms the wiring layer again.
  19. 19. the forming method of encapsulating structure as claimed in claim 1, it is characterised in that also include：Forming first weldering Before ball, the second insulating barrier is formed in the layer surface that connects up again, is had in second insulating barrier and is exposed part and connect up again Second through hole of layer；First soldered ball is formed in second through hole.
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JP6897163B2 (en) * 2017-03-02 2021-06-30 大日本印刷株式会社 Through Silicon Via Substrate and Its Manufacturing Method
US20180374717A1 (en) * 2017-06-23 2018-12-27 Powertech Technology Inc. Semiconductor package and method of forming the same
CN109801883A (en) * 2018-12-29 2019-05-24 华进半导体封装先导技术研发中心有限公司 A kind of fan-out-type stacking encapsulation method and structure
CN111599694B (en) * 2019-12-30 2022-08-26 矽磐微电子(重庆)有限公司 Semiconductor packaging method
CN115425000A (en) * 2022-09-21 2022-12-02 苏州通富超威半导体有限公司 Packaging structure and forming method thereof

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