CN102774804A - 具微机电元件的封装件及其制造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000011241 protective layer Substances 0.000 claims abstract description 52
- 238000004806 packaging method and process Methods 0.000 claims abstract description 42
- 239000004020 conductor Substances 0.000 claims abstract description 36
- 239000000084 colloidal system Substances 0.000 claims abstract description 18
- 229910000679 solder Inorganic materials 0.000 claims description 27
- 238000013459 approach Methods 0.000 claims description 21
- 238000012856 packing Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 239000012811 non-conductive material Substances 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000576 coating method Methods 0.000 abstract 1
- 239000011253 protective coating Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 6
- 239000006059 cover glass Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000005226 mechanical processes and functions Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
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- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2924/146—Mixed devices
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/181—Encapsulation
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Abstract
本发明涉及一种具微机电元件的封装件及其制造方法,其中,该具微机电元件的封装件包括:具有贯穿的开口的保护层、形成于该开口中的导体、形成于该保护层与导体上的电性接触垫、设于该电性接触垫上的微机电芯片、形成于该保护层上且包覆该微机电芯片的封装胶体。本发明通过于保护层上直接设置微机电芯片,而无需使用晶片或线路板等过厚的承载件,所以可降低该封装件的整体厚度,而达到微小化的目的。
Description
技术领域
本发明有关一种半导体封装件,尤指一种具微机电元件的半导体封装件。
背景技术
微机电系统(Micro Electro Mechanical System,MEMS)是一种兼具电子与机械功能的微小装置,在制造上则通过各种微细加工技术来达成,可将微机电元件设置于芯片的表面上,且以保护罩或底胶进行封装保护,而得到一微机电封装结构。请参阅图1A至图1D,现有具微机电元件的封装结构的各式实施例的剖视示意图。
如图1A所示,揭露于第6,809,412号美国专利者,其先于基板10上设置芯片14,且该芯片14上具有微机电元件141,再将该芯片14以导线11电性连接该基板10,最后于该基板10上设置玻璃盖体12,以封盖该芯片14、微机电元件141及导线11。
如图1B所示,揭露于第6,303,986号美国专利者,其先于具有微机电元件141的芯片14上设置玻璃盖体12,以封盖该微机电元件141,再将该芯片14设于承载用的导线架10’上,接着以导线11电性连接该导线架10’与芯片14,最后以封装材15包覆导线架10’、导线11、盖体12与芯片14。
然而,上述现有的封装结构均具有承载件(如图1A的基板10与图1B的导线架10’),导致增加整体结构的厚度,而无法满足微小化的需求。因此,遂发展出一种无承载件的封装结构。
如图1C所示的无承载件的封装结构,在第7,368,808号美国专利中,先于具有电性连接垫140及微机电元件141的芯片14上设置具有导电通孔120的玻璃盖体12,以封盖该微机电元件141,且该导电通孔120两侧具有接触垫122,内侧的接触垫122对应连接该电性连接垫140,而外侧的接触垫122上则形成有焊球16,以使该芯片14通过该焊球16连接至其他电子元件。
如图1D所示的第6,846,725号美国专利的封装结构,先于具有电性连接垫140及微机电元件141的芯片14上设置具有导电通孔120的玻璃盖体12,以封盖该微机电元件141,且该电性连接垫140上具有焊锡凸块142,而该导电通孔120两侧具有接触垫122,令内侧的接触垫122对应连接该焊锡凸块142,使该芯片14通过外侧的该接触垫122连接至其他电子元件。
然而,上述现有的封装结构虽无承载件而可满足微小化的需求,但于设置该盖体12前,需先于该盖体12中制作导电通孔120,不仅玻璃钻孔的成本高,且该导电通孔120两侧的接触垫122容易发生对位不精准或结合不稳固,导致电性连接不良,进而影响该芯片14外接电子元件的品质。
因此,如何避免上述现有技术的种种问题,实为当前所要解决的目标。
发明内容
为克服现有技术的问题,本发明的主要目的在于提供一种具微机电元件的封装件及其制造方法,可降低该封装件的整体厚度,而达到微小化的目的。
该具微机电元件的封装件,包括:保护层,具有相对的第一表面及第二表面、以及多个连通该第一及第二表面的开口;形成于该保护层的开口中的导体;形成于该保护层的第一表面与该导体上且电性连接该导体的电性接触垫;设于该电性接触垫上,且电性连接该电性接触垫的微机电芯片;以及形成于该保护层上方封装胶体,以包覆该微机电芯片,令该导体外露于该保护层的第二表面与该封装胶体。
本发明还提供一种具微机电元件的封装件的制造方法,包括:提供一承载板;形成具有相对的第一表面及第二表面的保护层于该承载板上,其中,该保护层的第二表面结合至该承载板上,且该保护层上形成有连通该第一及第二表面以外露出该承载板的部分表面的多个开口;形成导体于该保护层的开口中;形成电性接触垫于该保护层的第一表面与导体上,且该电性接触垫电性连接该导体;设置微机电芯片于该电性接触垫上,且该微机电芯片电性连接该电性接触垫;形成封装胶体于该保护层的第一表面上方,令该封装胶体包覆该微机电芯片;以及移除该承载板,令该导体外露于该保护层的第二表面。
前述的封装件及其制造方法中,可植接焊球于该导体的外露表面上。
前述的封装件及其制造方法中,可形成阻焊层于该保护层的第一表面上,且外露该电性接触垫。
此外,前述的封装件及其制造方法中,可形成导电凸块于该电性接触垫或该微机电芯片上,令该导电凸块连接该微机电芯片与该电性接触垫。
由上可知,本发明的具微机电元件的封装件及其制造方法,通过移除该承载板,使该封装件中未具有如现有技术中的基板或导线架等过厚的承载件,所以可降低该封装件的整体厚度,而达到微小化的目的。另外,通过该封装胶体取代现有盖体,且通过在该保护层中形成导体,可免除于盖体上进行钻孔的工艺,不仅工艺简单而易于实施,且因工艺步骤减少而降低制作成本。
此外,本发明的制造方法为晶片级封装(wafer-level packaging),所以无需使用例如现有基板或导线架,而可减少许多不必要的步骤,因而大幅缩短生产时程,以降低成本。
附图说明
图1A至图1D为现有具微机电元件的封装结构的各式实施例的剖视示意图;以及
图2A至图2I为本发明具微机电元件的封装件的制造方法的剖面示意图;其中,图2D’为图2D的另一实施例,图2F’为图2E的另一实施方式,图2F”为图2F及图2F’的另一实施例,图2H’为图2H的另一实施例。
主要元件符号说明
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式,熟悉本领域的技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供熟悉本领域的技术人员进行了解与阅读,并非用以限定本发明可实施的限定条件,所以不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上表面”、“下表面”、“上端面”、“下端面”及“一”等用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,也当视为本发明可实施的范畴。
请参阅图2A至图2I,其为本发明具微机电元件的封装件的制造方法的剖面示意图。
如图2A所示,提供一承载板20,接着形成一保护层21于该承载板20上,该保护层21具有上表面(第一表面)21a及下表面(第二表面)21b,且该保护层21的下表面21b结合至该承载板20上。于本实施例中,该承载板20为金属板,而形成该保护层21的材质为非导电材质,如:介电材、半导体材、防焊材及绝缘材。
接着,再利用图案化工艺,经阻层、曝光及显影等步骤,以于该保护层21上蚀刻形成多个开口210以外露出该承载板20的部分表面,而该开口210连通该上表面21a及下表面21b。
如图2B所示,通过电镀或无电解电镀的方式,形成导体22于该保护层21的开口210中,且该导体22具有上端面22a与下端面22b;于本实施例中,形成该导体22的材质为铜材。
如图2C所示,利用图案化工艺,且以电镀或无电解电镀的方式,形成多个电性接触垫23于该保护层21的上表面21a与导体22的上端面22a上,且该电性接触垫23电性连接该导体22。
如他2D所示,形成一阻焊层(solder mask)24于该保护层21的第一表面21a与电性接触垫23上,且于该阻焊层24上形成多个开口240,该些开口240的形式为SMD(solder mask defined),令该电性接触垫23的部分上表面外露于该阻焊层24开口240。
于另一实施例中,如图2D’所示,该些开口240’的形式可为NSMD(non-solder mask defined),令该电性接触垫23的全部上表面与侧表面及其周围的保护层21上表面21a均外露于该阻焊层24开口240’。
如图2E所示,形成导电凸块25于该阻焊层24开口240中的电性接触垫23上;于本实施例中,形成该导电凸块25的材质为金材或焊锡材料。
如图2F所示,设置至少一微机电芯片26于该导电凸块25上,且该微机电芯片26通过该导电凸块25电性连接该电性接触垫23。所述的微机电芯片26可为陀螺仪(gyroscope)、加速度计(Accelerometer)或射频(RF)件。
如图2F’所示,于另一实施实施例中,可将该导电凸块25’先形成于该微机电芯片26上,令该微机电芯片26通过该导电凸块25’接置该电性接触垫23。
如图2F”所示,于上述两实施例实施例中,也可不形成阻焊层(即省略图2D的工艺),而直接将该微机电芯片26通过该导电凸块25,25’接置于该电性接触垫23上。
如图2G所示,形成封装胶体27于该阻焊层24上,令该封装胶体27包覆该微机电芯片26。
如图2H所示,移除该承载板20,令该导体22的下端面22b外露于该保护层21的下表面21b。接着,视需求沿切割线L(如图2G所示)进行切单工艺,以取得单一个封装件2。
如图2H’所示,若经由图2F”的工艺,将制作出不具有阻焊层24的封装件2’。
因此,本发明提供一种具微机电元件的封装件2’,包括:具有上表面21a及下表面21b的保护层21,且该保护层21还具有多个连通该上、下表面21a,21b的开口210;形成于该开口210中的导体22;形成于该保护层21的上表面21a与该导体22上且电性连接该导体22的电性接触垫23;设于该电性接触垫23上且电性连接该电性接触垫23的微机电芯片26;以及形成于该保护层21上方以包覆该微机电芯片26的封装胶体27,令该导体22外露于该保护层21的下表面21b与该封装胶体27。
于另一实施实施例中,该封装件2还包括阻焊层24,形成于该保护层21的上表面21a,且该阻焊层24具有多个开口240’,令该电性接触垫23全部外露于该阻焊层24开口240,以接置该微机电芯片26;或者阻焊层24形成于该保护层21的上表面21a与电性接触垫23上,并外露部分电性接触垫23。其中,该封装胶体27形成于该阻焊层24上。
于上述两种型态的封装件2,2’中,还包括导电凸块25,设于该电性接触垫23与该微机电芯片26之间,以接置该电性接触垫23与该微机电芯片26。
另外,如图2I所示,可依需求植接焊球28于该导体22的下端面22b上。
综上所述,本发明的具微机电元件的封装件2,2’及其制造方法,通过移除该承载板20,以降低该封装件2,2’的整体厚度,而达到微小化的目的。
另外,通过该封装胶体27包覆该微机电芯片26,且于该保护层21中形成导体22,以免除如现有技术中的于覆盖件上进行钻孔的工艺,所以有效降低制作成本。
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉本领域的技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (18)
1.一种具微机电元件的封装件,包括:
保护层,具有相对的第一表面及第二表面、以及多个连通该第一及第二表面的开口;
导体,形成于该保护层的开口中;
电性接触垫,形成于该保护层的第一表面与该导体上,且电性连接该导体;
微机电芯片,设于该电性接触垫上,且电性连接该电性接触垫;以及
封装胶体,形成于该保护层上方,以包覆该微机电芯片,令该导体外露于该保护层的第二表面与该封装胶体。
2.根据权利要求1所述的具微机电元件的封装件,其特征在于,该保护层为非导电材质。
3.根据权利要求1所述的具微机电元件的封装件,其特征在于,该导体为铜材。
4.根据权利要求1所述的具微机电元件的封装件,还包括焊球,植接于该导体的外露表面上。
5.根据权利要求1所述的具微机电元件的封装件,还包括阻焊层,形成于该保护层的第一表面上,且该阻焊层具有多个开口,令该电性接触垫外露于该阻焊层开口,以供接置该微机电芯片。
6.根据权利要求5所述的具微机电元件的封装件,其特征在于,该封装胶体形成于该阻焊层上。
7.根据权利要求1所述的具微机电元件的封装件,还包括导电凸块,设于该电性接触垫与该微机电芯片之间,以连接该电性接触垫与该微机电芯片。
8.根据权利要求7所述的具微机电元件的封装件,其特征在于,该导电凸块为金材或焊锡材料。
9.一种具微机电元件的封装件的制造方法,包括:
提供一承载板;
形成具有相对的第一表面及第二表面的保护层于该承载板上,其中,该保护层的第二表面结合至该承载板上,且该保护层上形成有连通该第一及第二表面以外露出该承载板的部分表面的多个开口;
形成导体于该保护层的开口中;
形成电性接触垫于该保护层的第一表面与导体上,且该电性接触垫电性连接该导体;
设置微机电芯片于该电性接触垫上,且该微机电芯片电性连接该电性接触垫;
形成封装胶体于该保护层的第一表面上方,令该封装胶体包覆该微机电芯片;以及
移除该承载板,令该导体外露于该保护层的第二表面。
10.根据权利要求9所述的具微机电元件的封装件的制造方法,其特征在于,该承载板为金属板。
11.根据权利要求9所述的具微机电元件的封装件的制造方法,其特征在于,该保护层为非导电材质。
12.根据权利要求9所述的具微机电元件的封装件的制造方法,其特征在于,该导体为铜材。
13.根据权利要求9所述的具微机电元件的封装件的制造方法,还包括植接焊球于该导体的外露表面上。
14.根据权利要求9所述的具微机电元件的封装件的制造方法,还包括于设置该微机电芯片之前,先形成阻焊层于该保护层的第一表面上,且于该阻焊层上形成多个开口,令该电性接触垫外露于该阻焊层开口。
15.根据权利要求14所述的具微机电元件的封装件的制造方法,其特征在于,该封装胶体形成于该阻焊层上。
16.根据权利要求9所述的具微机电元件的封装件的制造方法,还包括形成导电凸块于该电性接触垫上,以连接该微机电芯片。
17.根据权利要求9所述的具微机电元件的封装件的制造方法,其特征在于,该微机电芯片上具有导电凸块,以令该微机电芯片通过该导电凸块接置于该电性接触垫上。
18.根据权利要求16或17所述的具微机电元件的封装件的制造方法,其特征在于,该导电凸块为金材或焊锡材料。
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