CN104617053B - 涉及陶瓷基板上射频装置封装的装置和方法 - Google Patents
涉及陶瓷基板上射频装置封装的装置和方法 Download PDFInfo
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- CN104617053B CN104617053B CN201410858176.0A CN201410858176A CN104617053B CN 104617053 B CN104617053 B CN 104617053B CN 201410858176 A CN201410858176 A CN 201410858176A CN 104617053 B CN104617053 B CN 104617053B
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- 239000000758 substrate Substances 0.000 title claims abstract description 137
- 239000000919 ceramic Substances 0.000 title claims abstract description 134
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004806 packaging method and process Methods 0.000 title abstract description 11
- 238000000576 coating method Methods 0.000 claims abstract description 51
- 239000011248 coating agent Substances 0.000 claims abstract description 50
- 230000008569 process Effects 0.000 claims description 16
- 230000007704 transition Effects 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 239000003973 paint Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 description 11
- 230000006870 function Effects 0.000 description 7
- 230000008901 benefit Effects 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000005253 cladding Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
- H05K9/0007—Casings
- H05K9/002—Casings with localised screening
- H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
- H05K9/0024—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields
- H05K9/0026—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields integrally formed from metal sheet
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
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- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
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Abstract
本发明公开了涉及陶瓷基板上射频装置封装的装置和方法。在一些实旋例中,封装电子装置可以包括配置成接收一个或多个元件的陶瓷基板。该陶瓷基板可包括与接地平面电接触的导电层。该封装电子装置还可进一步包括具有集成电路的裸芯,该裸芯安装在陶瓷基板的表面上。该封装电子装置还可包括在裸芯上实施从而提供屏蔽功能的保形导电涂层。该封装电子装置还可包括保形导电涂层和导电层之间的电连接。
Description
相关申请的交叉引用
本申请要求2013年11月5日提交的、申请号为61/900394、名称为“涉及陶瓷基板上射频装置封装的装置和方法”的美国临时申请的优先权,其公开内容以引用方式明确并入于此。
技术领域
本发明公开大体涉及封装射频(RF)模块的屏蔽。
背景技术
射频(RF)装置中例如RF模块的区域会产生电磁(EM)场或者电磁场会对射频装置的该区域产生不期望的影响。这种EM干扰(EMI)会降低采用这类RF模块的无线装置的性能。一些RF模块可设有EM屏蔽以解决这类与EMI相关的性能问题。
发明内容
根据一些应用,本发明公开涉及包括配置成接收一个或多个元件的陶瓷基板的封装电子装置。该陶瓷基板包括与接地平面电接触的导电层。该封装电子装置还包括具有集成电路的裸芯。该裸芯安装在陶瓷基板的表面上。该封装电子装置还包括在裸芯上实施从而提供屏蔽功能的保形导电涂层。该封装电子装置还包括保形导电涂层和导电层之间的电连接。
在一些实施例中,保形导电涂层可大致直接在裸芯上实施。直接位于裸芯上的该保形导电涂层会使封装电子装置成为小口面(low profile)的屏蔽装置。
在一些实施例中,该裸芯可以配置成倒装芯片装置。该封装电子装置可进一步包括在倒装芯片装置和陶瓷基板之间实施的底层填充部(underfill)。该底层填充部可包括配置成在倒装芯片装置的侧壁和陶瓷基板的表面之间提供倾斜过渡(angled transition)的边缘轮廓。该底层填充部的倾斜过渡轮廓配置成利于提高倒装芯片装置和陶瓷基板之间的保形导电涂层的覆盖率。
在一些实施例中,该集成电路可包括射频(RF)开关电路。在一些实施例中,该裸芯可为绝缘衬底上外延硅(SOI)裸芯。
在一些实施例中,该电连接可包括陶瓷基板表面上的部分保形导电涂层以及配置成在陶瓷基板表面上的保形导电涂层和导电层之间提供电连接的多个导电通孔。该导电层可包括在陶瓷基板内实施的一个或多个导电带。该导电层可包括多个导电带,这些导电带被设置为大体形成陶瓷基板边缘处或陶瓷基板边缘附近的周界(perimeter)。该一个或多个导电带中的每个导电带可至少部分地横向(laterally)覆盖相应的导电通孔。
在一些实施例中,该电连接可包括陶瓷基板表面上的部分保形导电涂层,该部分保形导电涂层延伸至陶瓷基板的侧边缘。该导电层可包括沿着相应的陶瓷基板侧边缘的边缘,以使得导电层的该边缘与该保形导电涂层电接触。该导电层可包括沿着相应的陶瓷基板侧边缘的导电带。该导电带可包括在相应的陶瓷基板侧边缘上充分暴露的边缘,以利于导电带和保形导电涂层之间的电接触。该导电层可包括多个导电带,这些导电带被设置为使得陶瓷基板的每个边缘包括与保形导电涂层电接触的、相应的导电带暴露边缘。
在一些实施例中,该保形导电涂层可包括金属涂料层或通过沉积形成的导电层。在一些实施例中,该陶瓷基板可包括低温共烧陶瓷(LTCC)基板。在一些实施例中,该封装电子装置还可包括在陶瓷基板的底面上实施的多个接触焊盘(contact pad)。该接触焊盘可配置成允许将封装电子装置安装在电路板上。在一些实施例中,该封装电子装置还可包括在裸芯上实施的包覆(overmold),以使得可在该包覆的表面上实施保形涂层。该包覆的尺寸可按需设计以使得其侧壁大致和相应的陶瓷基板侧壁对齐(align with)。
在多个应用中,本发明公开涉及一种无线装置,其包括配置成生成射频(RF)信号的收发器和配置成处理该RF信号的RF模块。该RF模块包括配置成接收一个或多个元件的陶瓷基板。该陶瓷基板包括与接地平面电接触的导电层。该RF模块还包括具有集成电路的裸芯,并且该裸芯安装在陶瓷基板的表面上。该RF模块还包括在裸芯上实施从而提供屏蔽功能的保形导电涂层。该RF模块还包括保形导电涂层和导电层之间的电连接。该无线装置还包括与RF模块通信的天线。该天线配置成利于传输处理后的RF信号。
在一些应用中,本发明公开涉及一种制造封装射频(RF)模块的方法。该方法包括形成或提供配置成接收一个或多个元件的陶瓷基板。该陶瓷基板包括与接地平面电接触的导电层。该方法还包括将包括集成电路的裸芯安装在陶瓷基板的表面上。该方法还包括在裸芯上形成与导电层电接触的保形导电涂层从而为该裸芯提供屏蔽功能。
在一些实施例中,该陶瓷基板可包括多个以堆叠设置的陶瓷层,该堆叠包括由网格线限定的单元阵列,沿着该网格线的单切(singulation)处理使单元被分割成多个独立的单元。该方法还可包括在形成保形导电涂层之前单切该单元阵列。可在单切步骤之前将裸芯安装在每个单元上。
根据一些教导,本发明公开涉及一种用于制造多个封装射频(RF)模块的陶瓷基板。该陶瓷基板包括多个以堆叠设置的陶瓷层,该堆叠包括单元阵列。每个单元配置成接收一个或多个元件。该单元阵列由网格线限定,沿着该网格线的单切处理使单元被分割成多个独立的单元。该陶瓷基板还包括在该堆叠内实施的接地平面。该陶瓷基板还包括在该堆叠内实施的、与该接地平面电接触的导电层。该导电层配置成使得在单切处理后、每个独立单元的至少一个边缘包括该导电层的暴露边缘。
在一些实施例中,该导电层可包括沿着相应的网格线实施的导电带,这样,沿着该线的单切处理使得两个相邻单元彼此分开,并且每个单元将该导电带的切割边缘作为暴露边缘。在一些实施例中,该陶瓷基板还可包括绝缘层、无源元件和导体特征中的一个或多个。无源元件可包括电阻元件、电容元件或者电感元件。导体特征可包括导电走线(conductor trace)或者导电通孔(conductor via)。在一些实施例中,陶瓷基板可包括低温共烧陶瓷(LTCC)基板。
为了概括本发明公开,此处描述了本发明的特定方面、优点和新的特征。应理解的是,并非所有的这些有益效果都能由本发明的任一特定实施例获得。因此,可以以获得或优化在此教导的一个或一组有益效果而不必获得在此教导或提出的其它有益效果的方式具体化或实现本发明。
附图说明
图1展示了一种屏蔽封装装置,其包括安装在例如陶瓷基板的基板上的未封装装置。
图2展示了图1所示的封装装置的一个更具体的实例,其中示出了安装在例如低温共烧陶瓷(LTCC)基板的陶瓷基板上的倒装芯片。
图3展示了可在图2所示的陶瓷基板内实施的导电带,该导电带可与多个导电通孔电连接,而这些导电通孔又可与形成在陶瓷基板上的导电层电连接。
图4展示了可作为图1所示的封装装置的一个更具体的实例的构造。
图5展示了如何实施导电层从而沿着例如陶瓷基板的基板的一个或多个边缘形成暴露边缘的实例。
图6展示了在一些实施例中陶瓷基板可配置成通过例如图5所示实例的导电层的暴露边缘来产生电连接性能。
图7展示了陶瓷基板单元阵列可以被单切成多个独立单元的实例。
图8展示了可被实施以制造包括一个或多个此处所述特征的屏蔽RF模块的过程。
图9展示了包括一个或多个此处所述特征的陶瓷基板可被用于具有包覆的屏蔽RF模块。
图10描绘了一种无线装置,其包括具有一个或多个此处所述特征的屏蔽RF模块。
具体实施方式
在此提供的标题(如果有的话)仅用于便利目的,并不影响请求保护的发明的范围或含义。
在此公开了如何将射频(RF)装置(例如倒装裸芯)安装到封装基板(例如陶瓷基板)上并且对其进行屏蔽的多个实例。虽然以倒装裸芯为背景进行了描述,但应理解的是,本发明公开的一个或多个特征可以在其它的应用中实施,包括那些涉及非倒装裸芯的应用。同样应理解的是,本发明公开的一个或多个特征也可以在其它非陶瓷类型的基板上实施。
图1展示了屏蔽封装装置100的实例,其包括安装在陶瓷基板106上的未封装装置104。这里所述的未封装装置可以是例如倒装芯片。如这里所述,安装在陶瓷基板106上的这种倒装芯片104可以在不使用包覆的情况下被屏蔽,从而例如可减小封装装置100的厚度(高度)。例如,可以使封装装置100的总厚度(高度)小于0.65mm的示范规格。
在图1的实例中,封装装置100示出为包括导电材料的保形涂层102,该保形涂层102大致覆盖了未封装装置102并且大致覆盖了陶瓷基板106上表面108的一些或全部暴露部分。这样的保形涂层可以通过电连接配置112与陶瓷基板内的接地节点110电连接。在此会详细描述如何实施这种电连接的各种实例。
如此处所述,未封装装置102可以包括例如具有一个或多个开关电路的裸芯。同样也可以使用包括其他类型的RF电路的裸芯。在一些实施例中,这样的开关裸芯可包括绝缘衬底上外延硅(SOI)裸芯。也允许实施其他类型的处理技术。如此处所述,陶瓷基板106可包括例如低温共烧陶瓷(LTCC)基板、高温共烧陶瓷(HTCC)基板或者其他类型的陶瓷材料和/配置。
图2展示了示例配置100,其可为图1中封装装置的一个更具体的实例。在此实例中,倒装芯片104,例如SOI开关裸芯,示出为安装在例如LTCC基板的陶瓷基板106上。焊球阵列120可利于倒装芯片104在陶瓷基板106上的这种安装。这样的焊球120可以提供机械安装功能,并且可以提供倒装芯片104和形成在陶瓷基板106的安装表面116上的接触焊盘之间的电连接。
如图2所示,可在倒装芯片104和陶瓷基板106之间形成底层填充部122。该底层填充部可设在倒装芯片104的边缘附近,这样可以更容易地形成导电材料的保形涂层102。例如,所示底层填充部122的外围部分提供了倒装芯片104的垂直边缘和陶瓷基板106的水平表面116之间的倾斜过渡。
在一些实施例中,可以应用导电材料通过例如喷涂或各种沉积方法形成该保形涂层102。该导电材料涂层可以为其所覆盖的部分提供屏蔽功能。还能通过在陶瓷基板106边缘处或边缘附近提供横向屏蔽以及在倒装芯片104的下方形成接地平面来大大增强封装装置100的整体屏蔽性能。
在图2所示的实例中,电连接配置112可包括与陶瓷基板106表面116上的导电涂层102电接触的多个导电通孔138。如图3所示,该导电通孔可以分布为形成周界,并且各通孔138可以被放置在合适的位置从而在该周界内外的区域之间提供横向屏蔽。尽管已经以该周界为背景进行了描述,但应理解的是,本发明公开的一个或多个特征同样可以应用到所述横向屏蔽不形成完整周界的配置中。例如,可以提供该导电通孔来实现模块内部的屏蔽功能而无需形成给定区域的完整周界。
在图2所示的实例中,该电连接配置112可进一步包括在陶瓷基板106内实施的一个或多个导电层(例如140、142)以与导电通孔138电接触。该导电层140、142可以与同样位于陶瓷基板106内的接地平面电接触。
图3展示了导电层140的实例。这样的层可以包括沿着由导电通孔138形成的该周界而设置的多个导电带。在所示出的实例中,每个导电带140示出为横向设置以与各自的通孔138相交。对于图2所示的示例性导电层142,每个导电带不必和对应的通孔138完全重叠,只要其能和通孔138形成电接触即可。通孔138和导电层140、142的其它配置也是可能的。
如图2所示,陶瓷基板106可包括多个层和特征130。这些层和特征可以包括例如介质层、无源元件(如电阻、电容和电感)、导体特征(如通孔和走线)以及接地平面。在此背景下,示例性导电层140、142可形成在选定的横向位置和/或选定的层上。
同样如图2所示,封装装置100可包括接触焊盘134、136,该接触焊盘能使封装装置100安装到电路板(例如电话主板)上并且利于封装装置100和电路板之间的电连接。
图4展示了可作为图1所示的封装装置的一个更具体的实例的另一个示例性构造100。在此实例中,例如SOI开关裸芯的倒装芯片104示出为安装在例如LTCC基板的陶瓷基板106上。焊球阵列120可利于倒装芯片104在陶瓷基板106上的这种安装。这样的焊球120可以提供机械安装功能,并且可以提供倒装芯片104和形成在陶瓷基板106的安装表面116上的接触焊盘之间的电连接。
如图4所示,可在倒装芯片104和陶瓷基板106之间形成底层填充部122。该底层填充部可设在倒装芯片104的边缘附近,这样可以更容易地形成导电材料的保形涂层102。例如,所示底层填充部122的外围部分提供了倒装芯片104的垂直边缘和陶瓷基板106的水平表面116之间的倾斜过渡。
在一些实施例中,可以应用导电材料通过例如喷涂或各种沉积方法形成该保形涂层102。该导电材料涂层可以为其所覆盖的部分提供屏蔽功能。还能通过在陶瓷基板106边缘处或边缘附近提供横向屏蔽以及在倒装芯片104的下方形成接地平面来大大增强封装装置100的整体屏蔽性能。
在图4所示的实例中,电连接配置112可包括从陶瓷基板106的上表面116延伸以基本覆盖陶瓷基板106侧边缘的保形导电涂层102。覆盖了陶瓷基板106侧边缘的该保形导电涂层102示出为与陶瓷基板106内的一个或多个导电层电接触并且延伸至陶瓷基板106的其对应边缘。例如,所示出的导电层160、162实施为使其边缘基本上和陶瓷基板106的对应边缘150对齐(align with)。因此,所示出的导电层160、162与保形导电涂层102电接触。这样,保形导电涂层102与接地平面(与导电层160、162电接触)一起对封装装置提供屏蔽功能。
如图4所示,陶瓷基板106可包括多个层和特征130。这些层和特征可以包括例如介质层、无源元件(如电阻、电容和电感)、导体特征(如通孔和走线)以及接地平面。在此背景下,示例性导电层160、162可以形成在选定的横向位置和/或选定的层上。在一些实施例中,导电层160、162可以例如由诸如银的导电材料的图案化印刷形成。
同样如图4所示,封装装置100可包括接触焊盘156,该接触焊盘可使封装装置100安装到电路板(例如电话主板)上并且利于封装装置100和电路板之间的电连接。
图5展示了如何实施例如示例层160(已在图4中描述)的导电层从而沿着陶瓷基板106的边缘150形成暴露边缘。在此实例中,所示出的层160包括沿着每个边缘150的导电带。所述导电带可以沿着限定在阵列中(例如,面板中)的、陶瓷基板106的相邻单元之间的分割线而布置。在将该阵列单切成多个独立单元后,所生成的边缘可以构成独立陶瓷基板106的边缘150。沿着陶瓷基板106的边缘,导电带160的分割部分可以形成暴露的导电边缘从而形成与保形导电涂层102的电接触。如上述参照图4的说明,这样的保形导电涂层可以包括覆盖了陶瓷基板106的一些或全部边缘以及导电带160的相应的一些或全部暴露边缘的部分。
如图5所示,导电带160不必一定形成围绕陶瓷基板106的完整周界。例如,如标记164所示的转角部分可以具有间隙,该间隙的尺寸足够小以能够提供屏蔽功能。在图5中,可配置多个通孔170以提供各种电连接和/或传热功能。
图6展示了在一些实施例中陶瓷基板106可配置成形成具有在此描述的一个或多个特征的电连接112。如所示,这样的陶瓷基板可以包括多个层130和/或在此描述的特征。而且,如此处所述,这样的陶瓷基板可以包括位于陶瓷基板106内并置为至少部分地暴露在边缘150上的一个或多个导电特征160。
在图6所示的实例中,陶瓷基板106描绘成以近似90度进行切割从而限定垂直边缘150。在一些实施例中,单切操作会生成沿该边缘的不垂直表面。例如,图7所示的一些实施例中,可以沿着切割线180对陶瓷基板的各单元(例如106a、106b)的阵列进行处理和单切。这样的单切配置可以通过例如在烧制过程之前基板材料较软时沿着界定(delineation)线180形成V型沟槽182来实现。烧制过程完成后,可以通过例如使各单元沿着该界定线180断开的方式对得到的硬化陶瓷基板进行单切。这种断开操作可以通过该V型沟槽来实现。
在上述经单切的陶瓷基板106a、106b中,导电层160沿V型沟槽182的表面184a、184b暴露的部分可以与其对应的保形导电涂层形成电接触。
图8展示了可被实施以制造封装射频(RF)模块的过程200。在步骤202中,可形成或提供具有导电层和接地平面的陶瓷基板。该导电层和接地平面可电连接。在步骤204中,可将裸芯安装在该陶瓷基板上。在步骤206中,可在该裸芯上形成与导电层电接触从而为该裸芯提供RF屏蔽的保形导电涂层。
在一些实施例中,图8所示的过程200的至少一些步骤中,陶瓷基板可为面板的形式。这样的面板可以包括以堆叠设置的多个陶瓷层,同时该面板可以包括由网格线限定的单元阵列。应理解的是,该网格线不一定实际存在于面板上,而是可以以例如单切指令和或数据的形式实施。沿这类网格线进行的单切可以使单元被分为多个独立的单元。在图4-7中示例的背景下,保形导电涂层可以应用于陶瓷基板的侧壁,这样的涂层步骤可以在单切步骤之后执行。在一些实施例中,可以在单切步骤之前将裸芯安装在每个单元上。
在参照图4所描述的实例中,安装在陶瓷基板106上的裸芯被描绘为未封装的倒装芯片104。如此处所述,这样的陶瓷基板可利于形成在未封装倒装芯片上的保形导电涂层的接地。
图9展示了在一些实施例中具有在此描述的一个或多个特征的陶瓷基板106还可应用于封装应用,所述封装应用是对安装在陶瓷基板106上的一个或多个元件进行封装。例如,屏蔽封装装置100可以包括裸芯210,该裸芯安装在以与如图4所示的示例类似的方式配置的陶瓷基板106上,并且该裸芯配置成提供RF功能。所示出的裸芯210由包覆212封装,并且所示出的保形导电涂层102大致覆盖该包覆212的上表面和侧壁以及陶瓷基板106的侧壁。如参照图4所述,陶瓷基板106内,导电层160、162可配置成在保形导电涂层102和接地平面之间提供电连接。
在一些实施例中,例如无线装置的RF装置可包括具有在此描述的一个或多个特征的装置。在一些实施例中,这样的无线装置可包括例如移动电话、智能电话、带或不带电话功能的手持无线装置、无线手写板等。
图10描绘了包括一个或多个在此描述的有利特征的示例性无线装置400。当一模块包括在此描述的一个或多个特征时,该模块可以应用到多个不同的应用中。例如,如虚线框100所示,屏蔽封装模块可实施为天线开关模块。应理解的是,此模块或多或少地包括图10中描绘的元件。
功率放大器(PA)310可以接收来自收发器410的其相应的RF信号,该收发器410可按照通常方式配置和操作以产生可被放大和传输的RF信号并处理接收到的信号。所示出的收发器410与基带子系统408交互,该基带子系统配置成提供适用于用户的数据和/或声音信号与适用于收发器410的RF信号之间的转换。所示出的收发器410还与电源管理部件406相连接,该电源管理部件配置成管理无线装置的操作电源。这种电源管理还可以控制基带子系统408的操作。
所示出的基带子系统408与用户界面402相连接以利于提供给用户或者接收自用户的声音和/或数据的各种输入和输出。该基带子系统408也可与存储器404相连接,该存储器404配置成存储数据和/或指令以利于无线装置的操作和/或配置成为用户提供信息存储。
在示例性无线装置400中,所示出的PA310的输出(通过相应的匹配电路306)与天线416匹配并且通过频带选择开关308、其相应的双工器412以及天线开关414被路由到该天线416。在一些实施例中,每个双工器412可使用普通天线(例如416)同时进行发射操作和接收操作。在图10中,如所示,接收到的信号被路由至“Rx”路径(未显示在图中),该“Rx”路径可包括例如低噪声放大器(LNA)。
其它一些无线装置配置也可利用在此描述的一个或多个特征。例如,该无线装置不必是多频带装置。又如,该无线装置可以包括额外的天线,比如分集式天线,以及额外的连接性特征,比如WIFI、蓝牙和GPS。
除非上下文中有明确的要求,否则本发明说明书和权利要求部分所使用的类似“组成”,“构成”等词语都应该理解为“包括”的意思,即与“排除”的意思相反。也就是说,应该理解为“包括,但不限于”的意思。本文中使用的词语“连接”是指两个或更多的元素或直接连接或通过一个或多个中间部件进行连接。此外,“此处”,“上述”,“下述”以及类似词语,在本申请中使用时,应该指本发明的全部内容,而非本发明的任何一个特定的部分。在允许的情况下,上述说明书中使用了单数或复数的词语应理解为分别可包括复数或单数。在参照两个或多个项目的列表使用词语“或”时,该词语表示涵盖了所有如下的解释:列表中任何一个项目,列表中的所有项目,列表中各项目的任意组合。
以上对本发明实施例的具体描述并非穷举或将本发明的限定为上述公开的精确形式。虽然在上文中出于例示的目的对本发明的特定实施例和实例进行了描述,但本领域技术人员应意识到,各种等效修改也可能落入本发明的范围。例如,虽然以给定顺序示出了各过程和步骤,但在可替换的实施例中可执行具有不同顺序的各步骤的例程或采用具有不同顺序的各组件的系统,而且可以删除、移动、增加、再分、合并和/修改一些过程或步骤。可以以各种不同方式实施这些过程或步骤中的每一个。同样,虽然所示出的过程或步骤是不时连续执行的,但这些过程和步骤也可以并行执行或在不同的时间执行。
本发明提供的教导可以应用于其它系统而不必是上述系统。上述各种实施例的部件和操作可以被组合以形成新的实施例。
虽然已经描述了本发明的一些实施例,但这些实施例仅以示例形式给出而非旨在限制本发明公开的范围。事实上,此处描述的新方法和系统可以通过各种其他方式实施;进一步地,可以在不违背本发明公开的精神的前提下对此处描述的方法和系统的形式进行各种省略、替换和更改。随附权利要求书及其等同方案旨在覆盖这些可落入本发明公开的范围和精神内的形式或修改。
Claims (9)
1.一种封装电子装置,包括:
陶瓷基板,配置成可接收一个或多个元件,所述陶瓷基板包括上表面、边缘和与接地平面电接触的导电层;
倒装芯片裸芯,具有集成电路,并且安装在所述陶瓷基板的上表面上;
保形导电涂层,直接实施于安装的倒装芯片裸芯上,并且实施在所述陶瓷基板的所述上表面的暴露部分上,延伸到所述陶瓷基板的边缘附近以提供屏蔽功能;
所述保形导电涂层和所述导电层之间的电连接,所述电连接包括从所述陶瓷基板的上表面的暴露部分延伸并延伸穿过所述陶瓷基板的导电通孔,所述导电层包括沿着所述陶瓷基板的周界的多个导电带,所述电连接至少部分地与所述多个导电带中的导电带重叠;以及
在所述倒装芯片裸芯和所述陶瓷基板之间实施的底层填充部,所述底层填充部包括边缘轮廓,所述边缘轮廓配置成提供所述倒装芯片裸芯的侧壁和所述陶瓷基板的上表面之间的倾斜过渡。
2.如权利要求1所述的封装电子装置,其特征在于所述底层填充部的倾斜过渡轮廓配置成利于提高所述倒装芯片裸芯和所述陶瓷基板的上表面之间的所述保形导电涂层的覆盖率。
3.如权利要求1所述的封装电子装置,其特征在于所述集成电路包括射频开关电路。
4.如权利要求3所述的封装电子装置,其特征在于所述倒装芯片裸芯是绝缘衬底上外延硅(SOI)裸芯。
5.如权利要求1所述的封装电子装置,其特征在于所述保形导电涂层包括金属涂料层或通过沉积形成的导电层。
6.如权利要求1所述的封装电子装置,其特征在于所述陶瓷基板包括低温共烧陶瓷(LTCC)基板。
7.如权利要求1所述的封装电子装置,其特征在于还包括在所述陶瓷基板的底面上实施的多个接触焊盘,所述接触焊盘配置成使所述封装电子装置安装在电路板上。
8.如权利要求1所述的封装电子装置,其特征在于所述保形导电涂层直接在所述倒装芯片裸芯上导致所述封装电子装置为低轮廓屏蔽装置。
9.一种射频模块,配置成处理射频信号,所述射频模块包括:
配置成接收一个或多个元件的陶瓷基板,所述陶瓷基板包括上表面、边缘和与接地平面电接触的导电层;
裸芯,具有集成电路,并且安装在所述陶瓷基板的上表面上;
保形导电涂层,直接实施于安装的裸芯上,并且实施在所述陶瓷基板的所述上表面的暴露部分上,延伸到所述陶瓷基板的边缘附近以提供屏蔽功能;
所述保形导电涂层和所述导电层之间的电连接,所述电连接包括从所述陶瓷基板的上表面的暴露部分延伸并延伸穿过所述陶瓷基板的导电通孔,所述导电层包括沿着所述陶瓷基板的周界的多个导电带,所述电连接至少部分地与所述多个导电带中的导电带重叠;以及
在所述裸芯和所述陶瓷基板之间实施的底层填充部,所述底层填充部包括边缘轮廓,所述边缘轮廓配置成提供所述裸芯的侧壁和所述陶瓷基板的上表面之间的倾斜过渡。
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Also Published As
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US20170149466A1 (en) | 2017-05-25 |
JP7214574B2 (ja) | 2023-01-30 |
KR102371332B1 (ko) | 2022-03-04 |
JP7242938B2 (ja) | 2023-03-20 |
US20150126134A1 (en) | 2015-05-07 |
US10771101B2 (en) | 2020-09-08 |
JP2022109908A (ja) | 2022-07-28 |
TWI652789B (zh) | 2019-03-01 |
CN104617053A (zh) | 2015-05-13 |
JP2019176172A (ja) | 2019-10-10 |
HK1206148A1 (zh) | 2015-12-31 |
TW201530731A (zh) | 2015-08-01 |
JP2015091135A (ja) | 2015-05-11 |
KR20150051924A (ko) | 2015-05-13 |
US9564937B2 (en) | 2017-02-07 |
JP6537807B2 (ja) | 2019-07-03 |
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