CN102610595B - 射频功率放大器及其封装方法 - Google Patents

射频功率放大器及其封装方法 Download PDF

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CN102610595B
CN102610595B CN201110025537.XA CN201110025537A CN102610595B CN 102610595 B CN102610595 B CN 102610595B CN 201110025537 A CN201110025537 A CN 201110025537A CN 102610595 B CN102610595 B CN 102610595B
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nude film
power amplifier
radio
frequency power
gaas
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CN102610595A (zh
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马平西
张黎阳
赵骞
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Shenzhen Volans Technology Co Ltd
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Nationz Technologies Inc
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Abstract

本发明涉及一种射频功率放大器、射频功率放大器的封装方法和生成方法，其中射频功率放大器包括：CMOS前级功率放大器,用于对输入功率进行初步放大;GaAs和/或SiGe后级功率放大器,用于对CMOS前级功率放大器的输出功率进行放大。射频功率放大器的封装方法为：射频功率放大器包括基板、CMOS裸片、GaAs裸片和/或SiGe裸片以及PHEMT裸片/SOI裸片/SOS裸片，使所述CMOS裸片、GaAs裸片和/或SiGe裸片、PHEMT裸片/SOI裸片/SOS裸片设置在基板上。本发明提供的射频功率放大器、射频功率放大器的封装方法和生成方法，能够在降低成本的基础上使射频功率放大器具有较高的性能。

Description

射频功率放大器及其封装方法
技术领域
本发明涉及射频电路，尤其涉及一种射频功率放大器及其封装方法。
背景技术
在功率放大器多芯片模组的生产领域中，传统的射频功率放大器的结构如图1所示。图1为现有技术中一种射频功率放大器的结构示意图。如图1所示，现有技术中，射频功率放大器通常包含一颗GaAs(砷化镓)裸片，用于信号通路的放大；一颗PHEMT(Pseudomorphic HEMT，赝配型高电子迁移率晶体管)Switch裸片，用于开关切换收发频段；一颗CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)控制器裸片，用于给信号放大模块以及开关模块提供偏置和控制信号。不同的应用场合下，有去除PHEMT Switch裸片的方案，也有去除CMOS控制器裸片的方案。这类功率放大器可以有很高的性能，但是成本偏高。
另外一种传统的射频功率放大器的结构如图2所示。图2为现有技术中另一种射频功率放大器的结构示意图，图2所示的射频功率放大器采用CMOS工艺实现图1中GaAs裸片的信号通路的放大功能，从而集成了CMOS控制器和信号放大模块；同样，在不同的应用场合下，有去除PHEMTSwitch裸片的方案。该方案的优点是成本低，缺点是技术难度大，性能难以提高。
一般来讲，射频功率放大器需要提供27～35dBm左右的输出功率，采用图2所示的纯CMOS工艺的功率放大器方案，其功耗、尺寸以及可靠性都受到考验，在性能上很难与图1所示的GaAs方案相当。而采用如图1的GaAs方案，尽管近年来GaAs裸片的尺寸在各家公司的努力下不断缩小，然而高昂的GaAs圆片价格使得该类产品依然面临不小的成本压力。
因此，如何能够既降低射频功率放大器的成本又可以使射频功率放大器具有较高的性能是射频功率放大器生产领域的一项重大挑战。
发明内容
本发明所要解决的技术问题是提供一种射频功率放大器及其封装方法，能够在降低成本的基础上使射频功率放大器具有较高的性能。
为解决上述技术问题，本发明提出了一种射频功率放大器，包括：
CMOS前级功率放大器，用于对输入功率进行初步放大；
GaAs和/或SiGe后级功率放大器，用于对所述CMOS前级功率放大器的输出功率进行放大；
该射频功率放大器还包括与所述GaAs和/或SiGe后级功率放大器相连的切换开关，所述切换开关用于作为信号通道开关和/或用于负载阻抗调整，所述切换开关为PHEMT开关、SOI开关、SOS开关中的任意一种或多种的组合。
进一步地，上述射频功率放大器还可具有以下特点，所述射频功率放大器还包括偏置/控制模块，所述偏置/控制模块用于给所述CMOS前级功率放大器、GaAs和/或SiGe后级功率放大器提供偏置和控制信号。
进一步地，上述射频功率放大器还可具有以下特点，所述射频功率放大器还包括偏置/控制模块，所述偏置/控制模块用于给所述CMOS前级功率放大器、GaAs和/或SiGe后级功率放大器、切换开关提供偏置和控制信号。
进一步地，上述射频功率放大器还可具有以下特点，所述射频功率放大器还包括与所述CMOS前级功率放大器相连的CMOS偏置电路。
进一步地，上述射频功率放大器还可具有以下特点，所述射频功率放大器为三级放大器，CMOS前级功率放大器提供第一级和第二级放大器，GaAs和/或SiGe后级功率放大器提供第三级放大器。
进一步地，上述射频功率放大器还可具有以下特点，所述射频功率放大器为三级放大器，CMOS前级功率放大器提供第一级放大器，GaAs和/或SiGe后级功率放大器提供第二级和第三级放大器。
进一步地，上述射频功率放大器还可具有以下特点，所述射频功率放大器为三级放大器，CMOS前级功率放大器提供第一级放大器，SiGe后级功率放大器提供第二级放大器，GaAs后级功率放大器提供第三级放大器。
进一步地，上述射频功率放大器还可具有以下特点，所述射频功率放大器为三级放大器，CMOS前级功率放大器提供第一级放大器，GaAs后级功率放大器提供第二级放大器，SiGe后级功率放大器提供第三级放大器。
进一步地，上述射频功率放大器还可具有以下特点，所述射频功率放大器为m+n级放大器，CMOS前级功率放大器提供前m级放大器，GaAs和/或SiGe后级功率放大器提供后n级放大器，m、n为自然数，且m+n大于3。
为解决上述技术问题，本发明还提出了一种射频功率放大器的封装方法，其中，所述射频功率放大器包括基板、CMOS裸片、GaAs裸片和/或SiGe裸片以及PHEMT裸片/SOI裸片/SOS裸片，其中，所述CMOS裸片为所述射频功率放大器的前级功率放大器，所述GaAs裸片和/或SiGe裸片为所述射频功率放大器的后级功率放大器，所述PHEMT裸片/SOI裸片/SOS裸片为所述射频功率放大器的切换开关，所述PHEMT裸片、SOI裸片、SOS裸片分别为PHEMT开关、SOI开关、SOS开关，所述切换开关与所述后级功率放大器相连关，所述切换开关用于作为信号通道开关和/或用于负载阻抗调整，所述切换开关为PHEMT开关、SOI开关、SOS开关中的任意一种或多种的组合，使所述CMOS裸片、GaAs裸片和/或SiGe裸片、PHEMT裸片/SOI裸片/SOS裸片设置在所述基板上。
进一步地，上述封装方法还可具有以下特点，所述CMOS裸片与所述基板电连接；所述CMOS裸片与所述GaAs裸片和/或SiGe裸片电连接，所述GaAs裸片和/或SiGe裸片与所述PHEMT裸片/SOI裸片/SOS裸片电连接。
进一步地，上述封装方法还可具有以下特点，使所述CMOS裸片设置在所述基板上且与所述基板电连接；使所述GaAs裸片和/或SiGe裸片以及所述PHEMT裸片/SOI裸片/SOS裸片设置于所述CMOS裸片上方，且所述GaAs裸片和/或SiGe裸片与所述CMOS裸片电连接；使所述PHEMT裸片/SOI裸片/SOS裸片与所述基板电连接。
进一步地，上述封装方法还可具有以下特点，所述CMOS裸片设置在基板上，所述GaAs裸片和/或SiGe裸片以及所述PHEMT裸片/SOI裸片/SOS裸片设置在所述CMOS裸片上方，且所述GaAs裸片和/或SiGe裸片以及所述PHEMT裸片/SOI裸片/SOS裸片与所述CMOS裸片连接，所述CMOS裸片与基板电连接。
进一步地，上述封装方法还可具有以下特点，所述GaAs裸片和/或SiGe裸片以及所述PHEMT裸片/SOI裸片/SOS裸片与所述CMOS裸片通过铜柱连接。
进一步地，上述封装方法还可具有以下特点，所述GaAs裸片和/或SiGe裸片以及所述PHEMT裸片/SOI裸片/SOS裸片设置在基板上，所述CMOS裸片设置在所述GaAs裸片和/或SiGe裸片、所述PHEMT裸片/SOI裸片/SOS裸片上方，且所述CMOS裸片与所述GaAs裸片和/或SiGe裸片、所述PHEMT裸片/SOI裸片/SOS裸片相连，所述CMOS裸片与基板相连。
进一步地，上述封装方法还可具有以下特点，所述CMOS裸片通过铜柱与所述GaAs裸片和/或SiGe裸片、所述PHEMT裸片/SOI裸片/SOS裸片相连，所述CMOS裸片通过铜柱与基板相连。
进一步地，上述封装方法还可具有以下特点，电连接通过绑定线的方式实现。
本发明提供的射频功率放大器、射频功率放大器的封装方法和生成方法，能够在降低成本的基础上使射频功率放大器具有较高的性能。
附图说明
图1为现有技术中一种射频功率放大器的结构示意图；
图2为现有技术中另一种射频功率放大器的结构示意图；
图3为本发明实施例中射频功率放大器的结构示意图；
图4为本发明实施例中射频功率放大器的一种封装形式示意图；
图5为本发明实施例中射频功率放大器的另一种封装形式示意图；
图6为本发明实施例中射频功率放大器的又一种封装形式示意图；
图7为本发明实施例中射频功率放大器的再一种封装形式示意图；
其中，图4-图7中各标号的含义如下：
400、基板，401、CMOS裸片，402、GaAs/SiGe裸片，
403、PHEMT/SOI/SOS裸片，500、绑定线，600、铜柱。
具体实施方式
本发明中所用的英文缩写主要有：PHEMT(Pseudomorphic HEMT)赝配型高电子迁移率晶体管；CMOS(Complementary Metal OxideSemiconductor)互补金属氧化物半导体；GaAs砷化镓；SOI(Silicon-On-Insulator)绝缘体硅；SOS蓝宝石硅；SiGe锗硅。
本发明的主要构思是，采用CMOS裸片作为射频功率放大器的前级电路，采用GaAs和/或SiGe裸片作为射频功率放大器的后级电路，这样可以显著降低射频功率放大器整体模块中的GaAs裸片或SiGe裸片的尺寸，从而显著降低成本，同时又能使射频功率放大器的性能达到完全采用GaAs裸片或SiGe裸片的方案的水平。
以下结合附图对本发明的原理和特征进行描述，所举实例只用于解释本发明，并非用于限定本发明的范围。
首先说明一下，本文中，符号″/″表示或者，例如，PHEMT/SOI/SOS意思是PHEMT或者SOI或者SOS。
图3为本发明实施例中射频功率放大器的结构示意图。如图3所示，本实施例中，射频功率放大器包括顺次相连的CMOS裸片11、GaAs或SiGe裸片12、PHEMT/SOI(Silicon-On-Insulator，绝缘体硅)/SOS(蓝宝石硅)裸片13。
其中，CMOS裸片11提供射频功率放大器的前级电路，CMOS裸片11中的核心电路为CMOS前级功率放大器102，CMOS前级功率放大器102用于实现输入匹配以及适当的增益和输出功率(通常小于23dBm)，也即CMOS前级功率放大器102用于对输入功率进行初步放大，采用CMOS工艺实现20dB左右增益，输出功率小于23dBm的功率放大器前级电路，此处，输出功率的定义为前级功率放大器输出端的电流信号的共轭与输出端的电压信号的乘积的模的一半，同时，实现模块输入口的50ohm匹配，该CMOS前级功率放大器可以由两级放大电路构成，第一级用于匹配和增益提高，第二级用于输出功率和增益的进一步提高；CMOS裸片11中还可以集成CMOS Switch(CMOS开关)101，CMOS开关101用于多模多频段应用时的输入信号开关切换，例如GSM(Global System for MobileCommunications，全球移动通讯系统)、EDGE(Enhanced Data Rate forGSM Evolution，增强型数据速率GSM演进技术)和TDSCDMA(TimeDivision-Synchronous Code Division Multiple Access，时分同步的码分多址技术)等信号均可以采用CMOS Switch作为信号开关，采用CMOS工艺实现输入口信号的切换，由于输入最大信号小于5dBm，采用CMOS工艺做开关切换不会遇到线性度的瓶颈，在技术上切实可行；CMOS裸片11中还可以集成CMOS偏置电路103，CMOS偏置电路103用于偏置CMOS前功率放大器以及后级功率放大器，并可以为射频功率放大器的整体模块提供控制接口，比如通道开关的控制信号等，采用CMOS工艺实现整个射频功率放大器模组的偏置和逻辑控制，CMOS偏置电路中可以包含BandGap(带隙)电路、LDO(低压差线性稳压器)电路、逻辑控制电路等。在本发明的其它实施例中，CMOS裸片内的CMOS开关、CMOS偏置电路在某些应用方案中可以缺省，例如用于单模应用时的手机发射前端的射频功率放大器时。在本发明的其它实施例中，CMOS裸片上还可以集成无源器件，如电感、电容、变压器、开关、双工器、滤波器等。
其中，GaAs或SiGe裸片12提供射频功率放大器的后级电路(即后级功率放大器，下同)，用于射频功率放大器后级尤其是最后一级的性能提高。若采用GaAs裸片，则GaAs裸片提供GaAs后级功率放大器，若采用SiGe裸片，则SiGe裸片提供SiGe后级功率放大器，它们都能够提高射频功率放大器的性能。在本发明的其它实施例中，可以采用GaAs裸片和SiGe裸片共同提供射频功率放大器的后级电路。
采用CMOS裸片以及GaAs裸片和/或SiGe裸片构成的射频功率放大器中，有如下可能的组合情形：
(1)CMOS裸片贡献第一级增益，GaAs裸片或SiGe裸片贡献第二级增益，即CMOS裸片提供第一级放大器，GaAs裸片或SiGe裸片提供第二级放大器；
(2)CMOS裸片贡献第一级和第二级增益，GaAs裸片或SiGe裸片贡献第三级增益，即CMOS裸片提供第一级和第二级放大器，GaAs裸片或SiGe裸片提供第三级放大器；
(3)CMOS裸片贡献第一级增益，GaAs裸片或SiGe裸片贡献第二级和第三级增益，即CMOS裸片提供第一级放大器，GaAs裸片或SiGe裸片提供第二级和第三级放大器；
(4)CMOS裸片贡献第一级增益，SiGe裸片贡献第二级增益，GaAs裸片贡献第三级增益，即CMOS裸片提供第一级放大器，SiGe裸片提供第二级放大器，GaAs裸片提供第三级放大器；或者，CMOS裸片贡献第一级增益，GaAs裸片贡献第二级增益，SiGe裸片贡献第三级增益，即CMOS裸片提供第一级放大器，GaAs裸片提供第二级放大器，SiGe裸片提供第三级放大器；
(5)大于3级的增益设计中，CMOS裸片处于前m级，而GaAs裸片和/或SiGe裸片处于后n级，m+n为射频功率放大器的总级数，即CMOS裸片提供前m级放大器，GaAs裸片和/或SiGe裸片提供后n级放大器。
CMOS前级功率放大器102能够实现20dB左右的增益，与常规的射频功率放大器的增益30dB左右相比还有10dB左右的差距，采用GaAs和/或SiGe工艺实现放大器的后级，设计10dB左右的增益，30～35dBm的输出功率，输出阻抗匹配50ohm，输入阻抗与CMOS前级功率放大器的输出端匹配。
其中，连接在GaAs裸片和/或SiGe裸片之后的PHEMT/SOI/SOS裸片13提供PHEMT Switch(PHEMT开关)、SOI Switch(SOI开关)或者SOS Switch(SOS开关)作为信号通道开关和/或用于负载阻抗调整，也就是说，可以用PHEMT开关、SOI开关或SOS开关作为射频功率放大器的切换开关，该切换开关用于切换射频功率放大器的多个发射通道以及外部接收机的多个接收通道。
下面对射频功率放大器的封装方式作一下说明。该射频功率放大器包括CMOS裸片、GaAs或SiGe裸片、PHEMT/SOI/SOS裸片以及基板。
图4为本发明实施例中射频功率放大器的一种封装形式示意图。图4所表示的为绑定线封装形式。如图4所示，CMOS裸片401、GaAs/SiGe裸片402以及PHEMT/SOI/SOS裸片403可以并列排布在基板400上，它们之间通过WireBond(绑定线)500相连，各个裸片可以通过背孔形成接地。图4中，CMOS裸片401与基板电连接；CMOS裸片401与GaAs裸片和/或SiGe裸片402电连接，GaAs裸片和/或SiGe裸片402与PHEMT裸片/SOI裸片/SOS裸片403电连接。电连接可以通过绑定线的方式实现。
图5为本发明实施例中射频功率放大器的另一种封装形式示意图。图5所表示的为叠裸片和绑定线结合的封装形式。如图5所示，本例中，CMOS裸片401正面朝上置于基板400上，GaAs/SiGe裸片402以及PHEMT/SOI/SOS裸片403正面朝上置于CMOS裸片401上方，它们之间也是通过绑定线WireBond500互连。图5中，CMOS裸片401设置在基板400上且与基板400电连接；GaAs裸片和/或SiGe裸片402以及PHEMT裸片/SOI裸片/SOS裸片403设置于CMOS裸片401上方，且GaAs裸片和/或SiGe裸片402与CMOS裸片401电连接；PHEMT裸片/SOI裸片/SOS裸片403与基板电连接。电连接可以通过绑定线的方式实现。
图6为本发明实施例中射频功率放大器的又一种封装形式示意图。图6所表示的为Flipchip(倒扣)和绑定线结合的封装形式。如图6所示，本例中，CMOS裸片401正面朝上置于基板400上，GaAs/SiGe裸片402以及PHEMT/SOI/SOS裸片403正面朝下置于CMOS裸片401上方，GaAs裸片/SiGe裸片402以及PHEMT/SOI/SOS裸片403通过Pillar Bump(铜柱)600与CMOS裸片401互连，CMOS裸片401通过绑定线WireBond500与基板400互连。该种封装形式将CMOS裸片放置在底座(即基板)上，将GaAs/SiGe/PHEMT器件等面积稍小的裸片采用倒扣的方式，通过Pillar Bump等方式连接到CMOS裸片的预留接口上，视GaAs/SiGe/PHEMT裸片为CMOS裸片的若干个补丁。图6中，CMOS裸片401设置在基板400上，GaAs裸片和/或SiGe裸片402以及PHEMT裸片/SOI裸片/SOS裸片403设置在CMOS裸片401上方，且GaAs裸片和/或SiGe裸片402以及PHEMT裸片/SOI裸片/SOS裸片403与CMOS裸片401连接，CMOS裸片401与基板电连接。电连接可以通过绑定线的方式实现。
图7为本发明实施例中射频功率放大器的再一种封装形式示意图。图7所表示的为两次Flipchip倒扣的封装形式。如图7所示，本例中，GaAs裸片/SiGe裸片402以及PHEMT/SOI/SOS裸片403倒扣在CMOS裸片401上，并通过铜柱Pillar Bump600与CMOS裸片401互连，CMOS裸片401倒扣在基板400上，CMOS裸片401通过铜柱Pillar Bump600与基板400互连。图7中，GaAs裸片和/或SiGe裸片402以及PHEMT裸片/SOI裸片/SOS裸片403设置在基板上，CMOS裸片401设置在GaAs裸片和/或SiGe裸片402、PHEMT裸片/SOI裸片/SOS裸片403上方，且CMOS裸片401与GaAs裸片和/或SiGe裸片402、PHEMT裸片/SOI裸片/SOS裸片403相连(通过铜柱)，CMOS裸片401与基板400相连(通过铜柱)。电连接可以通过绑定线的方式实现。
本发明的射频功率放大器，可以作为具有GSM Dual Band/TDSCDMADual Band 4个模式兼容的手机发射前端多芯片模组。
本发明将图1所示传统方案中的GaAs放大器的前级替换为CMOS裸片。从技术层面分析，采用CMOS工艺设计前级放大器电路，实现23dBm以内的输出功率、20dB左右的增益，并实现输入阻抗匹配是切实可行的。再配合后级GaAs工艺或者SiGe工艺或者SiGe+GaAs工艺的高性能裸片，模块性能可以与完全采用GaAs工艺或者SiGe工艺的传统方案相当。而与完全采用GaAs工艺或者SiGe工艺的传统方案相比，可以显著降低模块中GaAs或者SiGe裸片的尺寸，从而能够显著降低射频功率放大器整个模块的成本。
本发明将图2所示的传统方案中的CMOS放大器的后级替换为GaAs/SiGe的放大器作为补丁。从技术层面分析，GaAs/SiGe的放大器补丁仅需要小面积的功率管阵列，以及可能的少许偏置电路、补偿电路等，通过小尺寸的补丁，在略微提升成本以及封装难度的代价下，可以实现较高的可靠性、线性度等关键指标，同时，功耗也会比图2所示的传统方案低。
本发明射频功率放大器在设计和实现上有一定的难度，体现在：
1、前级的CMOS裸片设计，如果采用图4、图5或图6的绑定线封装形式实现设计，由于有限的接地绑定线带来的寄生电感效应，使得芯片接地不够良好，设计性能的提高会遇到一定的挑战；如果采用图7的倒封装技术实现，芯片接地良好，但是需要先进的加工工艺支持，Pillar Bump的生长目前在全球仅有少数的几家公司有实力进行；
2、采用多裸片集成的模组设计，空间上的电磁耦合是最难估计和调试的，需要电磁场仿真建模设计，目前电磁场仿真工具尚难以支持大信号的功率放大器设计需求，因此，采用多裸片集成的模组设计还需要设计者的丰富经验予以支持。
虽然在设计和实现上有一定的难度，但是本发明克服了设计上的困难，并使得本发明的射频功率放大器在现有的工艺水平下能够实现，做到了在不牺牲产品性能的前提下有效地降低了产品成本，保证了产品的核心竞争力。
可见，本发明提供的射频功率放大器，能够在降低成本的基础上使射频功率放大器具有较高的性能。
本发明还提出了一种射频功率放大器的生成方法，即用CMOS工艺生成射频功率放大器的前级CMOS裸片，用GaAs工艺和/或SiGe工艺生成射频功率放大器的后级GaAs裸片和/或SiGe裸片，将GaAs裸片和/或SiGe裸片连接在CMOS裸片之后且与该CMOS裸片置于同一基板上，得到射频功率放大器。进一步地，还可以用PHEMT工艺生成PHEMT裸片，或者用SOI工艺生成SOI裸片，或者用SOS工艺生成SOS裸片，将PHEMT裸片、SOI裸片或SOS裸片连接在GaAs裸片和/或SiGe裸片之后，且与CMOS裸片、GaAs裸片和/或SiGe裸片置于同一基板上。
使用本发明的生成方法制造的射频功率放大器，能够在降低成本的基础上使射频功率放大器具有较高的性能。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (17)

1.一种射频功率放大器，其特征在于，包括：
CMOS前级功率放大器，用于对输入功率进行初步放大；
GaAs和/或SiGe后级功率放大器，用于对所述CMOS前级功率放大器的输出功率进行放大；
该射频功率放大器还包括与所述GaAs和/或SiGe后级功率放大器相连的切换开关，所述切换开关用于作为信号通道开关和/或用于负载阻抗调整，所述切换开关为PHEMT开关、SOI开关、SOS开关中的任意一种或多种的组合。
2.根据权利要求1所述的射频功率放大器，其特征在于：
所述射频功率放大器还包括偏置/控制模块，所述偏置/控制模块用于给所述CMOS前级功率放大器、GaAs和/或SiGe后级功率放大器提供偏置和控制信号。
3.根据权利要求1所述的射频功率放大器，其特征在于：
所述射频功率放大器还包括偏置/控制模块，所述偏置/控制模块用于给所述CMOS前级功率放大器、GaAs和/或SiGe后级功率放大器、切换开关提供偏置和控制信号。
4.根据权利要求1所述的射频功率放大器，其特征在于：
所述射频功率放大器还包括与所述CMOS前级功率放大器相连的CMOS偏置电路。
5.根据权利要求1所述的射频功率放大器，其特征在于：
所述射频功率放大器为三级放大器，CMOS前级功率放大器提供第一级和第二级放大器，GaAs和/或SiGe后级功率放大器提供第三级放大器。
6.根据权利要求1所述的射频功率放大器，其特征在于：
所述射频功率放大器为三级放大器，CMOS前级功率放大器提供第一级放大器，GaAs和/或SiGe后级功率放大器提供第二级和第三级放大器。
7.根据权利要求1所述的射频功率放大器，其特征在于：
所述射频功率放大器为三级放大器，CMOS前级功率放大器提供第一级放大器，SiGe后级功率放大器提供第二级放大器，GaAs后级功率放大器提供第三级放大器。
8.根据权利要求1所述的射频功率放大器，其特征在于：
所述射频功率放大器为三级放大器，CMOS前级功率放大器提供第一级放大器，GaAs后级功率放大器提供第二级放大器，SiGe后级功率放大器提供第三级放大器。
9.根据权利要求1所述的射频功率放大器，其特征在于：
所述射频功率放大器为m+n级放大器，CMOS前级功率放大器提供前m级放大器，GaAs和/或SiGe后级功率放大器提供后n级放大器，m、n为自然数，且m+n大于3。
10.一种射频功率放大器的封装方法，其中，所述射频功率放大器包括基板、CMOS裸片、GaAs裸片和/或SiGe裸片以及PHEMT裸片/SOI裸片/SOS裸片，其中，所述CMOS裸片为所述射频功率放大器的前级功率放大器，所述GaAs裸片和/或SiGe裸片为所述射频功率放大器的后级功率放大器，所述PHEMT裸片/SOI裸片/SOS裸片为所述射频功率放大器的切换开关，所述PHEMT裸片、SOI裸片、SOS裸片分别为PHEMT开关、SOI开关、SOS开关，所述切换开关与所述后级功率放大器相连关，所述切换开关用于作为信号通道开关和/或用于负载阻抗调整，所述切换开关为PHEMT开关、SOI开关、SOS开关中的任意一种或多种的组合，其特征在于，使所述CMOS裸片、GaAs裸片和/或SiGe裸片、PHEMT裸片/SOI裸片/SOS裸片设置在所述基板上。
11.根据权利要求10所述的射频功率放大器的封装方法，其特征在于：
所述CMOS裸片与所述基板电连接；所述CMOS裸片与所述GaAs裸片和/或SiGe裸片电连接，所述GaAs裸片和/或SiGe裸片与所述PHEMT裸片/SOI裸片/SOS裸片电连接。
12.根据权利要求10所述的射频功率放大器的封装方法，其特征在于：
使所述CMOS裸片设置在所述基板上且与所述基板电连接；
使所述GaAs裸片和/或SiGe裸片以及所述PHEMT裸片/SOI裸片/SOS裸片设置于所述CMOS裸片上方，且所述GaAs裸片和/或SiGe裸片与所述CMOS裸片电连接；
使所述PHEMT裸片/SOI裸片/SOS裸片与所述基板电连接。
13.根据权利要求10所述的射频功率放大器的封装方法，其特征在于：
所述CMOS裸片设置在基板上，所述GaAs裸片和/或SiGe裸片以及所述PHEMT裸片/SOI裸片/SOS裸片设置在所述CMOS裸片上方，且所述GaAs裸片和/或SiGe裸片以及所述PHEMT裸片/SOI裸片/SOS裸片与所述CMOS裸片连接，所述CMOS裸片与基板电连接。
14.根据权利要求13所述的射频功率放大器的封装方法，其特征在于：
所述GaAs裸片和/或SiGe裸片以及所述PHEMT裸片/SOI裸片/SOS裸片与所述CMOS裸片通过铜柱连接。
15.根据权利要求10所述的射频功率放大器的封装方法，其特征在于：
所述GaAs裸片和/或SiGe裸片以及所述PHEMT裸片/SOI裸片/SOS裸片设置在基板上，所述CMOS裸片设置在所述GaAs裸片和/或SiGe裸片、所述PHEMT裸片/SOI裸片/SOS裸片上方，且所述CMOS裸片与所述GaAs裸片和/或SiGe裸片、所述PHEMT裸片/SOI裸片/SOS裸片相连，所述CMOS裸片与基板相连。
16.根据权利要求15所述的射频功率放大器的封装方法，其特征在于：
所述CMOS裸片通过铜柱与所述GaAs裸片和/或SiGe裸片、所述PHEMT裸片/SOI裸片/SOS裸片相连，所述CMOS裸片通过铜柱与基板相连。
17.根据权利要求10至16任一项所述的射频功率放大器的封装方法，其特征在于：电连接通过绑定线的方式实现。
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