CN202888168U - 电子元件 - Google Patents

电子元件 Download PDF

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Publication number
CN202888168U
CN202888168U CN 201220449975 CN201220449975U CN202888168U CN 202888168 U CN202888168 U CN 202888168U CN 201220449975 CN201220449975 CN 201220449975 CN 201220449975 U CN201220449975 U CN 201220449975U CN 202888168 U CN202888168 U CN 202888168U
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electronic component
chip
integrated circuit
screen
active face
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CN 201220449975
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张钦崇
宋尚霖
郑伟鸣
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Xinxing Electronics Co Ltd
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Xinxing Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/0951—Function
    • H01L2224/09515—Bonding areas having different functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

本实用新型公开一种电子元件，其包括一集成电路芯片及一屏蔽层。集成电路芯片具有一有源面、相对于有源面的一背面及连接有源面及背面的一侧面，而屏蔽层全面且直接地覆盖背面及侧面。将屏蔽层直接配置在集成电路芯片的表面有利于电子装置的薄型化及轻量化。

Description

电子元件
技术领域
本实用新型涉及一种电子元件，且特别是涉及一种具有屏蔽层的电子元件。
背景技术
目前一般电子元件的组装方式通常是将电子元件焊接至电路板上。若遇到电磁干扰（Electro-Magnetic Interference，EMI）的话，通常会加上法拉第笼（Faraday cage），以得到最好的电性品质。法拉第笼的原理是通过一个导电的遮断物（例如金属盖）将电的干扰没有伤害性地反射或传送到接地。然而，包围在电子元件外围的法拉第笼也同时增加了配置电子元件所需的空间及重量，但这不利于电子产品的薄型化及轻量化。
实用新型内容
本实用新型的目的在于提供一种电子元件，具有电磁屏蔽功能。
为达上述目的，本实用新型提出一种电子元件，其包括一集成电路芯片及一屏蔽层。集成电路芯片具有一有源面、对应于有源面的一背面及连接有源面及背面的一侧面，而屏蔽层全面且直接地覆盖背面及侧面。
该集成电路芯片为一半导体集成电路芯片或为一裸芯片。
该屏蔽层为一物理气相沉积层或为一溅镀层或一蒸镀层。
该屏蔽层的材质包括金属，即铜、不锈钢、铝或金。
该集成电路芯片具有多个接垫在该有源面上。
电子元件还包括：多个导电凸块，分别连接在这些接垫上。
该屏蔽层覆盖该有源面，且该屏蔽层不覆盖这些接垫。
该集成电路芯片具有延伸线，且该延伸线从该接垫延伸至该侧面并连接该屏蔽层。
该集成电路芯片具有内导孔，且该内导孔的末端在该背面连接该屏蔽层。
该集成电路芯片具有内连线，且该内连线的末端在该侧面连接该屏蔽层。
本实用新型的优点在于，相比较于现有的法拉第笼占用较大的空间及具有较大的重量，本实用新型将屏蔽层直接配置在集成电路芯片的表面，故有利于电子装置的薄型化及轻量化。
为让本实用新型的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1为本实用新型一实施例的电子元件安装至电路板的剖面图；
图2为本实用新型另一实施例的电子元件安装至电路板的剖面图；
图3为本实用新型另一实施例的电子元件安装至电路板的剖面图；
图4A为本实用新型另一实施例的电子元件安装至电路板的剖面图；
图4B为图4A的X部位的放大图；
图5A为本实用新型另一实施例的电子元件安装至电路板的剖面图；
图5B为图5A的电子元件的局部仰视立体图。
主要元件符号说明
100a、100b、100c、100d、100e：电子元件
110：集成电路芯片
110a：有源面
110b：背面
110c：侧面
112：接垫
114：延伸线
116：内导孔
118：内连线
119a：基底
119b：多重内连线结构
120：屏蔽层
130：导电凸块
200：电路板
具体实施方式
图1为本实用新型一实施例的电子元件安装至电路板的剖面图。请参考图1，本实施例的电子元件100a包括一集成电路芯片110及一屏蔽层120。集成电路芯片110具有一有源面110a、对应于有源面110a的一背面110b及连接有源面110a及背面110b的一侧面110c。屏蔽层120全面且直接地覆盖背面110b及侧面110c，用以提供电磁屏蔽。
值得注意的是，相比较于现有的法拉第笼占用较大的空间及具有较大的重量，屏蔽层120是直接全面地形成在集成电路芯片110的背面110b及侧面110c，因而有利于电子装置的薄型化及轻量化。
在本实施例中，集成电路芯片110可为一半导体集成电路芯片，即在半导体材质的晶片上制作集成电路后切割而成的裸芯片。前述的半导体材质例如为硅。就电性功能而言，集成电路芯片110是需要电磁屏蔽的芯片，例如中央处理单元（CPU）芯片、绘图处理单元（GPU）芯片及微处理器（microprocessor）芯片等。
在本实施例中，屏蔽层120可为一物理气相沉积层（PVD layer）。具体而言，屏蔽层120可为一溅镀层（sputtering layer）或一蒸镀层（evaporationlayer）。屏蔽层120的材质可包括金属，例如铜、不锈钢、铝或金等。
在本实施例中，集成电路芯片110具有多个接垫112在有源面110a上。此外，电子元件100a更可包括多个导电凸块130，其分别连接在这些接垫112上，用以连接电路板200，例如主机板或模块板。
图2为本实用新型另一实施例的电子元件安装至电路板的剖面图。请参考图2，相比较于图1的电子元件100a，本实施例的电子元件100b的集成电路芯片110还具有一延伸线114，其从接垫112延伸至侧面110c。因此，屏蔽层120可利用延伸线114连接至集成电路芯片110的接地端。
图3为本实用新型另一实施例的电子元件安装至电路板的剖面图。请参考图3，相比较于图1的电子元件100，本实施例的电子元件100c的集成电路芯片110还具有一内导孔116，即所谓的硅穿孔（Through Silicon Via，TSV），且内导孔116延伸至背面110b并连接屏蔽层120。换言之，内导孔116的末端在背面110b连接屏蔽层120。因此，屏蔽层120可利用内导孔116连接至集成电路芯片110的接地端。
图4A为本实用新型另一实施例的电子元件安装至电路板的剖面图，而图4B为图4A的X部位的放大图。请参考图4A及图4B，相较于图1的电子元件100，本实施例的电子元件100d的集成电路芯片110具有一或多个内连线118，且这些内连线118延伸至侧面110c并连接屏蔽层120。换言之，这些内连线118的末端在侧面110c连接屏蔽层120。因此，屏蔽层120可利用这些内连线118连接至集成电路芯片110的接地端。具体而言，集成电路芯片110包括一基底119a及一位在基底119a上的多重内连线结构119b，而这些内连线118是多重内连线结构119b的一部分。
图5A为本实用新型另一实施例的电子元件安装至电路板的剖面图，而图5B为图5A的电子元件的局部仰视立体图。请参考图5A及图5B，相比较于图1的电子元件100，本实施例的电子元件100e的屏蔽层120覆盖集成电路芯片110的有源面110a，但不覆盖而暴露出这些接垫112。因此，屏蔽层120可提供更完整的电磁屏蔽。
综上所述，相比较于现有的法拉第笼占用较大的空间及具有较大的重量，本实用新型将屏蔽层直接配置在集成电路芯片的表面，故有利于电子装置的薄型化及轻量化。

Claims (9)

1.一种电子元件，其特征在于，该电子元件包括：
集成电路芯片，具有有源面、相对于该有源面的背面及连接该有源面及该背面的侧面；以及
屏蔽层，全面且直接地覆盖该背面及该侧面。
2.如权利要求1所述的电子元件，其特征在于，该集成电路芯片为一半导体集成电路芯片。
3.如权利要求1所述的电子元件，其特征在于，该集成电路芯片为一裸芯片。
4.如权利要求1所述的电子元件，其特征在于，该集成电路芯片具有多个接垫在该有源面上。
5.如权利要求4所述的电子元件，其特征在于，该电子元件还包括：多个导电凸块，分别连接在这些接垫上。
6.如权利要求4所述的电子元件，其特征在于，该屏蔽层覆盖该有源面，且该屏蔽层不覆盖这些接垫。
7.如权利要求4所述的电子元件，其特征在于，该集成电路芯片具有延伸线，且该延伸线从该接垫延伸至该侧面并连接该屏蔽层。
8.如权利要求1所述的电子元件，其特征在于，该集成电路芯片具有内导孔，且该内导孔的末端在该背面连接该屏蔽层。
9.如权利要求1所述的电子元件，其特征在于，该集成电路芯片具有内连线，且该内连线的末端在该侧面连接该屏蔽层。
CN 201220449975 2012-09-05 2012-09-05 电子元件 Expired - Fee Related CN202888168U (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104617053A (zh) * 2013-11-05 2015-05-13 天工方案公司 涉及陶瓷基板上射频装置封装的装置和方法
CN110534502A (zh) * 2019-07-26 2019-12-03 南通通富微电子有限公司 封装结构

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104617053A (zh) * 2013-11-05 2015-05-13 天工方案公司 涉及陶瓷基板上射频装置封装的装置和方法
US10771101B2 (en) 2013-11-05 2020-09-08 Skyworks Solutions, Inc. Devices and methods related to packaging of radio-frequency devices on ceramic substrates
CN110534502A (zh) * 2019-07-26 2019-12-03 南通通富微电子有限公司 封装结构
CN110534502B (zh) * 2019-07-26 2021-12-10 南通通富微电子有限公司 封装结构

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