US20130252374A1 - Semiconductor packaging method and structure thereof - Google Patents

Semiconductor packaging method and structure thereof Download PDF

Info

Publication number
US20130252374A1
US20130252374A1 US13/893,620 US201313893620A US2013252374A1 US 20130252374 A1 US20130252374 A1 US 20130252374A1 US 201313893620 A US201313893620 A US 201313893620A US 2013252374 A1 US2013252374 A1 US 2013252374A1
Authority
US
United States
Prior art keywords
dissociation
contact areas
conductive contact
copper
semiconductor packaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/893,620
Inventor
Cheng-Hung Shih
Shu-Chen Lin
Cheng-Fan Lin
Yung-Wei Hsieh
Bo-Shiun Jiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chipbond Technology Corp
Original Assignee
Chipbond Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipbond Technology Corp filed Critical Chipbond Technology Corp
Priority to US13/893,620 priority Critical patent/US20130252374A1/en
Publication of US20130252374A1 publication Critical patent/US20130252374A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29393—Base material with a principal constituent of the material being a solid not provided for in groups H01L2224/293 - H01L2224/29391, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29499—Shape or distribution of the fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances.

Description

    FIELD OF THE INVENTION
  • The present invention is generally related to a semiconductor packaging method, which particularly relates to the semiconductor packaging method that prevents copper ions from dissociation.
    • BACKGROUND OF THE INVENTION
  • Modern electronic products gradually lead a direction of light, thin, short, and small. Accordingly, the circuit layout for electronic products destines to develop technique such as “micro space between two electronic connection devices”. However, a short phenomenon is easily occurred in mentioned circuit layout via an insufficient gap between two adjacent electronic connection devices.
    • SUMMARY
  • The primary object of the present invention is to provide a semiconductor packaging method includes providing a substrate having an upper surface and a plurality of pads disposed at the upper surface, and each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the upper surface and the pads of the substrate, wherein the conductible gel with anti-dissociation function includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, the chip comprises an active surface facing toward the upper surface of the substrate and a plurality of copper-containing bumps disposed at the active surface, wherein the conductible gel with anti-dissociation function covers the copper-containing bumps, each of the copper-containing bumps comprises a second coupling surface and a ring surface, said second coupling surface comprises a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, said copper-containing bumps are electrically connected with the pads via the conductive particles located between the first coupling surfaces and the second coupling surfaces, said conductive particles are electrically connected with the first conductive contact areas of the first coupling surfaces and the second conductive contact areas of the second coupling surfaces, wherein the anti-dissociation substances are located between adjacent conductive particles, each of the first coupling surfaces and each of the second coupling surfaces, said anti-dissociation substances are in contact with the second non-conductive contact areas of the second coupling surfaces, and the ring surfaces of the copper-containing bumps are covered with the anti-dissociation substances. As a result of the ring surfaces of the copper-containing bumps being covered by the anti-dissociation substances of the conductible gel with anti-dissociation function, when a dissociation phenomenon via copper ions from the copper-containing bumps is occurred, the anti-dissociation substances may capture those dissociated copper ions to avoid short phenomenon from happening.
    • DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A to 1C are section schematic diagrams illustrating a semiconductor packaging method in accordance with a preferred embodiment of the present invention.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • With reference to FIGS. 1A to 1C, a semiconductor packaging method in accordance with a preferred embodiment of the present invention includes the steps as followed. First, referring to FIG. 1A, providing a substrate 110 having an upper surface 111 and a plurality of pads 112 disposed at the upper surface 111, in this embodiment, the pad 112 can be a pin of the substrate 110 or a bump pad of trace lines. Each of the pads 112 comprises a first coupling surface 113 and a lateral surface 114, wherein the first coupling surface 113 comprises a plurality of first conductive contact areas 113 a and a plurality of first non-conductive contact areas 113 b. Next, referring to FIG. 1B, FIG. 1B indicates forming a conductible gel with anti-dissociation function 120 on the upper surface 111 and the pads 112 of the substrate 110, wherein the conductible gel with anti-dissociation function 120 includes a plurality of conductive particles 121 and a plurality of anti-dissociation substances 122. In this embodiment, the anti-dissociation substance 122 can be an organic solderability preservative, wherein the material of the organic solderability preservative can be chosen from one of benzimidazole or imidazole derivative. Furthermore, the imidazole derivative can be one of Brenzotriazole, Phenylimidazole, Substituted Benzimidazole, Aryl Phonylimidazole or a mixture thereof, and the benzimidazole can be one of Brenzotriazole, Phenylimidazole, Substituted Benzimidazole, Aryl Phonylimidazole or a mixture thereof.
  • Finally, referring to FIG. 1C, mounting a chip 130 on the substrate 110, said chip 130 comprises an active surface 131 facing toward the upper surface 111 of the substrate 110 and a plurality of copper-containing bumps 132 disposed at the active surface 131. In this embodiment, the material of the copper-containing bumps 132 can be chosen from one of copper/nickel or copper/nickel/gold. The conductible gel with anti-dissociation function 120 covers the copper-containing bumps 132, each of the copper-containing bumps 132 comprises a second coupling surface 133 and a ring surface 134, wherein the second coupling surface 133 comprises a plurality of second conductive contact areas 133 a and a plurality of second non-conductive contact areas 133 b. The copper-containing bumps 132 are electrically connected with the pads 112 via the conductive particles 121 located between the first coupling surfaces 113 and the second coupling surfaces 133. The conductive particles 121 are electrically connected with the first conductive contact areas 113 a of the first coupling surfaces 113 and the second conductive contact areas 133 a of the second coupling surfaces 133. The anti-dissociation substances 122 are located between adjacent conductive particles 121, each of the first coupling surfaces 113 and each of the second coupling surfaces 133. The anti-dissociation substances 122 are in contact with the second non-conductive contact areas 133 b of the second coupling surfaces 133, and the ring surfaces 134 of the copper-containing bumps 132 are covered with the anti-dissociation substances 122 therefore forming a semiconductor packaging structure 100. Besides, the anti-dissociation substances 122 are in contact with the first non-conductive contact areas 113 b of the first coupling surfaces 113 as well. As a result of the ring surfaces 134 of the copper-containing bumps 132 being covered by the anti-dissociation substances 122 of the conductible gel with anti-dissociation function 120, when a dissociation phenomenon via copper ions from the copper-containing bumps 132 is occurred, the anti-dissociation substances 122 may capture those dissociated copper ions in time to avoid short phenomenon from happening and to improve manufacturing yield of the semiconductor packaging structure 100.
  • With reference to FIG. 1C again, a semiconductor packaging structure 100 in accordance with a preferred embodiment of this invention includes a substrate 110, a conductible gel with anti-dissociation function 120 and a chip 130. The substrate 110 comprises an upper surface 111 and a plurality of pads 112 disposed at the upper surface 111, wherein each of the pads 112 comprises a first coupling surface 113 and a lateral surface 114. The first coupling surface 113 comprises a plurality of first conductive contact areas 113 a and a plurality of first non-conductive contact areas 113 b. The conductible gel with anti-dissociation function 120 is formed on the upper surface 111 and the pads 112 of the substrate 110, and said conductible gel with anti-dissociation function 120 includes a plurality of conductive particles 121 and a plurality of anti-dissociation substances 122. The chip 130 is mounted on the substrate 110 and comprises an active surface 131 facing toward the upper surface 111 of the substrate 110 and a plurality of copper-containing bumps 132 disposed at the active surface 131. Each of the copper-containing bumps 132 is covered with the conductible gel with anti-dissociation function 120 and comprises a second coupling surface 133 and a ring surface 134, wherein the second coupling surface 133 comprises a plurality of second conductive contact areas 133 a and a plurality of second non-conductive contact areas 133 b. The copper-containing bumps 132 are electrically connected with the pads 112 via the conductive particles 121 located between the first coupling surfaces 113 and the second coupling surfaces 133. Besides, the conductive particles 121 are electrically connected with the first conductive contact areas 113 a of the first coupling surfaces 113 and the second conductive contact areas 133 a of the second coupling surfaces 133, wherein the anti-dissociation substances 122 are located between adjacent conductive particles 121, each of the first coupling surfaces 113 and each of the second coupling surfaces 133. The anti-dissociation substances 122 are in contact with the second non-conductive contact areas 133 b of the second coupling surfaces 133 and the first non-conductive contact areas 113 b of the first coupling surfaces 113. The anti-dissociation substances 122 cover the ring surfaces 134 of the copper-containing bumps 132 and the lateral surfaces 114 of the pads 112.
  • While this invention has been particularly illustrated and described in detail with respect to the preferred embodiments thereof, it will be clearly understood by those skilled in the art that it is not limited to the specific features and describes and various modifications and changes in form and details may be made without departing from the spirit and scope of this invention.

Claims (7)

What is claimed is:
1. A semiconductor packaging method at least comprising:
providing a substrate having an upper surface and a plurality of pads disposed on the upper surface, wherein each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas;
forming a conductible gel with anti-dissociation function on the upper surface and the pads of the substrate, wherein the conductible gel with anti-dissociation function includes a plurality of conductive particles and a plurality of anti-dissociation substances; and
mounting a chip on the substrate, the chip comprises an active surface facing toward the upper surface of the substrate and a plurality of copper-containing bumps disposed at the active surface, wherein the conductible gel with anti-dissociation function covers the copper-containing bumps, each of the copper-containing bumps comprises a second coupling surface and a ring surface, said second coupling surface comprises a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, said copper-containing bumps are electrically connected with the pads via the conductive particles located between the first coupling surfaces and the second coupling surfaces, said conductive particles are electrically connected with the first conductive contact areas of the first coupling surfaces and the second conductive contact areas of the second coupling surfaces, wherein the anti-dissociation substances are located between adjacent conductive particles, each of the first coupling surfaces and each of the second coupling surfaces, said anti-dissociation substances are in contact with the second non-conductive contact areas of the second coupling surfaces, and the ring surfaces of the copper-containing bumps are covered with the anti-dissociation substances.
2. The semiconductor packaging method in accordance with claim 1, wherein the anti-dissociation substances are in contact with the first non-conductive contact areas of the first coupling surfaces.
3. The semiconductor packaging method in accordance with claim 1, wherein each of the pads comprises a lateral surface being covered with the anti-dissociation substances.
4. The semiconductor packaging method in accordance with claim 1, wherein the anti-dissociation substance can be an organic solderability preservative.
5. The semiconductor packaging method in accordance with claim 4, wherein the material of the organic solderability preservative can be chosen from one of benzimidazole or imidazole derivative.
6. The semiconductor packaging method in accordance with claim 5, wherein the imidazole derivative can be one of Brenzotriazole, Phenylimidazole, Substituted Benzimidazole, Aryl Phonylimidazole or a mixture thereof, and the benzimidazole can be one of Brenzotriazole, Phenylimidazole, Substituted Benzimidazole, Aryl Phonylimidazole or a mixture thereof.
7. The semiconductor packaging method in accordance with claim 1, wherein the material of the copper-containing bumps can be chosen from one of copper/nickel or copper/nickel/gold.
US13/893,620 2012-02-16 2013-05-14 Semiconductor packaging method and structure thereof Abandoned US20130252374A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/893,620 US20130252374A1 (en) 2012-02-16 2013-05-14 Semiconductor packaging method and structure thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/398,081 US8497579B1 (en) 2012-02-16 2012-02-16 Semiconductor packaging method and structure thereof
US13/893,620 US20130252374A1 (en) 2012-02-16 2013-05-14 Semiconductor packaging method and structure thereof

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US13/398,081 Division US8497579B1 (en) 2012-02-16 2012-02-16 Semiconductor packaging method and structure thereof

Publications (1)

Publication Number Publication Date
US20130252374A1 true US20130252374A1 (en) 2013-09-26

Family

ID=48808662

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/398,081 Active 2032-02-23 US8497579B1 (en) 2012-02-16 2012-02-16 Semiconductor packaging method and structure thereof
US13/893,620 Abandoned US20130252374A1 (en) 2012-02-16 2013-05-14 Semiconductor packaging method and structure thereof

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US13/398,081 Active 2032-02-23 US8497579B1 (en) 2012-02-16 2012-02-16 Semiconductor packaging method and structure thereof

Country Status (1)

Country Link
US (2) US8497579B1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11039531B1 (en) 2018-02-05 2021-06-15 Flex Ltd. System and method for in-molded electronic unit using stretchable substrates to create deep drawn cavities and features
US10964660B1 (en) * 2018-11-20 2021-03-30 Flex Ltd. Use of adhesive films for 3D pick and place assembly of electronic components
US10896877B1 (en) 2018-12-14 2021-01-19 Flex Ltd. System in package with double side mounted board
US10568215B1 (en) 2019-05-20 2020-02-18 Flex Ltd. PCBA encapsulation by thermoforming

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020067486A1 (en) * 2000-09-25 2002-06-06 S. Forney Leroy Solderability assessment
US6777464B1 (en) * 1997-03-31 2004-08-17 Hitachi Chemical Company, Ltd. Circuit connecting material, and structure and method of connecting circuit terminal
US20060033213A1 (en) * 2004-08-16 2006-02-16 Telephus Inc. Multilayered anisotropic conductive adhesive for fine pitch

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6861290B1 (en) * 1995-12-19 2005-03-01 Micron Technology, Inc. Flip-chip adaptor package for bare die
TW511122B (en) * 1999-12-10 2002-11-21 Ebara Corp Method for mounting semiconductor device and structure thereof
EP1223612A4 (en) * 2000-05-12 2005-06-29 Matsushita Electric Ind Co Ltd Semiconductor device mounting circuit board, method of producing the same, and method of producing mounting structure using the same
US7087458B2 (en) * 2002-10-30 2006-08-08 Advanpack Solutions Pte. Ltd. Method for fabricating a flip chip package with pillar bump and no flow underfill
JP4390541B2 (en) * 2003-02-03 2009-12-24 Ｎｅｃエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US20050014313A1 (en) * 2003-03-26 2005-01-20 Workman Derek B. Underfill method
US20050028361A1 (en) * 2003-08-07 2005-02-10 Indium Corporation Of America Integrated underfill process for bumped chip assembly
US20060216860A1 (en) * 2005-03-25 2006-09-28 Stats Chippac, Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
US7294451B2 (en) * 2003-11-18 2007-11-13 Texas Instruments Incorporated Raised solder-mask-defined (SMD) solder ball pads for a laminate electronic circuit board
JP4534062B2 (en) * 2005-04-19 2010-09-01 ルネサスエレクトロニクス株式会社 Semiconductor device
JP4609296B2 (en) * 2005-12-05 2011-01-12 株式会社日立製作所 High temperature solder, high temperature solder paste material, and power semiconductor device using the same
US7786001B2 (en) * 2007-04-11 2010-08-31 International Business Machines Corporation Electrical interconnect structure and method
TWI351729B (en) * 2007-07-03 2011-11-01 Siliconware Precision Industries Co Ltd Semiconductor device and method for fabricating th
KR100838647B1 (en) * 2007-07-23 2008-06-16 한국과학기술원 Wafer-level acf flip chip package using double-layered acf/ncf
JP2009212501A (en) * 2008-02-08 2009-09-17 Seiko Instruments Inc Light emitting device and method of manufacturing the same
US7812460B2 (en) * 2008-05-30 2010-10-12 Unimicron Technology Corp. Packaging substrate and method for fabricating the same
CN101621101A (en) * 2008-06-30 2010-01-06 展晶科技(深圳)有限公司 LED and production method thereof
JP5465942B2 (en) * 2009-07-16 2014-04-09 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US8988895B2 (en) * 2011-08-23 2015-03-24 Tessera, Inc. Interconnection elements with encased interconnects

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6777464B1 (en) * 1997-03-31 2004-08-17 Hitachi Chemical Company, Ltd. Circuit connecting material, and structure and method of connecting circuit terminal
US20020067486A1 (en) * 2000-09-25 2002-06-06 S. Forney Leroy Solderability assessment
US20060033213A1 (en) * 2004-08-16 2006-02-16 Telephus Inc. Multilayered anisotropic conductive adhesive for fine pitch

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Dowbenko, R., Anderson, C., and Chang, W. Imidazole Complexes as Hardeners for Epoxy Adhesives. 1971. Ind. Eng. Chem. Prod. Res. Develop., Vol. 10, No. 3. *
Rannulu, N. and Rodgers, M. Solvation of copper ions by imidazole. 10 February 2005. Phys. Chem. Chem. Phys. *

Also Published As

Publication number Publication date
US8497579B1 (en) 2013-07-30
US20130214407A1 (en) 2013-08-22

Similar Documents

Publication Publication Date Title
US9825010B2 (en) Stacked chip package structure and manufacturing method thereof
CN105845635B (en) Electron package structure
US8012868B1 (en) Semiconductor device having EMI shielding and method therefor
US20130026657A1 (en) Semiconductor package and method of fabricating the same
US8890329B2 (en) Semiconductor device
US8975735B2 (en) Redistribution board, electronic component and module
TW201533860A (en) Wiring board and semiconductor device using the same
KR20150130660A (en) Semiconductor package and method of manufacturing the same
US20150041972A1 (en) Semiconductor package and fabrication method thereof
TW201340261A (en) Semiconductor device and manufacturing method thereof
US8497579B1 (en) Semiconductor packaging method and structure thereof
TW201719829A (en) Electronic package and method of manufacture
TW201611225A (en) Semiconductor device
US20090260872A1 (en) Module for packaging electronic components by using a cap
US20150228602A1 (en) Semicondcutor chip and semionducot module
TW201606947A (en) Electric connection structure between front and back surfaces of chip and manufacturing method thereof
TWI517354B (en) Semiconductor package with embedded decoupling capacitors
SG191464A1 (en) Semiconductor packaging method and structure thereof
US20140284803A1 (en) Semiconductor package and fabrication method thereof
JP3178122U (en) Semiconductor mounting products
US20130214419A1 (en) Semiconductor packaging method and structure thereof
US10079190B2 (en) Methods of fabricating an electronic package structure
MY164814A (en) Leadframe area array packaging technology
US8581384B2 (en) Semiconductor package structure
CN103313175A (en) Micro-electro-mechanical microphone encapsulating module

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION