JP3178122U - Semiconductor mounting products - Google Patents

Semiconductor mounting products Download PDF

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JP3178122U
JP3178122U JP2012003721U JP2012003721U JP3178122U JP 3178122 U JP3178122 U JP 3178122U JP 2012003721 U JP2012003721 U JP 2012003721U JP 2012003721 U JP2012003721 U JP 2012003721U JP 3178122 U JP3178122 U JP 3178122U
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bonding surface
conductive particles
contact
copper
conductive
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政宏 施
淑真 林
政帆 林
永偉 謝
伯勳 姜
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▲き▼邦科技股▲分▼有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

【課題】銅イオンの遊離防止が可能な半導体実装品を提供する。
【解決手段】銅を含むバンプ１３２は、第２接合表面１３３と環状の表面１３４からなる。第２接合表面１３３は、複数個の第２導電性粒子の接触領域１３３ａと複数個の第２非導電性粒子の接触領域１３３ｂを有する。導電性粒子１２１は、第１接合表面１１３の第１導電性粒子の接触領域１１３ａと第２接合表面１３３の第２導電性粒子の接触領域１３３ａに位置される。遊離防止材１２２は、第２接合表面１３３の第２非導電性粒子の接触領域１３３ｂに結合されると共に銅を含むバンプ１３２の環状の表面１３４を被覆する。
【選択図】図１ＣA semiconductor packaging product capable of preventing the liberation of copper ions is provided.
A bump 132 including copper includes a second bonding surface 133 and an annular surface 134. The second bonding surface 133 has a plurality of second conductive particle contact regions 133a and a plurality of second non-conductive particle contact regions 133b. The conductive particles 121 are located in the first conductive particle contact region 113 a of the first bonding surface 113 and the second conductive particle contact region 133 a of the second bonding surface 133. The release preventing material 122 is bonded to the contact region 133 b of the second non-conductive particle of the second bonding surface 133 and covers the annular surface 134 of the bump 132 containing copper.
[Selection] Figure 1C

Description

本考案は、半導体実装品に関し、より詳しくは、銅イオンの遊離防止が可能な半導体実装品に関する。   The present invention relates to a semiconductor mounted product, and more particularly to a semiconductor mounted product capable of preventing the release of copper ions.

近年、電子製品が小型化および軽量化の趨勢にあることから、電子製品内部の回路のレイアウトの間隔もますます小さくなる傾向にある。   In recent years, since electronic products are becoming smaller and lighter, the circuit layout intervals inside the electronic products tend to become smaller and smaller.

しかしながら、前述した従来の技術では、回路配線の間隔が小さいほどショートする確率が上がるといった問題があった。   However, the above-described conventional technique has a problem that the probability of short-circuiting increases as the circuit wiring interval decreases.

本考案は、このような従来の問題に鑑みてなされたものであり、その目的は、銅イオンの遊離防止が可能な半導体実装品を提供することにある。   The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a semiconductor mounting product capable of preventing the release of copper ions.

上述の課題を解決し、目的を達成するために、本考案に係る半導体実装品は、上表面および前記上表面に設けられた複数個の接点を有し、各前記接点に第１接合表面があり、前記第１接合表面に複数個の第１導電性粒子の接触領域および複数個の第１非導電性粒子の接触領域がある基板を供給するステップと、複数個の導電性粒子および複数個の遊離防止材が混合された導電可能な遊離防止コロイドを前記基板の前記上表面および前記接点上に形成するステップと、主動面および前記主動面に設けられた複数個の銅を含むバンプを備えたチップを前記基板にフリップチップ結合するステップと、を含む。前記主動面は、前記基板の前記上表面に臨む。前記導電可能な遊離防止コロイドは、前記銅を含むバンプを被覆する。前記銅を含むバンプは、各々第２接合表面および環状の表面を有する。前記第２接合表面には、複数個の第２導電性粒子の接触領域および複数個の第２非導電性粒子の接触領域を有する。前記銅を含むバンプは、前記導電性粒子により前記接点に電気的に接続される。前記導電性粒子は、前記第１接合表面と前記第２接合表面との間にあり、且つ前記第１接合表面の前記第１導電性粒子の接触領域と前記第２接合表面の前記第２導電性粒子の接触領域とを電気的に接続する。前記遊離防止材は、近傍の前記導電性粒子の間にあり、且つ、各前記第１接合表面と各前記第２接合表面との間にあり、前記第２接合表面の前記第２非導電性粒子の接触領域に結合して、更に前記銅を含むバンプの前記環状の表面を被覆することを特徴とする。   In order to solve the above-described problems and achieve the object, a semiconductor package according to the present invention has an upper surface and a plurality of contacts provided on the upper surface, and each contact has a first bonding surface. Providing a substrate having a plurality of first conductive particle contact areas and a plurality of first non-conductive particle contact areas on the first bonding surface; a plurality of conductive particles and a plurality of conductive particles; Forming a conductive anti-release colloid mixed with an anti-release material on the upper surface and the contact of the substrate, and a main surface and a bump including a plurality of copper provided on the main surface. Flip-chip bonding the chip to the substrate. The main moving surface faces the upper surface of the substrate. The conductive anti-release colloid covers the copper-containing bump. Each of the bumps containing copper has a second bonding surface and an annular surface. The second bonding surface has a contact region of a plurality of second conductive particles and a contact region of a plurality of second nonconductive particles. The bump containing copper is electrically connected to the contact by the conductive particles. The conductive particles are between the first bonding surface and the second bonding surface, and the contact region of the first conductive particles on the first bonding surface and the second conductivity on the second bonding surface. It electrically connects with the contact area of the conductive particles. The release preventing material is between the conductive particles in the vicinity, and is between each of the first bonding surfaces and each of the second bonding surfaces, and the second nonconductive material of the second bonding surface. The annular surface of the bump containing copper is further bonded to the contact area of the particles.

前記導電可能な遊離防止コロイドにある前記遊離防止材が、前記銅を含むバンプの前記環状の表面を被覆することから、前記銅を含むバンプ中の銅イオンが遊離した場合、前記遊離防止材が直ちに銅イオンを捕捉してショートの発生を防止することができる。   Since the release preventing material in the conductive release preventing colloid covers the annular surface of the bump containing copper, when the copper ions in the bump containing copper are released, the release preventing material is It is possible to immediately capture copper ions and prevent the occurrence of a short circuit.

本考案によれば、銅イオンの遊離防止が可能な半導体実装品が得られる。   According to the present invention, it is possible to obtain a semiconductor package capable of preventing the release of copper ions.

本考案の第１実施形態による半導体実装品の製造途中の状態を示す断面図。Sectional drawing which shows the state in the middle of manufacture of the semiconductor mounting goods by 1st Embodiment of this invention. 本考案の第１実施形態による半導体実装品の製造途中の状態を示す断面図。Sectional drawing which shows the state in the middle of manufacture of the semiconductor mounting goods by 1st Embodiment of this invention. 本考案の第１実施形態による半導体実装品の断面図。Sectional drawing of the semiconductor mounting goods by 1st Embodiment of this invention.

以下に図面を参照して、本考案を実施するための形態について、詳細に説明する。なお、本考案は、以下に説明する実施形態に限定されるものではない。まず、本考案の半導体実装品の第１実施形態について説明する。
（第１実施形態）
本考案の第１実施形態の構成を図１Ａから図１Ｃに示す。図１Ａから図１Ｃは、本考案に係る好ましい実施形態における半導体実装方法および半導体実装品を示すものである。該方法は、下記のステップを有する。先ず、図１Ａでは、上表面１１１と前記上表面１１１に設けられた複数個の接点１１２を備えた基板１１０を供給する。前記接点１１２は、基板１１０上のピン、又は回路に接続されたバンプのボンドパッドでよい。前記各接点１１２は、第１接合表面１１３と側壁１１４を有する。前記第１接合表面１１３は、複数個の第１導電性粒子の接触領域１１３ａと複数個の第１非導電性粒子の接触領域１１３ｂを有する。
続いて、図１Ｂでは、導電可能な遊離防止コロイド１２０を前記基板１１０の前記上表面１１１と前記接点１１２上に形成する。前記導電可能な遊離防止コロイド１２０は、複数個の導電性粒子１２１と複数個の遊離防止材１２２が混合されている。本実施形態では、前記遊離防止材１２２の材料は、有機はんだ付け保護剤である。前記有機はんだ付け保護剤の材料は、ベンズイミダゾール又はイミダゾール誘導体のうちから選択される。前記イミダゾール誘導体は、ベンゾトリアゾール、フェニルイミダゾール、置換フェニルイミダゾール、若しくはアリールフェニルイミダゾール、又はその混合体のうちの一つでよい。前記ベンズイミダゾールは、ベンゾトリアゾール、フェニルイミダゾール、置換フェニルイミダゾール、若しくはアリールフェニルイミダゾール、又はその混合体のうちの一つでよい。 Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited to the embodiments described below. First, a first embodiment of a semiconductor package according to the present invention will be described.
(First embodiment)
The configuration of the first embodiment of the present invention is shown in FIGS. 1A to 1C. 1A to 1C show a semiconductor mounting method and a semiconductor mounted product in a preferred embodiment according to the present invention. The method has the following steps. First, in FIG. 1A, a substrate 110 having an upper surface 111 and a plurality of contacts 112 provided on the upper surface 111 is supplied. The contacts 112 may be pins on the substrate 110 or bump bond pads connected to a circuit. Each contact 112 has a first bonding surface 113 and a side wall 114. The first bonding surface 113 has a plurality of first conductive particle contact regions 113a and a plurality of first non-conductive particle contact regions 113b.
Subsequently, in FIG. 1B, a conductive anti-release colloid 120 is formed on the upper surface 111 and the contact 112 of the substrate 110. The electrically conductive release preventing colloid 120 includes a plurality of conductive particles 121 and a plurality of release prevention materials 122 mixed together. In this embodiment, the material of the release preventing material 122 is an organic soldering protective agent. The material of the organic soldering protective agent is selected from benzimidazole or imidazole derivatives. The imidazole derivative may be one of benzotriazole, phenylimidazole, substituted phenylimidazole, arylphenylimidazole, or a mixture thereof. The benzimidazole may be one of benzotriazole, phenylimidazole, substituted phenylimidazole, arylphenylimidazole, or a mixture thereof.

最後に、図１Ｃでは、主動面１３１と前記主動面１３１に設けられた複数個の銅を含むバンプ１３２を備えたチップ１３０を前記基板１１０にフリップチップ結合する。本実施形態では、前記銅を含むバンプ１３２の材料は、銅／ニッケル、又は銅／ニッケル／金のうちから一つ選択する。前記主動面１３１は、前記基板１１０の前記上表面１１１に臨む。前記導電可能な遊離防止コロイド１２０は、前記銅を含むバンプ１３２を被覆する。各前記銅を含むバンプ１３２には、第２接合表面１３３と環状の表面１３４がある。前記第２接合表面１３３は、複数個の第２導電性粒子の接触領域１３３ａと複数個の第２非導電性粒子の接触領域１３３ｂを有する。前記銅を含むバンプ１３２は、前記導電性粒子１２１により前記接点１１２に電気的に接続される。前記導電性粒子１２１は、前記第１接合表面１１３と前記第２接合表面１３３との間にあって、前記第１接合表面１１３の前記第１導電性粒子の接触領域１１３ａと前記第２接合表面１３３の前記第２導電性粒子の接触領域１３３ａとを電気的に接続する。前記遊離防止材１２２は、近傍の導電性粒子１２１の間にあり、且つ、各前記第１接合表面１１３と各前記第２接合表面１３３の間にあり、前記第２接合表面１３３の前記第２非導電性粒子の接触領域１３３ｂに結合して更に前記銅を含むバンプ１３２の前記環状の表面１３４を被覆する。また、前記遊離防止材１２２は前記第１接合表面１１３の前記第１非導電性粒子の接触領域１１３ｂにも結合し、前記接点１１２の前記側壁１１４を被覆して、半導体実装品１００を形成する。前記導電可能な遊離防止コロイド１２０にある前記遊離防止材１２２は、前記銅を含むバンプ１３２の前記環状の表面１３４を被覆可能なことから、前記銅を含むバンプ１３２中の銅イオンが遊離した場合、前記遊離防止材１２２は直ちに遊離した銅イオンを捕捉してショートの発生を防止し、前記半導体実装品１００の歩留りを高めることができる。   Finally, in FIG. 1C, a chip 130 having a main driving surface 131 and a plurality of copper-containing bumps 132 provided on the main driving surface 131 is flip-chip bonded to the substrate 110. In this embodiment, the material of the bump 132 containing copper is selected from copper / nickel or copper / nickel / gold. The main moving surface 131 faces the upper surface 111 of the substrate 110. The conductive anti-release colloid 120 covers the bump 132 containing copper. Each of the copper-containing bumps 132 has a second bonding surface 133 and an annular surface 134. The second bonding surface 133 includes a plurality of second conductive particle contact regions 133a and a plurality of second non-conductive particle contact regions 133b. The bump 132 containing copper is electrically connected to the contact 112 by the conductive particles 121. The conductive particles 121 are between the first bonding surface 113 and the second bonding surface 133, and the contact regions 113 a of the first conductive particles on the first bonding surface 113 and the second bonding surface 133. The contact region 133a of the second conductive particles is electrically connected. The release preventing material 122 is between the adjacent conductive particles 121 and between each of the first bonding surfaces 113 and each of the second bonding surfaces 133, and the second bonding surface 133 has the second of the second bonding surfaces 133. The annular surface 134 of the bump 132 containing copper is further bonded to the contact region 133b of the non-conductive particles. Further, the release preventing material 122 is also bonded to the contact region 113b of the first non-conductive particle on the first bonding surface 113 and covers the side wall 114 of the contact 112 to form the semiconductor package 100. . Since the release preventing material 122 in the conductive release preventing colloid 120 can cover the annular surface 134 of the bump 132 containing copper, the copper ions in the bump 132 containing copper are released. The release preventing material 122 can immediately capture the released copper ions to prevent the occurrence of short-circuits and increase the yield of the semiconductor package 100.

図１Ｃは本考案に係る好ましい実施形態における半導体実装品１００であり、基板１１０、導電可能な遊離防止コロイド１２０、及びチップ１３０を備える。前記基板１１０は、上表面１１１と前記上表面１１１に設けられた複数個の接点１１２を有し、前記各接点１１２には第１接合表面１１３があり、前記第１接合表面１１３には複数個の第１導電性粒子の接触領域１１３ａと複数個の第１非導電性粒子の接触領域１１３ｂがある。前記導電可能な遊離防止コロイド１２０は、前記基板１１０の前記上表面１１１と前記接点１１２上に形成されるが、複数個の導電性粒子１２１と複数個の遊離防止材１２２が混合される。前記チップ１３０は、前記基板１１０にフリップチップ結合され、主動面１３１と前記主動面１３１に設けられた複数個の銅を含むバンプ１３２を備える。前記主動面１３１は、前記基板１１０の前記上表面１１１に臨む。前記導電可能な遊離防止コロイド１２０は前記銅を含むバンプ１３２を被覆する。各前記銅を含むバンプ１３２には、第２接合表面１３３と環状の表面１３４がある。前記第２接合表面１３３には、複数個の第２導電性粒子の接触領域１３３ａと複数個の第２非導電性粒子の接触領域１３３ｂがある。前記銅を含むバンプ１３２は、前記導電性粒子１２１により前記接点１１２に電気的に接続される。前記導電性粒子１２１は、前記第１接合表面１１３と前記第２接合表面１３３との間にあり、前記第１接合表面１１３の前記第１導電性粒子の接触領域１１３ａと前記第２接合表面１３３の前記第２導電性粒子の接触領域１３３ａとを電気的に接続する。前記遊離防止材１２２は、近傍の導電性粒子１２１の間にあり、且つ、各前記第１接合表面１１３と前記各第２接合表面１３３との間にあり、前記第２接合表面１３３の前記第２非導電性粒子の接触領域１３３ｂと前記第１接合表面１１３の前記第１非導電性粒子の接触領域１１３ｂに結合して、更に前記銅を含むバンプ１３２の前記環状の表面１３４と前記接点１１２の前記側壁１１４を被覆する。   FIG. 1C shows a semiconductor package 100 according to a preferred embodiment of the present invention, which includes a substrate 110, a conductive release preventing colloid 120, and a chip 130. The substrate 110 has an upper surface 111 and a plurality of contacts 112 provided on the upper surface 111, each contact 112 has a first bonding surface 113, and the first bonding surface 113 has a plurality of contacts. There are a first conductive particle contact region 113a and a plurality of first non-conductive particle contact regions 113b. The conductive release preventing colloid 120 is formed on the upper surface 111 and the contact 112 of the substrate 110, and a plurality of conductive particles 121 and a plurality of release preventing materials 122 are mixed. The chip 130 is flip-chip bonded to the substrate 110 and includes a main driving surface 131 and a plurality of bumps 132 including copper provided on the main driving surface 131. The main moving surface 131 faces the upper surface 111 of the substrate 110. The conductive anti-release colloid 120 covers the bump 132 containing copper. Each of the copper-containing bumps 132 has a second bonding surface 133 and an annular surface 134. The second bonding surface 133 includes a plurality of second conductive particle contact regions 133a and a plurality of second non-conductive particle contact regions 133b. The bump 132 containing copper is electrically connected to the contact 112 by the conductive particles 121. The conductive particles 121 are between the first bonding surface 113 and the second bonding surface 133, and the contact region 113 a of the first conductive particles on the first bonding surface 113 and the second bonding surface 133. Are electrically connected to the contact region 133a of the second conductive particles. The release preventing material 122 is between the adjacent conductive particles 121 and between each of the first bonding surfaces 113 and each of the second bonding surfaces 133, and 2 The non-conductive particle contact region 133b and the first non-conductive particle contact region 113b of the first bonding surface 113 are coupled to the annular surface 134 and the contact 112 of the bump 132 containing copper. The side wall 114 is covered.

以上、本考案は、このような実施形態に限定されるものではなく、考案の趣旨を逸脱しない範囲において、種々の形態で実施することができる。   As mentioned above, this invention is not limited to such embodiment, In the range which does not deviate from the meaning of invention, it can implement with a various form.

１００ ・・・・半導体実装構造
１１０ ・・・・基板
１１１ ・・・・上表面
１１２ ・・・・接点
１１３ ・・・・第１接合表面
１１３ａ ・・・第１導電性粒子の接触領域
１１３ｂ ・・・第１非導電性粒子の接触領域
１１４ ・・・・側壁
１２０ ・・・・導電可能な遊離防止コロイド
１２１ ・・・・導電性粒子
１２２ ・・・・遊離防止材
１３０ ・・・・チップ
１３１ ・・・・主動面
１３２ ・・・・銅を含むバンプ
１３３ ・・・・第２接合表面
１３３ａ ・・・第２導電性粒子の接触領域
１３３ｂ ・・・第２非導電性粒子の接触領域
１３４ ・・・・環状の表面 DESCRIPTION OF SYMBOLS 100 ...... Semiconductor mounting structure 110 ...... Board | substrate 111 ...... Upper surface 112 ...... Contact 113 ...... 1st joining surface 113a ... Contact area | region 113b of 1st electroconductive particle ··· Contact region 114 of first nonconductive particle ··· Side wall 120 ··· Conductive release preventing colloid 121 ··· Conductive particle 122 ··· Release preventing material 130 ··· Chip 131 ··· Main driving surface 132 ··· Bump 133 containing copper ··· Second bonding surface 133a · Contact region 133b of second conductive particle · · · Contact region of second non-conductive particle 134... Annular surface

Claims (7)

上表面および前記上表面に設けられた複数個の接点を有し、各前記接点に第１接合表面があり、前記第１接合表面に複数個の第１導電性粒子の接触領域および複数個の第１非導電性粒子の接触領域がある基板と、
前記基板の前記上表面および前記接点上に形成され、複数個の導電性粒子および複数個の遊離防止材が混合された導電可能な遊離防止コロイドと、
前記基板にフリップチップ結合され、主動面および前記主動面に設けられた複数個の銅を含むバンプを備えたチップと、を備え、
前記主動面は、前記基板の前記上表面に臨み、
前記導電可能な遊離防止コロイドは、前記銅を含むバンプを被覆し、
前記銅を含むバンプは、各々第２接合表面および環状の表面を有し、
前記第２接合表面には、複数個の第２導電性粒子の接触領域および複数個の第２非導電性粒子の接触領域を有し、
前記銅を含むバンプは、前記導電性粒子により前記接点に電気的に接続され、
前記導電性粒子は、前記第１接合表面と前記第２接合表面との間にあり、且つ前記第１接合表面の前記第１導電性粒子の接触領域と前記第２接合表面の前記第２導電性粒子の接触領域とを電気的に接続し、
前記遊離防止材は、近傍の前記導電性粒子の間にあり、且つ各前記第１接合表面と各前記第２接合表面との間にあり、前記第２接合表面の前記第２非導電性粒子の接触領域に結合して、更に前記銅を含むバンプの前記環状の表面を被覆することを特徴とする半導体実装品。 An upper surface and a plurality of contacts provided on the upper surface, each contact having a first bonding surface, a plurality of first conductive particle contact areas and a plurality of contacts on the first bonding surface; A substrate with a contact area of first non-conductive particles;
A conductive anti-release colloid formed on the upper surface of the substrate and the contact and mixed with a plurality of conductive particles and a plurality of release prevention materials;
A chip that is flip-chip bonded to the substrate and includes a main moving surface and a plurality of copper-containing bumps provided on the main moving surface;
The main moving surface faces the upper surface of the substrate;
The conductive anti-release colloid covers the copper-containing bump;
Each of the bumps containing copper has a second bonding surface and an annular surface,
The second bonding surface has a contact region of a plurality of second conductive particles and a contact region of a plurality of second non-conductive particles,
The bump containing copper is electrically connected to the contact by the conductive particles,
The conductive particles are between the first bonding surface and the second bonding surface, and the contact region of the first conductive particles on the first bonding surface and the second conductivity on the second bonding surface. Electrically connected to the contact area of the conductive particles,
The release preventing material is between the conductive particles in the vicinity, and between the first bonding surface and the second bonding surface, and the second non-conductive particles on the second bonding surface. A semiconductor mounting product, wherein the annular surface of the bump including copper is further coated with the contact region. 前記遊離防止材は、前記第１接合表面の前記第１非導電性粒子の接触領域に結合することを特徴とする請求項１に記載の半導体実装品。   2. The semiconductor package according to claim 1, wherein the release preventing material is bonded to a contact region of the first non-conductive particles on the first bonding surface. 各前記接点は、側壁を有し、
前記遊離防止材は、前記側壁を被覆することを特徴とする請求項１に記載の半導体実装品。 Each said contact has a sidewall,
The semiconductor mounting product according to claim 1, wherein the release preventing material covers the side wall. 前記遊離防止材の材料は、有機はんだ付け保護剤であることを特徴とする請求項１に記載の半導体実装品。   The semiconductor mounting product according to claim 1, wherein the material of the release preventing material is an organic soldering protective agent. 前記有機はんだ付け保護剤の材料は、ベンズイミダゾール又はイミダゾール誘導体のうちから選択することを特徴とする請求項４に記載の半導体実装品。   The material for the organic soldering protective agent is selected from benzimidazole or imidazole derivatives. 前記イミダゾール誘導体は、ベンゾトリアゾール、フェニルイミダゾール、置換フェニルイミダゾール、若しくはアリールフェニルイミダゾール、又はその混合体のうちの一つであり、
前記ベンズイミダゾールは、ベンゾトリアゾール、フェニルイミダゾール、置換フェニルイミダゾール、若しくはアリールフェニルイミダゾール、又はその混合体うちの一つであることを特徴とする請求項５に記載の半導体実装品。 The imidazole derivative is one of benzotriazole, phenylimidazole, substituted phenylimidazole, or arylphenylimidazole, or a mixture thereof,
6. The semiconductor package according to claim 5, wherein the benzimidazole is one of benzotriazole, phenylimidazole, substituted phenylimidazole, arylphenylimidazole, or a mixture thereof. 前記銅を含むバンプの材料は、銅／ニッケル、又は銅／ニッケル／金のうちの一つから選択することを特徴とする請求項１に記載の半導体実装品。   2. The semiconductor package according to claim 1, wherein a material of the bump containing copper is selected from one of copper / nickel and copper / nickel / gold.
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JP2013140937A (en) * 2012-01-03 2013-07-18 ▲き▼邦科技股▲分▼有限公司 Semiconductor packaging method and semiconductor assembly

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013140937A (en) * 2012-01-03 2013-07-18 ▲き▼邦科技股▲分▼有限公司 Semiconductor packaging method and semiconductor assembly

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