TW201530731A - 與陶瓷基板上之射頻元件之封裝相關的元件及方法 - Google Patents

與陶瓷基板上之射頻元件之封裝相關的元件及方法 Download PDF

Info

Publication number
TW201530731A
TW201530731A TW103138412A TW103138412A TW201530731A TW 201530731 A TW201530731 A TW 201530731A TW 103138412 A TW103138412 A TW 103138412A TW 103138412 A TW103138412 A TW 103138412A TW 201530731 A TW201530731 A TW 201530731A
Authority
TW
Taiwan
Prior art keywords
ceramic substrate
conductive
die
electronic component
packaged electronic
Prior art date
Application number
TW103138412A
Other languages
English (en)
Other versions
TWI652789B (zh
Inventor
Anthony James Lobianco
Howard E Chen
David Scott Whitefield
Original Assignee
Skyworks Solutions Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Skyworks Solutions Inc filed Critical Skyworks Solutions Inc
Publication of TW201530731A publication Critical patent/TW201530731A/zh
Application granted granted Critical
Publication of TWI652789B publication Critical patent/TWI652789B/zh

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007—Casings
    • H05K9/002—Casings with localised screening
    • H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
    • H05K9/0024—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields
    • H05K9/0026—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields integrally formed from metal sheet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67236—Apparatus for manufacturing or treating in a plurality of work-stations the substrates being processed being not semiconductor wafers, e.g. leadframes or chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16052—Shape in top view
    • H01L2224/16055—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16113—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1712—Layout
    • H01L2224/1713—Square or rectangular array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1712—Layout
    • H01L2224/17179—Corner adaptations, i.e. disposition of the bump connectors at the corners of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H01L2924/1421—RF devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Electromagnetism (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Geometry (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Transceivers (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Inorganic Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本發明係關於與陶瓷基板上之射頻(RF)元件之封裝相關的元件及方法。在一些實施例中，一種封裝式電子元件可包括經組態以收納一或多個組件之一陶瓷基板。該陶瓷基板可包括與一接地平面進行電接觸之一導電層。該封裝式電子元件可進一步包括具有一積體電路且安裝於該陶瓷基板之一表面上的一晶粒。該封裝式電子元件可進一步包括實施於該晶粒上方以提供屏蔽功能性之一保形導電塗層。該封裝式電子元件可進一步包括在該保形導電塗層與該導電層之間的一電連接。

Description

與陶瓷基板上之射頻元件之封裝相關的元件及方法 相關申請案之交叉參考
本申請案主張2013年11月5日申請之名為「與陶瓷基板上之射頻元件之封裝相關的元件及方法(DEVICES AND METHODS RELATED TO PACKAGING OF RADIO-FREQUENCY DEVICES ON CERAMIC SUBSTRATES)」之美國臨時申請案第61/900,394號的優先權，該臨時申請案之揭示內容的全文係據此以引用方式明確地併入本文中。
本發明大體上係關於封裝式射頻(RF)模組之屏蔽。
電磁(EM)場可自諸如射頻(RF)模組之RF元件的區域產生，或對該區域產生不良影響。此EM干擾(EMI)可降級使用此RF模組之無線元件的效能。一些RF模組可具備EM屏蔽以處理與EMI相關聯之此等效能問題。
根據一些實施，本發明係關於一種封裝式電子元件，該封裝式電子元件包括經組態以收納一或多個組件之一陶瓷基板。該陶瓷基板包括與一接地平面進行電接觸之一導電層。該封裝式電子元件進一步包括具有一積體電路之一晶粒。該晶粒安裝於該陶瓷基板之一表面上。該封裝式電子元件進一步包括實施於該晶粒上方以提供屏蔽功能 性之一保形導電塗層。該封裝式電子元件進一步包括在該保形導電塗層與該導電層之間的一電連接。
在一些實施例中，該保形導電塗層可實質上直接地實施於該晶粒上。直接地在該晶粒上之該保形導電塗層可引起該封裝式電子元件為一低剖面屏蔽型元件。
在一些實施例中，該晶粒可經組態為一覆晶元件。該封裝式電子元件可進一步包括實施於該覆晶元件與該陶瓷基板之間的一底膠。該底膠可包括經組態以在該覆晶元件之側壁與該陶瓷基板之該表面之間提供一角形過渡的一邊緣剖面。該底膠之該角形過渡剖面可經組態以促進在該覆晶元件與該陶瓷基板之間的該保形導電塗層之改良式覆蓋。
在一些實施例中，該積體電路可包括一射頻(RF)切換電路。在一些實施例中，該晶粒可為一絕緣體上矽(SOI)晶粒。
在一些實施例中，該電連接可包括在該陶瓷基板之該表面上的該保形導電塗層之一部分，及經組態以在該陶瓷基板之該表面上的該保形導電塗層與該導電層之間提供電連接的複數個導電通孔。該導電層可包括實施於該陶瓷基板內之一或多個導電條帶。該導電層可包括該等導電條帶中之複數個導電條帶，該複數個導電條帶經配置以在該陶瓷基板之邊緣處或附近大體上形成一周界。該一或多個導電條帶中之每一者可橫向地與該等對應導電通孔至少部分地重疊。
在一些實施例中，該電連接可包括在該陶瓷基板之該表面上的該保形導電塗層之一部分，該部分延伸至該陶瓷基板之側邊緣。該導電層可包括沿著該陶瓷基板之該對應側邊緣的一邊緣，使得該導電層之該邊緣與該保形導電塗層進行電接觸。該導電層可包括沿著該陶瓷基板之該對應側邊緣的一導電條帶。該導電條帶可包括充分地曝露於該陶瓷基板之該對應側邊緣上以促進該導電條帶與該保形導電塗層之 間的該電接觸的一邊緣。該導電層可包括該等導電條帶中之複數個導電條帶，該複數個導電條帶經配置成使得該陶瓷基板之每一邊緣包括與該保形導電塗層進行電接觸的該導電條帶之該對應經曝露邊緣。
在一些實施例中，該保形導電塗層可包括藉由沈積而形成之一金屬漆層或一導電層。在一些實施例中，該陶瓷基板可包括一低溫共燒陶瓷(LTCC)基板。在一些實施例中，該封裝式電子元件可進一步包括實施於該陶瓷基板之一底面上的複數個接觸墊。該等接觸墊可經組態以允許將該封裝式電子元件安裝於一電路板上。在一些實施例中，該封裝式電子元件可進一步包括實施於該晶粒上方之一包覆模製件，使得該保形塗層實施於該包覆模製件之一表面上。該包覆模製件可經定尺寸為使得其側壁與該陶瓷基板之對應側壁大體上對準。
在數個實施中，本發明係關於一種無線元件，該無線元件包括經組態以產生一射頻(RF)信號之一收發器，及經組態以處理該RF信號之一RF模組。該RF模組包括經組態以收納一或多個組件之一陶瓷基板。該陶瓷基板包括與一接地平面進行電接觸之一導電層。該RF模組進一步包括具有一積體電路之一晶粒，其中該晶粒安裝於該陶瓷基板之一表面上。該RF模組進一步包括實施於該晶粒上方以提供屏蔽功能性之一保形導電塗層。該RF模組進一步包括在該保形導電塗層與該導電層之間的一電連接。該無線元件進一步包括與該RF模組通信之一天線。該天線經組態以促進該經處理RF信號之傳輸。
在一些實施中，本發明係關於一種用於製造一封裝式射頻(RF)模組之方法。該方法包括形成或提供經組態以收納一或多個組件之一陶瓷基板。該陶瓷基板包括與一接地平面進行電接觸之一導電層。該方法進一步包括將一晶粒安裝於該陶瓷基板之一表面上，其中該晶粒包括一積體電路。該方法進一步包括將一保形導電塗層形成於該晶粒上方且形成為與該導電層進行電接觸，以藉此向該晶粒提供屏蔽功能 性。
在一些實施例中，該陶瓷基板可包括以具有由一線柵格界定之一單元陣列之一堆疊而配置的複數個陶瓷層，沿著該線柵格之一單粒化程序引起將該等單元分離成複數個個別單元。該方法可進一步包括在該保形導電塗層之該形成之前單粒化該單元陣列。可在該單粒化步驟之前對該等單元中之每一者執行該晶粒之該安裝。
根據一些教示，本發明係關於一種用於製造複數個封裝式射頻(RF)模組之陶瓷基板。該陶瓷基板包括以具有一單元陣列之一堆疊而配置的複數個陶瓷層。每一單元經組態以收納一或多個組件。該單元陣列係由一線柵格界定，沿著該線柵格之一單粒化程序引起將該等單元分離成複數個個別單元。該陶瓷基板進一步包括實施於該堆疊內之一接地平面。該陶瓷基板進一步包括實施於該堆疊內且與該接地平面進行電接觸之一導電層。該導電層經組態成使得在該單粒化程序後，每一個別單元之至少一個邊緣就包括該導電層之一經曝露邊緣。
在一些實施例中，該導電層可包括沿著該線柵格中之一對應線而實施的一導電條帶，使得沿著該線之該單粒化程序引起使兩個相鄰單元分離，其中每一單元具有該導電條帶之一切割邊緣作為該經曝露邊緣。在一些實施例中，該陶瓷基板可進一步包括一介電層、一被動組件及一導體特徵中之一或多者。該被動組件可包括一電阻性器件、一電容性器件或一電感性器件。該導體特徵可包括一導體跡線或一導電通孔。在一些實施例中，該陶瓷基板可包括一低溫共燒陶瓷(LTCC)基板。
出於概述本發明之目的，已在本文中描述本發明之某些態樣、優勢及新穎特徵。應理解，根據本發明之任一特定實施例，未必可達成所有此等優勢。因此，可以達成或最佳化如本文所教示之一個優勢或優勢群組而未必達成如本文中可教示或提出之其他優勢的方式來實 施或進行本發明。
100‧‧‧封裝式元件
102‧‧‧保形導電塗層
104‧‧‧未經囊封元件/覆晶
106‧‧‧陶瓷基板
106a‧‧‧經單粒化陶瓷基板
106b‧‧‧經單粒化陶瓷基板
108‧‧‧上部表面
110‧‧‧接地節點
112‧‧‧電連接組態
116‧‧‧表面
120‧‧‧焊球
122‧‧‧底膠
130‧‧‧層及特徵
134‧‧‧接觸墊
136‧‧‧接觸墊
138‧‧‧導電通孔
140‧‧‧導電層
142‧‧‧導電層
150‧‧‧邊緣
154‧‧‧接觸墊
160‧‧‧導電層/導電條帶
162‧‧‧導電層/導電條帶
164‧‧‧隅角部分
170‧‧‧通孔
180‧‧‧切割線/定界線
182‧‧‧V形溝槽
184a‧‧‧表面
184b‧‧‧表面
200‧‧‧程序
202‧‧‧區塊
204‧‧‧區塊
206‧‧‧區塊
212‧‧‧包覆模製件
306‧‧‧匹配電路
308‧‧‧頻帶選擇開關
310‧‧‧功率放大器
400‧‧‧無線元件
402‧‧‧使用者介面
404‧‧‧記憶體
406‧‧‧功率管理組件
408‧‧‧基頻子系統
410‧‧‧收發器
412‧‧‧雙工器
414‧‧‧天線開關
416‧‧‧天線
圖1展示包括安裝於諸如陶瓷基板之基板上之未經囊封元件的屏蔽型封裝式元件。
圖2展示圖1之封裝式元件之更特定實例，其中覆晶被展示為安裝於諸如低溫共燒陶瓷(LTCC)基板之陶瓷基板上。
圖3展示導電條帶可實施於圖2之陶瓷基板內，且導電條帶可電連接至複數個導電通孔，該等導電通孔又可電連接至形成於陶瓷基板上方之導電層。
圖4展示可被實施為圖1之封裝式元件之更特定實例的組態。
圖5展示可如何實施導電層以便沿著諸如陶瓷基板之基板之一或多個邊緣形成經曝露邊緣的實例。
圖6展示在一些實施例中，陶瓷基板可經組態以經由諸如圖5之實例的導電層之經曝露邊緣而得到電連接能力。
圖7展示陶瓷基板之單元陣列可被單粒化成複數個個別單元的實例。
圖8展示可經實施以促進具有如本文所描述之一或多個特徵之屏蔽型RF模組的程序。
圖9展示具有如本文所描述之一或多個特徵之陶瓷基板可用於具有包覆模製件之屏蔽型RF模組。
圖10描繪包括具有如本文所描述之一或多個特徵之屏蔽型RF模組的無線元件。
本文所提供之標題(若存在)係僅出於方便起見，且未必影響本發明之範疇或意義。
本文中揭示諸如覆晶晶粒之射頻(RF)元件可如何安裝於諸如陶瓷 基板之封裝基板上且如何被屏蔽的各種實例。儘管在覆晶晶粒之上下文中進行描述，但將理解，本發明之一或多個特徵可實施於包括涉及非覆晶晶粒之彼等應用的其他應用中。亦將理解，本發明之一或多個特徵亦可實施於其他類型之非陶瓷基板中。
圖1展示屏蔽型封裝式元件100之實例，其包括安裝於陶瓷基板106上之未經囊封元件104。如本文所描述，此未經囊封元件可為(例如)覆晶。如本文所描述，可在不使用包覆模製件的情況下屏蔽安裝於陶瓷基板106上之此覆晶104，藉此允許(例如)縮減封裝式元件100之高度。舉例而言，可使封裝式元件100之總高度小於為0.65mm之實例規格。
在圖1之實例中，封裝式元件100被展示為包括導電材料保形塗層102，其實質上覆蓋未經囊封元件102，及陶瓷基板106之上部表面108的經曝露部分之一些或全部。此保形塗層可藉由電連接組態112而電連接至陶瓷基板內之接地節點110。本文中更詳細地描述此等電連接可被如何實施之各種實例。
如本文所描述，未經囊封元件102可包括(例如)具有一或多個切換電路之晶粒。亦可利用具有其他類型之RF電路的晶粒。在一些實施例中，此切換晶粒可包括絕緣體上矽(SOI)晶粒。亦可實施其他類型之程序技術。如本文所描述，陶瓷基板106可包括(例如)低溫共燒陶瓷(LTCC)基板、高溫共燒(HTCC)基板，或其他類型之陶瓷材料及/或組態。
圖2展示可為圖1之封裝式元件之更特定實例的實例組態100。在該實例中，諸如SOI切換晶粒之覆晶104被展示為安裝於諸如LTCC基板之陶瓷基板106上。覆晶104於陶瓷基板106上之此安裝可由焊球120之陣列促進。此等焊球120可提供機械安裝功能性，以及在覆晶104與形成於陶瓷基板106之安裝表面116上的接觸墊之間提供電連接。
如圖2所展示，可在覆晶104與陶瓷基板106之間形成底膠122。 此底膠可組態於覆晶104之邊緣附近，以便促進較容易地形成導電材料保形塗層102。舉例而言，底膠122之周邊部分被展示為在覆晶104之垂直邊緣與陶瓷基板106之水平表面116之間提供角形過渡。
在一些實施例中，可藉由(例如)噴塗或各種沈積方法來塗覆導電材料而形成保形塗層102。此導電材料塗層可向其所覆蓋之部分提供屏蔽功能性。可藉由亦在陶瓷基板106之邊緣處或附近提供橫向屏蔽以及在覆晶104下方提供接地平面而極大地增強針對封裝式元件100之總屏蔽效能。
在圖2所展示之實例中，電連接組態112可包括與陶瓷基板106之表面116上的導電塗層102進行電接觸的複數個導電通孔138。如圖3所展示，此等導電通孔可經分佈以形成一周界；且通孔138可經適當地隔開以在該周界內之區域與該周界外部之區域之間提供橫向屏蔽。儘管在此周界之上下文中進行描述，但將理解，本發明之一或多個特徵亦可實施於此橫向屏蔽未形成完整周界的組態中。舉例而言，可提供此等導電通孔，以便在不必圍繞給定區域形成完整周界的情況下促進模組內屏蔽功能性。
在圖2所展示之實例中，電連接組態112可進一步包括實施於陶瓷基板106內以便與導電通孔138進行電接觸之一或多個導電層(例如，140、142)。此等導電層140、142可與亦在陶瓷基板106內之接地平面進行電接觸。
圖3中展示導電層140之實例。此層可包括沿著藉由導電通孔138形成之周界而定位的複數個導電條帶。在所展示實例中，導電條帶140中之每一者被展示為橫向地定位以便與各別通孔138相交。對於圖2之實例導電層142，每一條帶未必需要與各別通孔138完全地重疊，只要其與通孔138形成電接觸即可。通孔138及導電層140、142之其他 組態亦係可能的。
如圖2所展示，陶瓷基板106可包括複數個層及特徵130。此等層及特徵可包括(例如)介電層、被動組件(諸如，電阻器、電容器及電感器)、導體特徵(諸如，通孔及跡線)，及接地平面。在此上下文中，實例導電層140、142可形成於所選擇橫向位置及/或所選擇層處。
亦如圖2所展示，封裝式元件100可包括接觸墊134、136，其允許將封裝式元件100安裝於電路板(例如，電話板)上，且促進封裝式元件100與電路板之間的電連接。
圖4展示可為圖1之封裝式元件之更特定實例的另一實例組態100。在該實例中，諸如SOI切換晶粒之覆晶104被展示為安裝於諸如LTCC基板之陶瓷基板106上。覆晶104於陶瓷基板106上之此安裝可由焊球120之陣列促進。此等焊球120可提供機械安裝功能性，以及在覆晶104與形成於陶瓷基板106之安裝表面116上的接觸墊之間提供電連接。
如圖4所展示，可在覆晶104與陶瓷基板106之間形成底膠122。 此底膠可組態於覆晶104之邊緣附近，以便促進較容易地形成導電材料保形塗層102。舉例而言，底膠122之周邊部分被展示為在覆晶104之垂直邊緣與陶瓷基板106之水平表面116之間提供角形過渡。
在一些實施例中，可藉由(例如)噴塗或各種沈積方法來塗覆導電材料而形成保形塗層102。此導電材料塗層可向其所覆蓋之部分提供屏蔽功能性。可藉由亦在陶瓷基板106之邊緣處提供橫向屏蔽以及在覆晶104下方提供接地平面而極大地增強針對封裝式元件100之總屏蔽效能。
在圖4所展示之實例中，電連接組態112可包括自陶瓷基板106之上部表面116延伸以大體上覆蓋陶瓷基板106之側邊緣的保形導電塗層102。覆蓋陶瓷基板106之側邊緣的此保形導電塗層102被展示為與陶 瓷基板106內之一或多個導電層進行電接觸，且延伸至陶瓷基板106之其各別邊緣。舉例而言，導電層160、162被展示為經實施成使得其邊緣與陶瓷基板106之各別邊緣(150)大體上對準。因此，導電層160、162被展示為與保形導電塗層102進行電接觸。因此，在與接地平面組合(與導電層160、162進行電接觸)的情況下，保形導電塗層102向封裝式元件提供屏蔽功能性。
如圖4所展示，陶瓷基板106可包括複數個層及特徵130。此等層及特徵可包括(例如)介電層、被動組件(諸如，電阻器、電容器及電感器)、導體特徵(諸如，通孔及跡線)，及接地平面。在此上下文中，實例導電層160、162可形成於所選擇橫向位置及/或所選擇層處。在一些實施例中，可藉由(例如)諸如銀之導電材料的圖案化印刷來形成導電層160、162。
亦如圖4所展示，封裝式元件100可包括接觸墊154，其允許將封裝式元件100安裝於電路板(例如，電話板)上，且促進封裝式元件100與電路板之間的電連接。
圖5展示可如何實施諸如實例層160之導電層(亦參看圖4所描述)以便沿著陶瓷基板106之邊緣150形成經曝露邊緣的實例。在該實例中，層160被展示為包括沿著每一邊緣150之導電條帶。此等條帶可沿著以一陣列(例如，在一面板中)而界定的陶瓷基板106之相鄰單元之間的切割線而定位。在將該陣列單粒化成個別單元後，所得邊緣就可形成個別陶瓷基板106之邊緣150。沿著陶瓷基板106之邊緣，導電條帶160之切割部分可形成用於與保形導電塗層102形成電接觸之經曝露導電邊緣。如參看圖4所描述，此保形導電塗層可包括覆蓋陶瓷基板106之邊緣中之一些或全部及導電條帶160之對應經曝露邊緣中之一些或全部的部分。
如圖5所展示，導電條帶160未必需要圍繞陶瓷基板106形成完整 周界。舉例而言，被指示為164之隅角部分可具有經定尺寸為足夠小以提供屏蔽功能性之間隙。在圖5中，複數個通孔170可經組態以提供各種電連接及/或熱轉移功能性。
圖6展示在一些實施例中，陶瓷基板106可經組態以得到具有如本文所描述之一或多個特徵之電連接112。如所展示，此陶瓷基板可包括如本文所描述之複數個層130及/或特徵。亦如本文所描述，此陶瓷基板可包括在陶瓷基板106內且經定位為至少部分地曝露於邊緣150上之一或多個導電特徵160。
在圖6之實例中，陶瓷基板106被描繪為具有大體上90度切口以界定垂直邊緣150。在一些實施例中，單粒化操作可沿著此等邊緣得到非垂直表面。舉例而言，圖7展示在一些實施例中，陶瓷基板的個別單元(例如，106a、106b)之陣列可沿著切割線180被處理及單粒化。此單粒化組態可在基板材料相對軟時之燃燒程序之前由(例如)沿著定界線180而形成之V形溝槽182促進。在完成燃燒程序後，就可藉由(例如)沿著定界線180折斷個別單元來單粒化所得經硬化陶瓷基板。此折斷操作可由該V形溝槽促進。
在此等經單粒化陶瓷基板106a、106b中，沿著V形溝槽182之表面184a、184b的導電層160中之經曝露部分可與其各別保形導電塗層形成電接觸。
圖8展示可經實施以製造封裝式射頻(RF)模組之程序200。在區塊202中，可形成或提供具有導電層及接地平面之陶瓷基板。導電層及接地平面可電連接。在區塊204中，可將晶粒安裝於陶瓷基板上。在區塊206中，可將保形導電塗層形成於晶粒上方且形成為與導電層進行電接觸，以藉此向晶粒提供RF屏蔽。
在一些實施例中，在圖8之程序200的至少一些步驟期間，陶瓷基板可呈面板之形式。此面板可包括以一堆疊而配置之複數個陶瓷 層，且該面板可包括由線柵格界定之單元陣列。將理解，此線柵格未必實體上存在於該面板上，且可被實施為(例如)單粒化指令及/或資料。沿著此線柵格之單粒化可引起將該等單元分離成複數個個別單元。在可將保形導電塗層塗覆至陶瓷基板之側壁的圖4至圖7之實例之上下文中，可在單粒化步驟之後執行此塗佈步驟。在一些實施例中，可在單粒化步驟之前對該等單元中之每一者執行晶粒之安裝。
在本文參看圖4所描述之實例中，安裝於陶瓷基板106上之晶粒被描繪為未經囊封覆晶104。如本文所描述，此陶瓷基板可促進形成於該未經囊封覆晶上方之保形導電塗層的接地。
圖9展示在一些實施例中，具有如本文所描述之一或多個特徵之陶瓷基板106亦可用於封裝應用中，該等封裝應用利用安裝於陶瓷基板106上之一或多個組件的囊封。舉例而言，屏蔽型封裝式元件100可包括經組態以提供RF功能性之晶粒210，晶粒210安裝於陶瓷基板106上，其可以與圖4之實例中類似的方式進行組態。晶粒210被展示為由包覆模製件212囊封，且保形導電塗層102被展示為大體上覆蓋包覆模製件212之上部表面及側壁以及陶瓷基板106之側壁。如參看圖4所描述，導電層160、162可經組態以在保形導電塗層102與陶瓷基板106內之接地平面之間提供電連接。
在一些實施中，具有本文所描述之一或多個特徵之元件可包括於諸如無線元件之RF元件中。在一些實施例中，此無線元件可包括(例如)蜂巢式電話、智慧型電話、具有或不具有電話功能性之手持型無線元件、無線平板電腦等等。
圖10描繪具有本文所描述之一或多個有利特徵之實例無線元件400。在具有如本文所描述之一或多個特徵之模組的上下文中，此模組可經實施用於數種不同應用。舉例而言，如由虛線方框100大體上所描繪，屏蔽型封裝式模組可被實施為天線開關模組。將理解，此模 組可包括比圖10所描繪之組件更多或更少的組件。
功率放大器(PA)310可自收發器410接收其各別RF信號，收發器410可以已知方式進行組態及操作以產生待放大及傳輸之RF信號，且處理經接收信號。收發器410被展示為與基頻子系統408互動，基頻子系統408經組態以在適合於使用者之資料及/或語音信號與適合於收發器410之RF信號之間提供轉換。收發器410亦被展示為連接至經組態以管理用於無線元件之操作之功率的功率管理組件406。此功率管理亦可控制基頻子系統408之操作。
基頻子系統408被展示為連接至使用者介面402，以促進提供至使用者或自使用者接收之語音及/或資料之各種輸入及輸出。基頻子系統408亦可連接至經組態以儲存資料及/或指令之記憶體404，以促進無線元件之操作及/或向使用者提供資訊儲存。
在實例無線元件400中，PA 310之輸出被展示為匹配(經由各別匹配電路306)且經由頻帶選擇開關308、該等輸出之各別雙工器412及天線開關414而路由至天線416。在一些實施例中，每一雙工器412可允許使用共同天線(例如，416)來傳輸及接收待同步地執行之操作。在圖10中，經接收信號經展示為路由至可包括(例如)低雜訊放大器(LNA)之「Rx」路徑(未圖示)。
數種其他無線元件組態可利用本文所描述之一或多個特徵。舉例而言，無線元件無需為多頻帶元件。在另一實例中，無線元件可包括諸如分集天線之額外天線，以及諸如Wi-Fi、藍芽及GPS之額外連接性特徵。
除非上下文另有明確要求，否則貫穿【實施方式】及申請專利範圍，詞語「包含」及其類似者應被認作包括性意義，此與排他性或詳盡性意義相反；亦即，意義為「包括但不限於」。如本文大體上所使用，詞語「耦接」係指兩個或兩個以上器件可直接地連接，或經由 一或多個中間器件而連接。另外，當用於本申請案中時，詞語「本文中」、「上文」、「下文」及類似匯入詞語應係指本申請案整體而非本申請案之任何特定部分。在上下文准許的情況下，使用單數或複數數目之以上【實施方式】中的詞語亦可分別包括複數或單數數目。詞語「或」參考兩個或兩個以上項目之清單，彼詞語涵蓋該詞語之所有以下解譯：該清單中之任一項目、該清單中之所有項目，及該清單中之項目的任何組合。
本發明之實施例之以上詳細描述不意欲為詳盡的或將本發明限於上文所揭示之精確形式。熟習相關技術者將認識到，雖然上文出於說明性目的而描述本發明之特定實施例及其實例，但在本發明之範疇內可作出各種等效修改。舉例而言，雖然以給定次序呈現程序或區塊，但替代性實施例可執行具有呈不同次序之步驟的常式或使用具有呈不同次序之區塊的系統，且可刪除、移動、添加、細分、組合及/或修改一些程序或區塊。此等程序或區塊中之每一者可以多種不同方式予以實施。又，雖然有時將程序或區塊展示為連續地執行，但可改為並行地執行此等程序或區塊，或可在不同時間執行此等程序或區塊。
本文所提供的本發明之教示可應用於其他系統，未必為上文所描述之系統。可組合上文所描述之各種實施例的器件及動作以提供另外實施例。
雖然已描述本發明之一些實施例，但此等實施例係僅作為實例而呈現，且不意欲限制本發明之範疇。實際上，本文所描述之新穎方法及系統可以多種其他形式予以體現；此外，在不脫離本發明之精神的情況下，可對本文所描述之方法及系統的形式進行各種省略、取代及改變。隨附申請專利範圍及其等效者意欲涵蓋將屬於本發明之範疇及精神的此等形式或修改。
100‧‧‧封裝式元件
102‧‧‧保形導電塗層
104‧‧‧未經囊封元件/覆晶
106‧‧‧陶瓷基板
112‧‧‧電連接組態
116‧‧‧表面
120‧‧‧焊球
122‧‧‧底膠
130‧‧‧層及特徵
150‧‧‧邊緣
154‧‧‧接觸墊
160‧‧‧導電層/導電條帶
162‧‧‧導電層/導電條帶

Claims (20)

  1. 一種封裝式電子元件，其包含：經組態以收納一或多個組件之一陶瓷基板，該陶瓷基板包括與一接地平面進行電接觸之一導電層；具有一積體電路之一晶粒，該晶粒安裝於該陶瓷基板之一表面上；實施於該晶粒上方以提供屏蔽功能性之一保形導電塗層；及在該保形導電塗層與該導電層之間的一電連接。
  2. 如請求項1之封裝式電子元件，其中該保形導電塗層實質上直接地實施於該晶粒上。
  3. 如請求項2之封裝式電子元件，其中該晶粒經組態為一覆晶元件。
  4. 如請求項3之封裝式電子元件，其進一步包含實施於該覆晶元件與該陶瓷基板之間的一底膠。
  5. 如請求項4之封裝式電子元件，其中該底膠包括經組態以在該覆晶元件之側壁與該陶瓷基板之該表面之間提供一角形過渡的一邊緣剖面。
  6. 如請求項5之封裝式電子元件，其中該底膠之該角形過渡剖面經組態以促進在該覆晶元件與該陶瓷基板之間的該保形導電塗層之改良式覆蓋。
  7. 如請求項2之封裝式電子元件，其中該積體電路包括一射頻(RF)切換電路。
  8. 如請求項7之封裝式電子元件，其中該晶粒為一絕緣體上矽(SOI)晶粒。
  9. 如請求項2之封裝式電子元件，其中該電連接包括在該陶瓷基板 之該表面上的該保形導電塗層之一部分，該部分延伸至該陶瓷基板之側邊緣。
  10. 如請求項9之封裝式電子元件，其中該導電層包括沿著該陶瓷基板之該對應側邊緣的一邊緣，使得該導電層之該邊緣與該保形導電塗層進行電接觸。
  11. 如請求項10之封裝式電子元件，其中該導電層包括沿著該陶瓷基板之該對應側邊緣的一導電條帶。
  12. 如請求項11之封裝式電子元件，其中該導電條帶包括充分地曝露於該陶瓷基板之該對應側邊緣上以促進該導電條帶與該保形導電塗層之間的該電接觸的一邊緣。
  13. 如請求項12之封裝式電子元件，其中該導電層包括該等導電條帶中之複數個導電條帶，該複數個導電條帶經配置成使得該陶瓷基板之每一邊緣包括與該保形導電塗層進行電接觸的該導電條帶之該對應經曝露邊緣。
  14. 如請求項1之封裝式電子元件，其中該保形導電塗層包括藉由沈積而形成之一金屬漆層或一導電層。
  15. 如請求項1之封裝式電子元件，其中該陶瓷基板包括一低溫共燒陶瓷(LTCC)基板。
  16. 如請求項1之封裝式電子元件，其進一步包含實施於該陶瓷基板之一底面上的複數個接觸墊，該等接觸墊經組態以允許將該封裝式電子元件安裝於一電路板上。
  17. 一種用於製造一封裝式射頻(RF)模組之方法，該方法包含：形成或提供經組態以收納一或多個組件之一陶瓷基板，該陶瓷基板包括與一接地平面進行電接觸之一導電層；將一晶粒安裝於該陶瓷基板之一表面上，該晶粒包括一積體電路；及 將一保形導電塗層形成於該晶粒上方且形成為與該導電層進行電接觸，以藉此向該晶粒提供屏蔽功能性。
  18. 如請求項17之方法，其中該陶瓷基板包括以具有由一線柵格界定之一單元陣列之一堆疊而配置的複數個陶瓷層，沿著該線柵格之一單粒化程序引起將該等單元分離成複數個個別單元。
  19. 如請求項18之方法，其進一步包含在該保形導電塗層之該形成之前單粒化該單元陣列。
  20. 一種無線元件，其包含：一收發器，其經組態以產生一射頻(RF)信號；一RF模組，其經組態以處理該RF信號，該RF模組包括經組態以收納一或多個組件之一陶瓷基板，該陶瓷基板包括與一接地平面進行電接觸之一導電層，該RF模組進一步包括具有一積體電路之一晶粒，該晶粒安裝於該陶瓷基板之一表面上，該RF模組進一步包括實施於該晶粒上方以提供屏蔽功能性之一保形導電塗層，該RF模組進一步包括在該保形導電塗層與該導電層之間的一電連接；及一天線，其與該RF模組通信，該天線經組態以促進該經處理RF信號之傳輸。
TW103138412A 2013-11-05 2014-11-05 與陶瓷基板上之射頻元件之封裝相關的元件及方法 TWI652789B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201361900394P 2013-11-05 2013-11-05
US61/900,394 2013-11-05
US14/528,447 US9564937B2 (en) 2013-11-05 2014-10-30 Devices and methods related to packaging of radio-frequency devices on ceramic substrates
US14/528,447 2014-10-30

Publications (2)

Publication Number Publication Date
TW201530731A true TW201530731A (zh) 2015-08-01
TWI652789B TWI652789B (zh) 2019-03-01

Family

ID=53007383

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103138412A TWI652789B (zh) 2013-11-05 2014-11-05 與陶瓷基板上之射頻元件之封裝相關的元件及方法

Country Status (6)

Country Link
US (2) US9564937B2 (zh)
JP (3) JP6537807B2 (zh)
KR (1) KR102371332B1 (zh)
CN (1) CN104617053B (zh)
HK (1) HK1206148A1 (zh)
TW (1) TWI652789B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI632662B (zh) * 2016-04-22 2018-08-11 矽品精密工業股份有限公司 電子封裝件及其製法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3170228B1 (en) * 2014-07-16 2019-05-01 Siemens Aktiengesellschaft Subsea electrical connector component and method of manufacturing thereof
US10729001B2 (en) 2014-08-31 2020-07-28 Skyworks Solutions, Inc. Devices and methods related to metallization of ceramic substrates for shielding applications
JPWO2016080333A1 (ja) * 2014-11-21 2017-08-24 株式会社村田製作所 モジュール
TWI656543B (zh) * 2015-10-16 2019-04-11 日商村田製作所股份有限公司 Electronic parts
WO2017179325A1 (ja) 2016-04-11 2017-10-19 株式会社村田製作所 高周波部品
JP2017200183A (ja) * 2016-04-29 2017-11-02 スカイワークス ソリューションズ, インコーポレイテッドSkyworks Solutions, Inc. 遮蔽されたダイバーシティ受信モジュール
WO2018067578A1 (en) 2016-10-04 2018-04-12 Skyworks Solutions, Inc. Dual-sided radio-frequency package with overmold structure
CN108022886A (zh) * 2017-11-30 2018-05-11 深圳华远微电科技有限公司 一种倒装芯片式滤波器的封装结构
US11503704B2 (en) * 2019-12-30 2022-11-15 General Electric Company Systems and methods for hybrid glass and organic packaging for radio frequency electronics
US11804435B2 (en) 2020-01-03 2023-10-31 Skyworks Solutions, Inc. Semiconductor-on-insulator transistor layout for radio frequency power amplifiers
US11291106B2 (en) * 2020-01-29 2022-03-29 Dell Products L.P. System and method for enhanced cooling
US11342277B2 (en) * 2020-06-10 2022-05-24 Micron Technology, Inc. Semiconductor device assemblies with conductive underfill dams for grounding EMI shields and methods for making the same
CN113327899A (zh) * 2021-04-22 2021-08-31 成都芯源系统有限公司 倒装芯片封装单元及封装方法

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213755A (ja) * 1995-01-31 1996-08-20 Kyocera Corp コンデンサ内蔵型積層セラミック回路基板及びその製造方法
US20010033478A1 (en) * 2000-04-21 2001-10-25 Shielding For Electronics, Inc. EMI and RFI shielding for printed circuit boards
JP2002026178A (ja) * 2000-07-04 2002-01-25 Hitachi Ltd 半導体装置及びその製造方法並びに電子装置
JP3724450B2 (ja) 2002-04-23 2005-12-07 株式会社村田製作所 無線通信用高周波回路およびそれを備えた通信機
JP4178880B2 (ja) * 2002-08-29 2008-11-12 松下電器産業株式会社 モジュール部品
US7167688B2 (en) * 2003-07-30 2007-01-23 Chi Mei Communication Systems, Inc. RF transceiver module formed in multi-layered ceramic
JP2006210629A (ja) 2005-01-28 2006-08-10 Matsushita Electric Ind Co Ltd 半導体装置
US7342303B1 (en) * 2006-02-28 2008-03-11 Amkor Technology, Inc. Semiconductor device having RF shielding and method therefor
JP2007306172A (ja) * 2006-05-10 2007-11-22 Tdk Corp バンドパスフィルタ素子および高周波モジュール
TWI332275B (en) * 2006-07-04 2010-10-21 Advanced Semiconductor Eng Semiconductor package having electromagnetic interference shielding and fabricating method thereof
US7701040B2 (en) * 2007-09-24 2010-04-20 Stats Chippac, Ltd. Semiconductor package and method of reducing electromagnetic interference between devices
US7906371B2 (en) * 2008-05-28 2011-03-15 Stats Chippac, Ltd. Semiconductor device and method of forming holes in substrate to interconnect top shield and ground shield
TW201013881A (en) 2008-09-10 2010-04-01 Renesas Tech Corp Semiconductor device and method for manufacturing same
JP5402482B2 (ja) * 2009-10-01 2014-01-29 パナソニック株式会社 モジュールとモジュールの製造方法
CN102054821B (zh) * 2009-10-30 2013-09-11 日月光半导体制造股份有限公司 具有内屏蔽体的封装结构及其制造方法
US8378466B2 (en) * 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
JP2011193191A (ja) * 2010-03-15 2011-09-29 Renesas Electronics Corp 半導体集積回路およびそれを内蔵した高周波モジュール
KR101171512B1 (ko) * 2010-06-08 2012-08-06 삼성전기주식회사 반도체 패키지의 제조 방법
KR20120053332A (ko) * 2010-11-17 2012-05-25 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
CN102610595B (zh) * 2011-01-24 2015-02-18 国民技术股份有限公司 射频功率放大器及其封装方法
TWI438885B (zh) * 2011-03-18 2014-05-21 矽品精密工業股份有限公司 半導體封裝件及其製法
US9179538B2 (en) 2011-06-09 2015-11-03 Apple Inc. Electromagnetic shielding structures for selectively shielding components on a substrate
US9190340B2 (en) * 2011-06-17 2015-11-17 Stats Chippac, Ltd. Semiconductor device and method of forming RF FEM and RF transceiver in semiconductor package
WO2013035819A1 (ja) * 2011-09-08 2013-03-14 株式会社村田製作所 電子部品モジュール及び該電子部品モジュールの製造方法
US8637963B2 (en) * 2011-10-05 2014-01-28 Sandisk Technologies Inc. Radiation-shielded semiconductor device
JP2013207213A (ja) * 2012-03-29 2013-10-07 Tdk Corp 電子部品モジュール及びその製造方法
TW201351599A (zh) * 2012-06-04 2013-12-16 矽品精密工業股份有限公司 半導體封裝件及其製法
CN202888168U (zh) * 2012-09-05 2013-04-17 欣兴电子股份有限公司 电子元件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI632662B (zh) * 2016-04-22 2018-08-11 矽品精密工業股份有限公司 電子封裝件及其製法

Also Published As

Publication number Publication date
US20170149466A1 (en) 2017-05-25
JP7214574B2 (ja) 2023-01-30
CN104617053B (zh) 2020-09-11
KR102371332B1 (ko) 2022-03-04
JP7242938B2 (ja) 2023-03-20
US20150126134A1 (en) 2015-05-07
US10771101B2 (en) 2020-09-08
JP2022109908A (ja) 2022-07-28
TWI652789B (zh) 2019-03-01
CN104617053A (zh) 2015-05-13
JP2019176172A (ja) 2019-10-10
HK1206148A1 (zh) 2015-12-31
JP2015091135A (ja) 2015-05-11
KR20150051924A (ko) 2015-05-13
US9564937B2 (en) 2017-02-07
JP6537807B2 (ja) 2019-07-03

Similar Documents

Publication Publication Date Title
TWI652789B (zh) 與陶瓷基板上之射頻元件之封裝相關的元件及方法
US11127690B2 (en) Dual-sided radio-frequency package with overmold structure
TWI645773B (zh) 用於提供模組內射頻隔離之系統及方法
TWI641297B (zh) 射頻(rf)模組
JP6469572B2 (ja) アンテナ一体型無線モジュールおよびこのモジュールの製造方法
US11277901B2 (en) Methods related to metallization of ceramic substrates for shielding applications
US20180076148A1 (en) Through-mold features for shielding applications
TWI733209B (zh) 具較小面積之經屏蔽射頻模組
US20200161222A1 (en) Methods related to through-mold openings for dual-sided packaged modules with ball grid arrays
US20220254730A1 (en) Signal isolation for module with ball grid array