TW202213652A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

Info

Publication number
TW202213652A
TW202213652A TW109132583A TW109132583A TW202213652A TW 202213652 A TW202213652 A TW 202213652A TW 109132583 A TW109132583 A TW 109132583A TW 109132583 A TW109132583 A TW 109132583A TW 202213652 A TW202213652 A TW 202213652A
Authority
TW
Taiwan
Prior art keywords
carrier
conductive
electronic
layer
package
Prior art date
Application number
TW109132583A
Other languages
English (en)
Other versions
TWI734616B (zh
Inventor
邱志賢
張克維
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW109132583A priority Critical patent/TWI734616B/zh
Priority to CN202011126623.5A priority patent/CN114256213A/zh
Priority to US17/159,527 priority patent/US11587892B2/en
Application granted granted Critical
Publication of TWI734616B publication Critical patent/TWI734616B/zh
Publication of TW202213652A publication Critical patent/TW202213652A/zh
Priority to US18/097,847 priority patent/US20230154872A1/en
Priority to US18/097,965 priority patent/US11984412B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F17/0033—Printed inductances with the coil helically wound around a magnetic core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

一種電子封裝件，係於承載件與電子元件之間配置至少一導磁件，且該電子元件具有第一導電層，而該承載件具有第二導電層，以令該導磁件位於該第一導電層與第二導電層之間，並於該電子元件與該承載件之間配置複數電性連接該第一導電層與第二導電層之導電凸塊，以環繞該導磁件而產生磁通量。

Description

電子封裝件及其製法
本發明係有關一種半導體裝置，尤指一種具導磁件(ferromagnetic material)之電子封裝件及其製法。
一般半導體應用裝置，例如通訊或高頻半導體裝置中，常需要將電阻器、電感器、電容器及振盪器(oscillator)等多數射頻(radio frequency)被動元件電性連接至所封裝之半導體晶片，俾使該半導體晶片具有特定之電流特性或發出訊號。
以球柵陣列(Ball Grid Array，簡稱BGA)半導體裝置為例，多數被動元件雖安置於基板表面，然為了避免該等被動元件阻礙半導體晶片與多數銲墊間之電性連結及配置，傳統上多將該等被動元件安置於基板角端位置或半導體晶片接置區域以外之基板額外佈局面積上。
然而，限定被動元件之位置將限制基板線路佈局(Routability)之靈活性；同時此舉需考量銲墊位置會導致該等被動元件佈設數量受到侷限，不利半導體裝置高度集積化之發展趨勢；甚者，被動元件佈設數量隨著半導體封裝件高性能之要求而相對地遽增，如採習知方法該基板表面必須同時容納多數半導體 晶片以及較多被動元件而造成封裝基板面積加大，進而迫使封裝件體積增大，亦不符合半導體封裝件輕薄短小之發展潮流。
基於上述問題，業界遂將該多數被動元件製作成集總元件(如晶片型電感)整合至半導體晶片與銲墊區域間之基板區域上。如圖1所示之半導體封裝件1，其於一具有線路層100之封裝基板10上設置一半導體晶片11及複數電感元件12，且該半導體晶片11藉由複數銲線110電性連接該線路層100之銲墊101。
惟，該電感元件12係為晶片型，故其所需體積大，特別是電源電路所需之電感元件12，且該電感元件12距離該半導體晶片11過遠，致使寄生(parasitic)效應隨著該電感元件12遠離該半導體晶片11而增加，因而造成該半導體封裝件1之電性效能不佳。
再者，該電感元件12形成於該封裝基板10之表面上，將佔據該封裝基板10之大量佈設空間，因而容易造成該半導體封裝件1難以符合微小化的需求。
另外，業界亦有以線圈型電感12’取代該晶片型電感元件12，如圖1’所示之半導體封裝件1’，但該線圈型電感12’僅設在該封裝基板10上，因而該線圈型電感12’所產生之電感模擬值有限，致使該線圈型電感12’之電感值過小而難以符合需求。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：承載件；電子元件，係設於該承載件上；至少一導磁件，係設於該承載件與該電子元件之間；以及導體結構，係包含配置於該電子元件上之第一導電層、配置於該承載件上之第二導電層、及複數設於該電子元件與該承載件之間的導電凸塊，以令該導磁件位於該第一導電層與第二導電層之間，且該複數導電凸塊電性連接該第一導電層與第二導電層。
本發明復提供一種電子封裝件之製法，係包括：提供一具有第一導電層之電子元件及一具有第二導電層之承載件；以及將該電子元件藉由複數導電凸塊設於該承載件上，且令該電子元件與該承載件之間夾置有至少一導磁件，其中，該複數導電凸塊電性連接該第一導電層與第二導電層，且該導磁件位於該第一導電層與第二導電層之間。
前述之電子封裝件及其製法中，該承載件係為無核心層之線路結構。
前述之電子封裝件及其製法中，該承載件係具有一供容置該導磁件之凹部。例如，該導體結構復包含複數嵌埋於該承載件中之導電柱，且該複數導電柱係位於該凹部之周圍並電性連接該導電凸塊與該第二導電層。
前述之電子封裝件及其製法中，該導磁件係結合至該承載件上。
前述之電子封裝件及其製法中，該導磁件係結合至該電子元件上。例如，該導磁件係嵌埋於該電子元件中。
前述之電子封裝件及其製法中，該承載件與該電子元件之間係配置有複數該導磁件。
前述之電子封裝件及其製法中，該承載件係為封裝基板，其具有核心層及結合於該核心層相對兩側之線路結構。
前述之電子封裝件及其製法中，該電子元件係為主動元件或封裝結構。
由上可知，本發明之電子封裝件及其製法中，主要藉由將該導體結構之第一導電層與第二導電層分別配置於該承載件與該電子元件上，而易於環繞該導磁件，使該導磁件與該導體結構產生之磁通量增加，以增加電感量，進而增加電感值。
再者，藉由該導磁件之設計，可增加單一線圈之電感值，故相較於習知無導磁件之線圈型電感，本發明可用較少的線圈數量達到相同的電感值，因而能微小化電感之體積。
1,1’:半導體封裝件
10:封裝基板
100,200:線路層
101:銲墊
11,61:半導體晶片
110:銲線
12:電感元件
12’:線圈型電感
2,3,3’,4,4’,5,6:電子封裝件
2a,4a:電感
20,30,50:承載件
20a:第一側
20b:第二側
21,21’,6a:電子元件
21a:半導體基體
21b:介電體
210:佈線層
211,63:接點
22,32,42:導磁件
22a:第一表面
22b:第二表面
22c:側面
23:導體結構
23a:第一導電層
23b:第二導電層
230:導電凸塊
231:導電柱
24:封裝層
25:導電元件
500:核心層
501:線路結構
60:包覆層
61a:作用面
61b:非作用面
610:電極墊
62:線路部
620:介電層
621:線路重佈層
S:凹部
圖1係為習知半導體封裝件之剖面示意圖。
圖1’係為習知另一半導體封裝件之剖面示意圖。
圖2A至圖2D係為本發明之電子封裝件之第一實施例之製法之剖視示意圖。
圖2C’係為圖2C之局部上視示意圖。
圖3A係為本發明之電子封裝件之第二實施例之剖視示意圖。
圖3B係為本發明之電子封裝件之第三實施例之剖視示意圖。
圖4A係為係為本發明之電子封裝件之第四實施例之剖視示意圖。
圖4B係為圖4A之另一態樣之剖視示意圖。
圖5係為本發明之電子封裝件之第五實施例之剖視示意圖。
圖6係為本發明之電子封裝件之第六實施例之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2D係為本發明之電子封裝件2之第一實施例之製法的剖面示意圖。
如圖2A所示，提供一電子元件21，其為如半導體晶片之主動元件，係包含一半導體基體21a及一形成於該半導體基體21a上之介電體21b，該半導體基體21a中具有積體電路，且該介電體21b中設有至少一佈線層210及一第一導電層23a。
於本實施例中，該佈線層210與該第一導電層23a均為銅材，且該佈線層210係部分外露於該介電體21b以作為接點211，並使該第一導電層23a電性連接該接點211。
如圖2B所示，提供一具有凹部S之承載件20，並於該凹部S中容置一導磁件22。
如圖2B至圖2C所示，將該電子元件21對應該導磁件22設於該承載件20上，使該導磁件22位於該承載件20與該電子元件21之間。
於本實施例中，該承載件20係為無核心層(coreless)之線路結構，其係於介電材上形成至少一線路層200及一第二導電層23b，如扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)，且介電材係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等。例如，該承載件20係具有相對之第一側20a與第二側20b，且該電子元件21與該導磁件22係設於該承載件20之第一側20a上。應可理解地，該承載件20之第一側20a上亦可配置其它電子元件21’。
再者，該承載件20之第一側20a係形成有該凹部S，且該電子元件21係對應遮蓋於該凹部S之上方。例如，該電子元件21以其接點211藉由複數導電凸塊230以覆晶方式電性連接該承載件20之線路層200，且該第二導電層23b係配置於該凹部S之底側，並於該承載件20中對應該凹部S之側壁周圍形成複數電性連接該第二導電層23b與該導電凸塊230之導電柱231。
又，該導磁件22係具有高磁導率(permeability)之特性，如鐵素體(ferrite)，其具有相對之第一表面22a與第二表面22b、及鄰接該第一表面22a與第二表面22b之側面22c，以於該導磁件22上圈繞一導體結構23。例如，該導體結構23係包含第一導電層23a、第二導電層23b、導電柱231與導電凸塊230，以令該導體結構23呈迴狀線圈，使該導磁件22位於該迴狀線圈中。具體地，如圖2C’所示，該第一導電層23a與第二導電層23b係為直線狀導電跡線，其佈設係對應該導磁件22之第一表面22a及第二表面22b，而該些導電柱221與導電凸塊230之佈設對應該導磁件22之側面22c，使該迴狀線圈之路徑係依序經過該導磁件22之第一表面22a、側面22c、第二表面22b及側面22c。
另外，該導體結構23係與該導磁件22產生磁通量，以令該導體結構23與該導磁件22構成電感2a。
如圖2D所示，形成一封裝層24於該承載件20之第一側20a上，以包覆該電子元件21,21’、該導磁件22與該導電凸塊230，使該導磁件22固定於該凹部S中。
於本實施例中，該封裝層24之形成材質係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝層(molding compound)。例如，該封裝層24之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成於該承載件20之第一側20a上。
再者，該承載件20之第二側20b可依需求形成複數如銲球之導電元件25。
又，若該製法中之承載件20呈現整版面型式，可依需求進行切單製程。
因此，本發明之製法中，係藉由將第一導電層23a與第二導電層23b分別配置於該承載件20與該電子元件21上，並於承載件20與電子元件21之間配置至少一導磁件22，以令該導磁件22位於該第一導電層23a與第二導電層23b之間，並於該電子元件21與該承載件20之間配置複數電性連接該第一導電層23a與第二導電層23b之導電凸塊230，以環繞該導磁件22，使該導磁件22與導體結構23產生磁通量。
圖3A係為本發明之電子封裝件3之第二實施例之剖面示意圖。本實施例與第一實施例之差異在於導磁件22之位置與承載件30之態樣，故僅說明相異處，而其它相同處不再贅述。
如圖3A所示，該承載件30之第一側20a未形成有凹部，以令該導磁件22設於該承載件30之第一側20a之表面上。
圖3B係為本發明之電子封裝件3’之第三實施例之剖面示意圖。本實施例與第二實施例之差異在於導磁件32之位置，故僅說明相異處，而其它相同處不再贅述。
如圖3B所示，該導磁件32設於該電子元件21之介電體21b之表面上。
圖4A係為本發明之電子封裝件4之第四實施例之剖面示意圖。本實施例與第三實施例之差異在於導磁件42之位置，故僅說明相異處，而其它相同處不再贅述。
如圖4A所示，該導磁件42係嵌埋於該電子元件21之介電體21b中。於本實施例中，係於製作該電子元件21時，一併將該導磁件42嵌埋於該介電體21b中。
再者，亦可於第一實施例中配置一具有該導磁件42之電子元件21，如圖4B所示之電子封裝件4’，以於該承載件20與該電子元件21之間配置有複數導磁件22,42，以增加該電感4a之磁通量。
圖5係為本發明之電子封裝件5之第五實施例之剖面示意圖。本實施例與上述各實施例之差異在於承載件50之態樣，故僅說明相異處，而其它相同處不再贅述。
如圖5所示，基於第二實施例，該承載件50係為封裝基板(substrate)，其具有一核心層500及結合於該核心層500相對兩側之線路結構501，其係於介電材上形成至少一線路層及該第二導電層23b，如扇出(fan out)型重佈線路層(RDL)，且介電材係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)等。
圖6係為本發明之電子封裝件6之第六實施例之剖面示意圖。本實施例與上述各實施例之差異在於電子元件6a之態樣，故僅說明相異處，而其它相同處不再贅述。
如圖6所示，基於第一實施例，該電子元件6a係為封裝結構，如晶圓級封裝(Wafer Level Package，簡稱WLP)結構或晶片級封裝(Chip Scale Package，簡稱CSP)結構，其係以包覆層60包覆至少一半導體晶片61，再於該包覆層60上形成一電性連接該半導體晶片61之線路部62。
於本實施例中，該包覆層60之形成材質係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝層(molding compound)。例如，該包覆層60之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成。應可理解地，該包覆層60與該封裝層24可為相同材質或不同材質。
再者，該半導體晶片61係具有相對之作用面61a與非作用面61b，且該作用面61a具有複數電極墊610。
又，該線路部62係包含至少一介電層620與至少一設於該介電層620上並電性連接該電極墊610之線路重佈層(Redistribution layer，簡稱RDL)621，且該第一導電層23a係設於該介電層620中且電性連接該線路重佈層621。例如，形成該線路重佈層621之材質係為銅，且形成該介電層620之材質係如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材。具體地，該電子元件6a之線路重佈層621係部分外露於該介電層620以作為接點63，以令該些接點63藉由該些導電凸塊230電性連接該承載件20之線路層200。
另外，係於製作該線路部62時，一併將該導磁件42嵌埋於該介電層620中。
本發明之電子封裝件2,3,3’,4,4’,5,6藉由該導體結構23環繞該導磁件22,32,42，使磁場將趨向於集中在低磁阻的鐵磁路徑(ferromagnetic path)，即該導磁件22,32,42，因而得以增加磁通量，進而增加電感量，使本發明之電感值可大幅提高。
再者，本發明藉由該導磁件22,32,42之設計，可增加單一線圈之電感值，故相較於習知無磁鐵之線圈型電感，本發明可用較少的線圈數量達到相同的電感值。例如，習知線圈型電感需三圈線圈才能達到17nH，而本發明之迴狀線圈僅需一圈即可達到17nH。
又，本發明之電感2a,4a係由該導體結構23與該導磁件22,32,42所構成，故能依需求微小化電感之體積。例如，欲達到相同的電感值，本發明之迴狀線圈之圈數少於習知線圈型電感之圈數圈，因而減少電感之體積，且該導磁件22,32,42內部可無需設計線路(即純導磁材質)，因而其體積可依需求減少，故本發明之電感符合微小化之需求。
因此，相較於習知技術，本發明之電子封裝件2,3,3’,4,4’,5,6能以更小的佈設範圍製作電感2a,4a並產生更大的電感值。
本發明復提供一種電子封裝件2,3,3’,4,4’,5,6，係包括：一承載件20,30,50、一電子元件21,6a、至少一導磁件22,32,42、以及一導體結構23。
所述之承載件20,30,50係具有相對之第一側20a與第二側20b。
所述之電子元件21,6a係設於該承載件20,30,50上。
所述之導磁件22,32,42係設於該承載件20,30,50與該電子元件21,6a之間。
所述之導體結構23係包含一配置於該電子元件21,6a上之第一導電層23a、一配置於該承載件20,30,50上之第二導電層23b、及複數設於該電子元件21,6a與該承載件20,30,50之間的導電凸塊230，以令該導磁件22,32,42位於該第 一導電層23a與第二導電層23a,23b之間，且該複數導電凸塊230電性連接該第一導電層23a與第二導電層23b。
於一實施例中，該承載件20,30係為無核心層之線路結構。
於一實施例中，該承載件20係具有一供容置該導磁件22之凹部S。例如，該導體結構23復包含複數嵌埋於該承載件20中之導電柱231，且該複數導電柱231係位於該凹部S之側壁周圍並電性連接該導電凸塊230與該第二導電層23b。
於一實施例中，該導磁件22係結合至該承載件30之第一側20a之表面上。
於一實施例中，該導磁件32,42係結合至該電子元件21上。進一步，該導磁件42係嵌埋於該電子元件21中。
於一實施例中，該承載件20與該電子元件21之間係配置有複數該導磁件22,42。
於一實施例中，該承載件50係為封裝基板，其具有一核心層500及結合於該核心層500相對兩側之線路結構501。
於一實施例中，該電子元件21係為主動元件。
於一實施例中，該電子元件6a係為封裝結構。
綜上所述，本發明之電子封裝件及其製法，係藉由將該導體結構之第一導電層與第二導電層分別配置於該承載件與該電子元件上，而易於環繞該導磁件，使該導磁件與該導體結構產生之磁通量增加，以增加電感量，進而增加電感值。再者，藉由該導磁件之設計，可增加單一線圈之電感值，故相較於習知無導磁件之線圈型電感，本發明可用較少的線圈數量達到相同的電感值，因而能微小化電感之體積。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
2a:電感
20:承載件
20a:第一側
20b:第二側
21,21’:電子元件
22:導磁件
23:導體結構
23a:第一導電層
23b:第二導電層
230:導電凸塊
231:導電柱
24:封裝層
25:導電元件
S:凹部

Claims (20)

  1. 一種電子封裝件，係包括：
    承載件；
    電子元件，係設於該承載件上；
    至少一導磁件，係設於該承載件與該電子元件之間；以及
    導體結構，係包含配置於該電子元件上之第一導電層、配置於該承載件上之第二導電層、及複數設於該電子元件與該承載件之間的導電凸塊，以令該導磁件位於該第一導電層與第二導電層之間，且該複數導電凸塊電性連接該第一導電層與第二導電層。
  2. 如請求項1所述之電子封裝件，其中，該承載件係為無核心層之線路結構。
  3. 如請求項1所述之電子封裝件，其中，該承載件係具有一供容置該導磁件之凹部。
  4. 如請求項3所述之電子封裝件，其中，該導體結構復包含複數嵌埋於該承載件中之導電柱，且該複數導電柱係位於該凹部之周圍並電性連接該導電凸塊與該第二導電層。
  5. 如請求項1所述之電子封裝件，其中，該導磁件係結合至該承載件上。
  6. 如請求項1所述之電子封裝件，其中，該導磁件係結合至該電子元件上。
  7. 如請求項1所述之電子封裝件，其中，該導磁件係嵌埋於該電子元件中。
  8. 如請求項1所述之電子封裝件，其中，該承載件與該電子元件之間係配置有複數該導磁件。
  9. 如請求項1所述之電子封裝件，其中，該承載件係為封裝基板，其具有核心層及結合於該核心層相對兩側之線路結構。
  10. 如請求項1所述之電子封裝件，其中，該電子元件係為主動元件或封裝結構。
  11. 一種電子封裝件之製法，係包括：
    提供一具有第一導電層之電子元件及一具有第二導電層之承載件；以及
    將該電子元件藉由複數導電凸塊設於該承載件上，且令該電子元件與該承載件之間夾置有至少一導磁件，其中，該複數導電凸塊電性連接該第一導電層與第二導電層，且該導磁件位於該第一導電層與第二導電層之間。
  12. 如請求項11所述之電子封裝件之製法，其中，該承載件係為無核心層之線路結構。
  13. 如請求項11所述之電子封裝件之製法，其中，該承載件具有一供容置該導磁件之凹部。
  14. 如請求項13所述之電子封裝件之製法，復包括於該承載件中形成複數導電柱，且該複數導電柱係位於該凹部之周圍並電性連接該導電凸塊與該第二導電層。
  15. 如請求項11所述之電子封裝件之製法，其中，該導磁件係結合至該承載件上。
  16. 如請求項11所述之電子封裝件之製法，其中，該導磁件係結合至該電子元件上。
  17. 如請求項11所述之電子封裝件之製法，其中，該導磁件係嵌埋於該電子元件中。
  18. 如請求項11所述之電子封裝件之製法，其中，該承載件與該電子元件之間係配置有複數該導磁件。
  19. 如請求項11所述之電子封裝件之製法，其中，該承載件係為封裝基板，其具有核心層及結合於該核心層相對兩側之線路結構。
  20. 如請求項11所述之電子封裝件之製法，其中，該電子元件係為主動元件或封裝結構。
TW109132583A 2020-09-21 2020-09-21 電子封裝件及其製法 TWI734616B (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
TW109132583A TWI734616B (zh) 2020-09-21 2020-09-21 電子封裝件及其製法
CN202011126623.5A CN114256213A (zh) 2020-09-21 2020-10-20 电子封装件及其制法
US17/159,527 US11587892B2 (en) 2020-09-21 2021-01-27 Electronic package and manufacturing method thereof
US18/097,847 US20230154872A1 (en) 2020-09-21 2023-01-17 Electronic package and manufacturing method thereof
US18/097,965 US11984412B2 (en) 2020-09-21 2023-01-17 Electronic package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW109132583A TWI734616B (zh) 2020-09-21 2020-09-21 電子封裝件及其製法

Publications (2)

Publication Number Publication Date
TWI734616B TWI734616B (zh) 2021-07-21
TW202213652A true TW202213652A (zh) 2022-04-01

Family

ID=77911252

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109132583A TWI734616B (zh) 2020-09-21 2020-09-21 電子封裝件及其製法

Country Status (3)

Country Link
US (2) US11587892B2 (zh)
CN (1) CN114256213A (zh)
TW (1) TWI734616B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI734616B (zh) * 2020-09-21 2021-07-21 矽品精密工業股份有限公司 電子封裝件及其製法
JP2022144711A (ja) * 2021-03-19 2022-10-03 三菱電機株式会社 半導体装置の製造方法
CN116864494B (zh) * 2023-09-01 2023-12-05 甬矽电子(宁波)股份有限公司 扇出型封装结构和扇出型封装结构制作方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI244715B (en) * 2004-12-23 2005-12-01 Advanced Semiconductor Eng Semiconductor package
US7531893B2 (en) * 2006-07-19 2009-05-12 Texas Instruments Incorporated Power semiconductor devices having integrated inductor
US10879183B2 (en) * 2018-06-22 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11335618B2 (en) * 2018-07-09 2022-05-17 Intel Corporation Thermals for packages with inductors
TWI734616B (zh) * 2020-09-21 2021-07-21 矽品精密工業股份有限公司 電子封裝件及其製法

Also Published As

Publication number Publication date
US11587892B2 (en) 2023-02-21
US20220093538A1 (en) 2022-03-24
US20230154873A1 (en) 2023-05-18
US20230154872A1 (en) 2023-05-18
TWI734616B (zh) 2021-07-21
CN114256213A (zh) 2022-03-29

Similar Documents

Publication Publication Date Title
TWI734616B (zh) 電子封裝件及其製法
US20140117562A1 (en) Semiconductor device
TWI611542B (zh) 電子封裝結構及其製法
TW201724926A (zh) 具有被動元件的低剖面封裝
TW201526178A (zh) 晶片封裝結構
TWI559341B (zh) 電子封裝件
CN112992476B (zh) 变压器，以及封装模块
TWI728936B (zh) 電子封裝件及其製法
CN107895717B (zh) 电子封装件及其制法
TWI718838B (zh) 電子封裝件及其製法
TWI723414B (zh) 電子封裝件及其製法
TW201838136A (zh) 電子封裝件及其承載結構與製法
TWI681414B (zh) 電子模組
US20220254869A1 (en) Inductor structure and fabrication method thereof, electronic package and fabrication method thereof, and method for fabricating packaging carrier
TWI610402B (zh) 電子封裝結構及其製法
US11984412B2 (en) Electronic package and manufacturing method thereof
CN108305855B (zh) 电子封装件及其基板结构
TWI646652B (zh) 電感組合及其線路結構
US20160300660A1 (en) Electronic device
TW201738976A (zh) 晶片封裝體及晶片封裝製程
CN115692384A (zh) 一种射频芯片模块的堆叠结构及其封装方法
JP2004133762A (ja) データキャリア及びその製造方法
TW202249229A (zh) 電子封裝件及其製法
TW201640531A (zh) 電子裝置