CN114256213A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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CN114256213A
CN114256213A CN202011126623.5A CN202011126623A CN114256213A CN 114256213 A CN114256213 A CN 114256213A CN 202011126623 A CN202011126623 A CN 202011126623A CN 114256213 A CN114256213 A CN 114256213A
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conductive
electronic
layer
carrier
magnetic
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邱志贤
张克维
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

本发明涉及一种电子封装件及其制法，包括于承载件与电子元件之间配置至少一导磁件，且该电子元件具有第一导电层，而该承载件具有第二导电层，以令该导磁件位于该第一导电层与第二导电层之间，并于该电子元件与该承载件之间配置多个电性连接该第一导电层与第二导电层的导电凸块，以环绕该导磁件而产生磁通量。

Description

电子封装件及其制法
技术领域
本发明有关一种半导体装置，尤指一种具导磁件(ferromagnetic material)的电子封装件及其制法。
背景技术
一般半导体应用装置，例如通讯或高频半导体装置中，常需要将电阻器、电感器、电容器及振荡器(oscillator)等多个射频(radio frequency)被动元件电性连接至所封装的半导体芯片，从而使该半导体芯片具有特定的电流特性或发出信号。
以球栅阵列(Ball Grid Array，简称BGA)半导体装置为例，多个被动元件虽安置于基板表面，然为了避免所述被动元件阻碍半导体芯片与多个焊垫间的电性连接及配置，传统上多将所述被动元件安置于基板角端位置或半导体芯片接置区域以外的基板额外布局面积上。
然而，限定被动元件的位置将限制基板线路布局(Routability)的灵活性；同时此举需考虑焊垫位置会导致所述被动元件布设数量受到局限，不利半导体装置高度集成化的发展趋势；甚者，被动元件布设数量随着半导体封装件高性能的要求而相对地遽增，如采现有方法该基板表面必须同时容纳多个半导体芯片以及较多被动元件而造成封装基板面积加大，进而迫使封装件体积增大，也不符合半导体封装件轻薄短小的发展潮流。
基于上述问题，业界遂将该多个被动元件制作成集总元件(如芯片型电感)整合至半导体芯片与焊垫区域间的基板区域上。如图1所示的半导体封装件1，其于一具有线路层100的封装基板10上设置一半导体芯片11及多个电感元件12，且该半导体芯片11经由多个焊线110电性连接该线路层100的焊垫101。
然而，该电感元件12为芯片型，故其所需体积大，特别是电源电路所需的电感元件12，且该电感元件12距离该半导体芯片11过远，致使寄生(parasitic)效应随着该电感元件12远离该半导体芯片11而增加，因而造成该半导体封装件1的电性效能不佳。
此外，该电感元件12形成于该封装基板10的表面上，将占据该封装基板10的大量布设空间，因而容易造成该半导体封装件1难以符合微小化的需求。
另外，业界也有以线圈型电感12’取代该芯片型电感元件12，如图1’所示的半导体封装件1’，但该线圈型电感12’仅设在该封装基板10上，因而该线圈型电感12’所产生的电感模拟值有限，致使该线圈型电感12’的电感值过小而难以符合需求。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺陷，本发明提供一种电子封装件及其制法，以解决或部分解决现有技术存在的各种问题。
本发明的电子封装件，包括：承载件；电子元件，其设于该承载件上；至少一导磁件，其设于该承载件与该电子元件之间；以及导体结构，其包含配置于该电子元件上的第一导电层、配置于该承载件上的第二导电层、及多个设于该电子元件与该承载件之间的导电凸块，以令该导磁件位于该第一导电层与第二导电层之间，且该多个导电凸块电性连接该第一导电层与第二导电层。
本发明还提供一种电子封装件的制法，包括：提供一具有第一导电层的电子元件及一具有第二导电层的承载件；以及将该电子元件经由多个导电凸块设于该承载件上，且令该电子元件与该承载件之间夹置有至少一导磁件，其中，该多个导电凸块电性连接该第一导电层与第二导电层，且该导磁件位于该第一导电层与第二导电层之间。
前述的电子封装件及其制法中，该承载件为无核心层的线路结构。
前述的电子封装件及其制法中，该承载件具有一供容置该导磁件的凹部。例如，该导体结构还包含多个嵌埋于该承载件中的导电柱，且该多个导电柱位于该凹部的周围并电性连接该导电凸块与该第二导电层。
前述的电子封装件及其制法中，该导磁件结合至该承载件上。
前述的电子封装件及其制法中，该导磁件结合至该电子元件上。例如，该导磁件嵌埋于该电子元件中。
前述的电子封装件及其制法中，该承载件与该电子元件之间配置有多个该导磁件。
前述的电子封装件及其制法中，该承载件为封装基板，其具有核心层及结合于该核心层相对两侧的线路结构。
前述的电子封装件及其制法中，该电子元件为主动元件或封装结构。
由上可知，本发明的电子封装件及其制法中，主要经由将该导体结构的第一导电层与第二导电层分别配置于该承载件与该电子元件上，而易于环绕该导磁件，使该导磁件与该导体结构产生的磁通量增加，以增加电感量，进而增加电感值。
此外，经由该导磁件的设计，可增加单一线圈的电感值，故相比于现有无导磁件的线圈型电感，本发明可用较少的线圈数量达到相同的电感值，因而能微小化电感的体积。
附图说明
图1为现有半导体封装件的剖面示意图。
图1’为现有另一半导体封装件的剖面示意图。
图2A至图2D为本发明的电子封装件的第一实施例的制法的剖视示意图。
图2C’为图2C的局部上视示意图。
图3A为本发明的电子封装件的第二实施例的剖视示意图。
图3B为本发明的电子封装件的第三实施例的剖视示意图。
图4A为为本发明的电子封装件的第四实施例的剖视示意图。
图4B为图4A的另一实施例的剖视示意图。
图5为本发明的电子封装件的第五实施例的剖视示意图。
图6为本发明的电子封装件的第六实施例的剖面示意图。
附图标记说明
1,1’：半导体封装件
10：封装基板
100,200：线路层
101：焊垫
11,61：半导体芯片
110：焊线
12：电感元件
12’：线圈型电感
2,3,3’,4,4’,5,6：电子封装件
2a,4a：电感
20,30,50：承载件
20a：第一侧
20b：第二侧
21,21’,6a：电子元件
21a：半导体基体
21b：介电体
210：布线层
211,63：接点
22,32,42：导磁件
22a：第一表面
22b：第二表面
22c：侧面
23：导体结构
23a：第一导电层
23b：第二导电层
230：导电凸块
231：导电柱
24：封装层
25：导电元件
500：核心层
501：线路结构
60：包覆层
61a：作用面
61b：非作用面
610：电极垫
62：线路部
620：介电层
621：线路重布层
S：凹部。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2D为本发明的电子封装件2的第一实施例的制法的剖面示意图。
如图2A所示，提供一电子元件21，其为如半导体芯片的主动元件，包含一半导体基体21a及一形成于该半导体基体21a上的介电体21b，该半导体基体21a中具有积体电路，且该介电体21b中设有至少一布线层210及一第一导电层23a。
于本实施例中，该布线层210与该第一导电层23a均为铜材，且该布线层210部分外露于该介电体21b以作为接点211，并使该第一导电层23a电性连接该接点211。
如图2B所示，提供一具有凹部S的承载件20，并于该凹部S中容置一导磁件22。
如图2B至图2C所示，将该电子元件21对应该导磁件22设于该承载件20上，使该导磁件22位于该承载件20与该电子元件21之间。
于本实施例中，该承载件20为无核心层(coreless)的线路结构，其于介电材上形成至少一线路层200及一第二导电层23b，如扇出(fan out)型重布线路层(redistributionlayer，简称RDL)，且介电材为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)等。例如，该承载件20具有相对的第一侧20a与第二侧20b，且该电子元件21与该导磁件22设于该承载件20的第一侧20a上。应可理解地，该承载件20的第一侧20a上也可配置其它电子元件21’。
此外，该承载件20的第一侧20a形成有该凹部S，且该电子元件21对应遮盖于该凹部S的上方。例如，该电子元件21以其接点211经由多个导电凸块230以覆晶方式电性连接该承载件20的线路层200，且该第二导电层23b配置于该凹部S的底侧，并于该承载件20中对应该凹部S的侧壁周围形成多个电性连接该第二导电层23b与该导电凸块230的导电柱231。
另外，该导磁件22具有高磁导率(permeability)的特性，如铁素体(ferrite)，其具有相对的第一表面22a与第二表面22b、及邻接该第一表面22a与第二表面22b的侧面22c，以于该导磁件22上圈绕一导体结构23。例如，该导体结构23包含第一导电层23a、第二导电层23b、导电柱231与导电凸块230，以令该导体结构23呈回状线圈，使该导磁件22位于该回状线圈中。具体地，如图2C’所示，该第一导电层23a与第二导电层23b为直线状导电迹线，其布设对应该导磁件22的第一表面22a及第二表面22b，而该些导电柱221与导电凸块230的布设对应该导磁件22的侧面22c，使该回状线圈的路径依序经过该导磁件22的第一表面22a、侧面22c、第二表面22b及侧面22c。
另外，该导体结构23与该导磁件22产生磁通量，以令该导体结构23与该导磁件22构成电感2a。
如图2D所示，形成一封装层24于该承载件20的第一侧20a上，以包覆该电子元件21,21’、该导磁件22与该导电凸块230，使该导磁件22固定于该凹部S中。
于本实施例中，该封装层24的形成材料为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(epoxy)或封装层(molding compound)。例如，该封装层24的制程可选择液态封胶(liquid compound)、喷涂(injection)、压合(lamination)或模压(compression molding)等方式形成于该承载件20的第一侧20a上。
此外，该承载件20的第二侧20b可依需求形成多个如焊球的导电元件25。
另外，若该制法中的承载件20呈现整版面型式，可依需求进行切单制程。
因此，本发明的制法中，经由将第一导电层23a与第二导电层23b分别配置于该承载件20与该电子元件21上，并于承载件20与电子元件21之间配置至少一导磁件22，以令该导磁件22位于该第一导电层23a与第二导电层23b之间，并于该电子元件21与该承载件20之间配置多个电性连接该第一导电层23a与第二导电层23b的导电凸块230，以环绕该导磁件22，使该导磁件22与导体结构23产生磁通量。
图3A为本发明的电子封装件3的第二实施例的剖面示意图。本实施例与第一实施例的差异在于导磁件22的位置与承载件30的实施例，故仅说明相异处，而其它相同处不再赘述。
如图3A所示，该承载件30的第一侧20a未形成有凹部，以令该导磁件22设于该承载件30的第一侧20a的表面上。
图3B为本发明的电子封装件3’的第三实施例的剖面示意图。本实施例与第二实施例的差异在于导磁件32的位置，故仅说明相异处，而其它相同处不再赘述。
如图3B所示，该导磁件32设于该电子元件21的介电体21b的表面上。
图4A为本发明的电子封装件4的第四实施例的剖面示意图。本实施例与第三实施例的差异在于导磁件42的位置，故仅说明相异处，而其它相同处不再赘述。
如图4A所示，该导磁件42嵌埋于该电子元件21的介电体21b中。于本实施例中，于制作该电子元件21时，一并将该导磁件42嵌埋于该介电体21b中。
此外，也可于第一实施例中配置一具有该导磁件42的电子元件21，如图4B所示的电子封装件4’，以于该承载件20与该电子元件21之间配置有多个导磁件22,42，以增加该电感4a的磁通量。
图5为本发明的电子封装件5的第五实施例的剖面示意图。本实施例与上述各实施例的差异在于承载件50的实施例，故仅说明相异处，而其它相同处不再赘述。
如图5所示，基于第二实施例，该承载件50为封装基板(substrate)，其具有一核心层500及结合于该核心层500相对两侧的线路结构501，其于介电材上形成至少一线路层及该第二导电层23b，如扇出(fan out)型重布线路层(RDL)，且介电材为如聚对二唑苯(PBO)、聚酰亚胺(PI)、预浸材(PP)等。
图6为本发明的电子封装件6的第六实施例的剖面示意图。本实施例与上述各实施例的差异在于电子元件6a的实施例，故仅说明相异处，而其它相同处不再赘述。
如图6所示，基于第一实施例，该电子元件6a为封装结构，如晶圆级封装(WaferLevel Package，简称WLP)结构或芯片级封装(Chip Scale Package，简称CSP)结构，其以包覆层60包覆至少一半导体芯片61，再于该包覆层60上形成一电性连接该半导体芯片61的线路部62。
于本实施例中，该包覆层60的形成材料为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(epoxy)或封装层(molding compound)。例如，该包覆层60的制程可选择液态封胶(liquid compound)、喷涂(injection)、压合(lamination)或模压(compression molding)等方式形成。应可理解地，该包覆层60与该封装层24可为相同材料或不同材料。
此外，该半导体芯片61具有相对的作用面61a与非作用面61b，且该作用面61a具有多个电极垫610。
另外，该线路部62包含至少一介电层620与至少一设于该介电层620上并电性连接该电极垫610的线路重布层(Redistribution layer，简称RDL)621，且该第一导电层23a设于该介电层620中且电性连接该线路重布层621。例如，形成该线路重布层621的材料为铜，且形成该介电层620的材料如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它等的介电材。具体地，该电子元件6a的线路重布层621部分外露于该介电层620以作为接点63，以令该些接点63经由该些导电凸块230电性连接该承载件20的线路层200。
另外，于制作该线路部62时，一并将该导磁件42嵌埋于该介电层620中。
本发明的电子封装件2,3,3’,4,4’,5,6经由该导体结构23环绕该导磁件22,32,42，使磁场将趋向于集中在低磁阻的铁磁路径(ferromagnetic path)，即该导磁件22,32,42，因而得以增加磁通量，进而增加电感量，使本发明的电感值可大幅提高。
此外，本发明经由该导磁件22,32,42的设计，可增加单一线圈的电感值，故相比于现有无磁铁的线圈型电感，本发明可用较少的线圈数量达到相同的电感值。例如，现有线圈型电感需三圈线圈才能达到17nH，而本发明的回状线圈仅需一圈即可达到17nH。
另外，本发明的电感2a,4a由该导体结构23与该导磁件22,32,42所构成，故能依需求微小化电感的体积。例如，欲达到相同的电感值，本发明的回状线圈的圈数少于现有线圈型电感的圈数圈，因而减少电感的体积，且该导磁件22,32,42内部可无需设计线路(即纯导磁材料)，因而其体积可依需求减少，故本发明的电感符合微小化的需求。
因此，相比于现有技术，本发明的电子封装件2,3,3’,4,4’,5,6能以更小的布设范围制作电感2a,4a并产生更大的电感值。
本发明还提供一种电子封装件2,3,3’,4,4’,5,6，包括：一承载件20,30,50、一电子元件21,6a、至少一导磁件22,32,42、以及一导体结构23。
所述的承载件20,30,50具有相对的第一侧20a与第二侧20b。
所述的电子元件21,6a设于该承载件20,30,50上。
所述的导磁件22,32,42设于该承载件20,30,50与该电子元件21,6a之间。
所述的导体结构23包含一配置于该电子元件21,6a上的第一导电层23a、一配置于该承载件20,30,50上的第二导电层23b、及多个设于该电子元件21,6a与该承载件20,30,50之间的导电凸块230，以令该导磁件22,32,42位于该第一导电层23a与第二导电层23a,23b之间，且该多个导电凸块230电性连接该第一导电层23a与第二导电层23b。
于一实施例中，该承载件20,30为无核心层的线路结构。
于一实施例中，该承载件20具有一供容置该导磁件22的凹部S。例如，该导体结构23还包含多个嵌埋于该承载件20中的导电柱231，且该多个导电柱231位于该凹部S的侧壁周围并电性连接该导电凸块230与该第二导电层23b。
于一实施例中，该导磁件22结合至该承载件30的第一侧20a的表面上。
于一实施例中，该导磁件32,42结合至该电子元件21上。进一步，该导磁件42嵌埋于该电子元件21中。
于一实施例中，该承载件20与该电子元件21之间配置有多个该导磁件22,42。
于一实施例中，该承载件50为封装基板，其具有一核心层500及结合于该核心层500相对两侧的线路结构501。
于一实施例中，该电子元件21为主动元件。
于一实施例中，该电子元件6a为封装结构。
综上所述，本发明的电子封装件及其制法，经由将该导体结构的第一导电层与第二导电层分别配置于该承载件与该电子元件上，而易于环绕该导磁件，使该导磁件与该导体结构产生的磁通量增加，以增加电感量，进而增加电感值。此外，经由该导磁件的设计，可增加单一线圈的电感值，故相比于现有无导磁件的线圈型电感，本发明可用较少的线圈数量达到相同的电感值，因而能微小化电感的体积。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (20)

1.一种电子封装件，其特征在于，包括：
承载件；
电子元件，其设于该承载件上；
至少一导磁件，其设于该承载件与该电子元件之间；以及
导体结构，其包含配置于该电子元件上的第一导电层、配置于该承载件上的第二导电层、及多个设于该电子元件与该承载件之间的导电凸块，以令该导磁件位于该第一导电层与第二导电层之间，且该多个导电凸块电性连接该第一导电层与第二导电层。
2.如权利要求1所述的电子封装件，其特征在于，该承载件为无核心层的线路结构。
3.如权利要求1所述的电子封装件，其特征在于，该承载件具有一供容置该导磁件的凹部。
4.如权利要求3所述的电子封装件，其特征在于，该导体结构还包含多个嵌埋于该承载件中的导电柱，且该多个导电柱位于该凹部的周围并电性连接该导电凸块与该第二导电层。
5.如权利要求1所述的电子封装件，其特征在于，该导磁件结合至该承载件上。
6.如权利要求1所述的电子封装件，其特征在于，该导磁件结合至该电子元件上。
7.如权利要求1所述的电子封装件，其特征在于，该导磁件嵌埋于该电子元件中。
8.如权利要求1所述的电子封装件，其特征在于，该承载件与该电子元件之间配置有多个该导磁件。
9.如权利要求1所述的电子封装件，其特征在于，该承载件为封装基板，其具有核心层及结合于该核心层相对两侧的线路结构。
10.如权利要求1所述的电子封装件，其特征在于，该电子元件为主动元件或封装结构。
11.一种电子封装件的制法，其特征在于，包括：
提供一具有第一导电层的电子元件及一具有第二导电层的承载件；以及
将该电子元件经由多个导电凸块设于该承载件上，且令该电子元件与该承载件之间夹置有至少一导磁件，其中，该多个导电凸块电性连接该第一导电层与第二导电层，且该导磁件位于该第一导电层与第二导电层之间。
12.如权利要求11所述的电子封装件的制法，其特征在于，该承载件为无核心层的线路结构。
13.如权利要求11所述的电子封装件的制法，其特征在于，该承载件具有一供容置该导磁件的凹部。
14.如权利要求13所述的电子封装件的制法，还包括于该承载件中形成多个导电柱，且该多个导电柱位于该凹部的周围并电性连接该导电凸块与该第二导电层。
15.如权利要求11所述的电子封装件的制法，其特征在于，该导磁件结合至该承载件上。
16.如权利要求11所述的电子封装件的制法，其特征在于，该导磁件结合至该电子元件上。
17.如权利要求11所述的电子封装件的制法，其特征在于，该导磁件嵌埋于该电子元件中。
18.如权利要求11所述的电子封装件的制法，其特征在于，该承载件与该电子元件之间配置有多个该导磁件。
19.如权利要求11所述的电子封装件的制法，其特征在于，该承载件为封装基板，其具有核心层及结合于该核心层相对两侧的线路结构。
20.如权利要求11所述的电子封装件的制法，其特征在于，该电子元件为主动元件或封装结构。
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