WO2019232749A1 - 一种集成电路 - Google Patents

一种集成电路 Download PDF

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Publication number
WO2019232749A1
WO2019232749A1 PCT/CN2018/090269 CN2018090269W WO2019232749A1 WO 2019232749 A1 WO2019232749 A1 WO 2019232749A1 CN 2018090269 W CN2018090269 W CN 2018090269W WO 2019232749 A1 WO2019232749 A1 WO 2019232749A1
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WO
WIPO (PCT)
Prior art keywords
ground
substrate
chip
layer
material layer
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Application number
PCT/CN2018/090269
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English (en)
French (fr)
Inventor
刘立筠
张珊
刘国文
吴韦
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201880094420.7A priority Critical patent/CN112292916B/zh
Priority to PCT/CN2018/090269 priority patent/WO2019232749A1/zh
Publication of WO2019232749A1 publication Critical patent/WO2019232749A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields

Definitions

  • the present application relates to the technical field of electronic product manufacturing, and in particular, to an integrated circuit.
  • Electromagnetic interference usually includes radio frequency interference (Radio Frequency Interference) and magnetic field interference.
  • Radio frequency interference is due to interference between different RF modules (WCDMA, LTE, WiFi / BT & GPS) of the same product.
  • Magnetic field interference is caused by changes in the magnetic field caused by changes in current and voltage in the hardware circuits of electronic products. The higher the frequency of current and voltage in electronic products, the smaller the product, and the greater the harm from electromagnetic interference.
  • the conventional EMI solution is to add a good conductive metal layer / shell or conductive medium (EMI shielding).
  • EMI Shielding directly covers the shielding conductive medium (through sputtering, plating, spraying, etc.) directly on the top and sides of the package to achieve the effect of electromagnetic shielding.
  • the electronic components are soldered on the substrate, and a shielding layer (EMI shielding) is attached to the side of the electronic components and the substrate.
  • the substrate contains a single or multiple copper layers, and each copper layer is composed of a wiring wiring portion and a ground wiring portion.
  • the shield layer is directly or through other means connected to the ground wiring part, so that the shield layer is grounded, so as to achieve a better isolation effect.
  • ground wiring part is very close to the internal circuit, and it is easy to induce instantaneous current (rapid change of strong electric field) in the circuit, which is very easy to cause the current of electronic components to be overloaded, and finally the electrical performance of the components is invalidated or reduced.
  • the present application provides an integrated circuit. Can improve the ability of electronic products to prevent electromagnetic interference and anti-static discharge.
  • a specific embodiment of the present application provides an integrated circuit including a substrate, a chip carried on the substrate, and a shielding case, the shielding case covers the chip and the substrate, and the shielding case is made of a conductive material;
  • the first ground layer includes a first ground portion and a second ground portion. The first ground layer is disconnected between the first ground portion and the second ground portion.
  • a first ground interface and a second ground are provided at the bottom of the substrate. Interface; the first ground portion is electrically connected to the shield case and the first ground interface, and the second ground portion is electrically connected to the chip and the second ground interface.
  • the substrate is further provided with a second ground layer.
  • the second ground layer includes a third ground portion and a fourth ground portion.
  • the third ground portion is electrically connected to the first ground interface
  • the fourth ground portion is connected to the first ground interface.
  • the two ground interfaces are electrically connected, and the second ground layer is disconnected between the third ground portion and the fourth ground portion.
  • the fracture of the second ground layer between the third ground portion and the fourth ground portion is staggered from the fracture of the first ground layer between the first ground portion and the second ground portion.
  • the electromagnetic interference signals entering the chip through the fractures are reduced, thereby further reducing the electromagnetic interference of the chip.
  • a third ground layer is further provided in the substrate.
  • the third ground layer includes a fifth ground portion, and the fifth ground portion is electrically connected to the second ground interface and separated from the shield case.
  • the chip is disposed on the upper surface of the substrate, and the shielding case surrounds the side of the substrate.
  • the first ground layer is filled with a dielectric material in a fracture between the first ground portion and the second ground portion.
  • the substrate is further provided with at least two dielectric material layers, and the at least two dielectric material layers and the ground layer are alternately arranged.
  • the material of the dielectric material layer is the same as the material of the dielectric filling the fracture.
  • the chip is disposed on the dielectric material layer, and the ground end of the chip is electrically connected to the ground layer through the dielectric material layer.
  • the first ground portion is an area surrounded by a fracture of the closed structure in the ground layer
  • the second ground portion is an area outside the area surrounded by the fracture of the closed structure in the ground layer.
  • an isolation material is also provided between the shielding case and the chip.
  • FIG. 1 is an integrated circuit provided by a specific embodiment of the present application
  • FIG. 3 is an integrated circuit in which a chip is disposed on an inverted surface of a substrate according to a specific embodiment of the present application.
  • FIG. 1 is an integrated circuit provided by a specific embodiment of the present application. As shown in FIG. 1, the integrated circuit includes a substrate 101, a chip 102 carried on the substrate 101, and a shield case 103.
  • the shielding shell covers the chip and the substrate, and is used for shielding electromagnetic signals from the chip and the substrate.
  • the shielding case 103 may be a concave structure.
  • the chip and the substrate are disposed in a concave cavity formed by the shielding case 103.
  • the shielding case 103 includes four side walls and a top plate, and the length and width of the top plate are equal to the length and width of the substrate.
  • the four side walls are respectively arranged vertically on the four sides of the top plate, and the lengths of the four side walls are respectively equal to the lengths of the sides of the top plate provided.
  • the shielding case 103 is disposed on the chip 102 and the substrate 101.
  • the shielding housing 103 is a concave cavity is only one specific implementation of the present application.
  • both can be the shielding case 103 of the specific embodiment of the present application.
  • the shielding case 103 is a material capable of shielding electromagnetic signals.
  • the shielding case 103 is a metal material.
  • a shielding case is provided on the substrate 101 and the chip 102 so as to prevent the substrate 101 and the chip 102 from being subjected to electromagnetic interference (Electro-Magnetic Interference, EMI).
  • EMI Electro-Magnetic Interference
  • the type and number of the chip 102 can be set as required.
  • the surface of the chip 102 may be provided with an isolation material, and the shielding case 103 and the chip 102 are separated by the isolation material.
  • the substrate 101 includes at least one layer of a conductive material and at least two layers of a dielectric material.
  • the at least one layer of the conductive material is overlapped, and the at least two layers of the dielectric material respectively cover the top of each of the at least one layer of the conductive material. Surface and lower surface.
  • the substrate 101 in the specific embodiment of the present application includes a first conductive material layer 106 to a fourth conductive material layer 109 and a first dielectric material layer 110 to a fifth dielectric material layer 113.
  • One side of the first conductive material layer 106 covers the first dielectric material layer 110 and the other side covers the second dielectric material layer 111.
  • One side of the second conductive material layer 107 covers the second dielectric material layer 111 and the other side covers the third dielectric material layer 112.
  • One side of the third conductive material layer 108 covers the third dielectric material layer 112 and the other side covers the fourth dielectric material layer 113.
  • One side of the fourth conductive material layer 109 covers the fourth dielectric material layer 113 and the other side covers the fifth dielectric material layer 114.
  • Each conductive material layer may be a metal wiring
  • the metal wiring includes a ground wiring portion (the ground wiring portion may also be referred to as a ground layer) and a wiring wiring portion.
  • the wiring and wiring part is electrically connected to the signal input / output terminal 104 of the chip 102 and is used for transmitting working signals for the chip 102.
  • the ground wiring portion is electrically connected to the ground terminal 105 of the chip 102 and the shield case 103, and is used to ground the ground terminal 105 of the chip 102 and the shield case 103.
  • the application does not limit the arrangement of the ground wiring portion and the wiring wiring portion in each conductive material layer.
  • the metal wiring of the present application may further include a dummy wiring portion, and the redundant wiring portion is used to improve the strength of the substrate 101. Whether or not the metal wiring includes the redundant wiring portion and the position of the redundant wiring portion can be determined during the design of the substrate 101, which is not limited in this application.
  • the chip 102 may be disposed on the first dielectric material layer 110, and the signal input / output terminal 104 of the chip 102 is conductive with at least one layer by punching in the first dielectric material layer 110.
  • the wiring and wiring portion in the layer is electrically connected, and the ground end 105 of the chip 102 is electrically connected to the ground wiring portion in at least one conductive layer.
  • connection manner between the signal input / output terminal 104 and the wiring wiring unit and the connection manner between the ground terminal 105 and the ground wiring unit can be determined according to specific lines, which is not limited in this application.
  • each conductive material layer can be divided into a first ground wiring 115 and a second ground wiring 116 (the first ground wiring may also be referred to as a first ground wiring, and the second ground wiring may also be referred to as a second ground wiring ).
  • the fracture 117 between the first ground wiring 115 and the second ground wiring 116 may also be filled with a dielectric material, and the dielectric material is an insulating material.
  • the dielectric material may be the same material as the dielectric material layer.
  • the fracture 117 is a closed structure.
  • the area surrounded by the fracture 117 is the first ground wiring 115, and the area outside the area surrounded by the fracture 117 is the second ground wiring 116.
  • the shield case 103 is electrically connected to the second ground wiring 116.
  • the substrate 101 is rectangular, and the second ground wiring 116 is electrically connected to the inside of the shield case 103 at a position equal to the length and width of the substrate.
  • the shield case 103 is grounded through the second ground wiring 116.
  • the shield case 103 is a cylinder matching the substrate 101.
  • a position of the second ground wiring 116 having a diameter equal to that of the substrate 101 is electrically connected to the shield case 103.
  • the above-mentioned substrate 101 is circular or rectangular is only an example in the specific embodiment of the present application. In a specific embodiment of the present application, the substrate 101 may be of any regular or irregular shape.
  • the connection between the shield case 103 and the second ground wiring 116 is the same as described above.
  • each conductive material layer is divided into a first ground wiring 115 and a second ground wiring 116 to prevent static electricity on the shielding case 103 from flowing to the first ground wiring 115, thereby preventing damage to the chip 102.
  • the position of the break between the first ground wiring and the second ground wiring in the first conductive material layer 106 and the position of the break between the first ground wiring and the second ground wiring in the second conductive material layer 107 are staggered.
  • the position of the break between the first ground wiring and the second ground wiring in the second conductive material layer 107 and the position of the break between the first ground wiring and the second ground wiring in the third conductive material layer 108 are staggered.
  • the position of the break between the first ground wiring and the second ground wiring in the third conductive material layer 108 and the position of the break between the first ground wiring and the second ground wiring in the fourth conductive material layer 109 are staggered.
  • the fractures of two adjacent conductive material layers are staggered, and the projections of the fractures of two adjacent conductive material layers on the plane where the conductive material layer is located do not overlap.
  • the entry through the locations of the fractures between the first ground wiring and the second ground wiring in at least one conductive material layer is reduced.
  • the electromagnetic interference signal of the chip 102 further reduces the electromagnetic interference of the chip.
  • At least one through-hole 118 is further provided between the first conductive material layer 106 to the fourth conductive material layer 109, and the through-hole 118 is used to connect ground wirings between different conductive material layers.
  • the fourth conductive material layer 109 is further provided with at least one connection end 119, and each connection end 119 passes through the fifth dielectric material layer 114. Therefore, the ground signal of the chip 102 and the shield case 103 and the working signal of the chip 102 are output through the at least one connection terminal 119.
  • connection terminal 119 is divided into a ground interface and a wiring interface according to the functions it implements.
  • the ground interface is used to connect to the ground wiring in at least one layer of conductive material
  • the wiring interface is used to connect to the wiring in at least one layer of conductive material connection.
  • Different wiring can connect different wiring interfaces. This application does not limit the connection of wiring and wiring interfaces.
  • the first ground wiring of the fourth conductive material layer 114 includes at least one first ground interface, and the first ground interface is electrically connected to the shield case.
  • the second ground wiring of the fourth conductive material layer 114 includes at least one second ground interface, and the second ground interface is connected to a ground terminal of the chip.
  • the first ground interface may be an EMI function pin (PAD)
  • the second ground interface may be a ground PAD.
  • the EMI function PAD and the ground PAD are used to ground the ground signal of the shield case and / or the chip 102, respectively.
  • connection length of each first ground interface of the fourth conductive material layer 114 and the shielding case is not limited.
  • the first ground interface may have a ring structure around the fracture, and the first ground interface is electrically connected to the shield case in all directions. connection.
  • the fourth conductive material layer 114 may further include at least one input / output (I / O) PAD, and the I / O PAD may be used to input / output a plurality of different signals.
  • I / O PAD input / output PAD
  • the functions and number are not limited.
  • any one of the at least one conductive material layer may also adopt other arrangement methods.
  • FIG. 2 is an integrated circuit provided by a specific embodiment of the present application. As shown in FIG. 2, it includes a substrate 201, a chip 202 carried on the substrate 201, and a shield case 203.
  • the shielding case 203 is disposed on the chip 202 and the substrate 201.
  • the shielding case 203 and the chip 202 may be the same as those shown in FIG. 1, which are not described in detail in this application. This application only describes the substrate 201.
  • the substrate 201 includes at least one conductive material layer and at least two dielectric material layers.
  • the at least one conductive material layer is disposed in an overlapping manner, and the at least two dielectric material layers respectively cover the upper surface and the lower surface of each conductive material layer.
  • the substrate 201 in the specific embodiment of the present application includes a first conductive material layer 204 to a fourth conductive material layer 207 and a first dielectric material layer 208 to a fifth dielectric material layer 212.
  • One side of the first conductive material layer 204 covers the first dielectric material layer 208 and the other side covers the second dielectric material layer 209.
  • One side of the second conductive material layer 205 covers the second dielectric material layer 209 and the other side covers the third dielectric material layer 210.
  • One side of the third conductive material layer 206 covers the third dielectric material layer 210 and the other side covers the fourth dielectric material layer 211.
  • One side of the fourth conductive material layer 207 covers the fourth dielectric material layer 211 and the other side covers the fifth dielectric material layer 212.
  • Each conductive material layer may be a metal wiring, and the metal wiring includes a ground wiring portion (the ground wiring portion may also be referred to as a ground layer) and a wiring wiring portion.
  • the metal wiring of the present application may further include a dummy wiring portion.
  • the metal wiring of each conductive material layer is the same as that in FIG. 1, which is not described in this application.
  • the ground wiring portions of the second conductive material layer 205 and the fourth conductive material layer 207 may include a first ground wiring 213 and a second ground wiring 214 (the first ground wiring may also be referred to as (The first ground portion and the second ground wiring may also be referred to as a second ground portion).
  • a break 215 exists between the first ground wiring 213 and the second ground wiring 214. The break 215 is used to divide the second conductive material layer 205 and the fourth conductive material layer 207 into first ground wiring 213 and Two ground wiring 214.
  • Fracture 215 is a closed structure.
  • the area surrounded by the fracture 215 is the first ground wiring 213, and the area outside the area surrounded by the fracture 215 is the second ground wiring 214.
  • the sizes of the first conductive material layer 204 and the third conductive material layer 206 are smaller than those of the second conductive material layer 205 and the fourth conductive material layer 207.
  • the length and width of the second conductive material layer 205 and the fourth conductive material layer 207 are equal to the length and width of the substrate 201.
  • the length and width of the first conductive material layer 204 and the third conductive material layer 206 are smaller than the length and width of the second conductive material layer 205 and the fourth conductive material layer 207, respectively.
  • the first conductive material layer 204 and the third conductive material layer 206 can be understood as the first ground wiring 213 of the second conductive material layer 205 and the fourth conductive material layer 207.
  • the position of the break 215 between the first ground wiring 213 and the second ground wiring 214 in the second conductive material layer 205 and the fourth conductive material layer 207, and the length of the first conductive material layer 204 and the third conductive material layer 206 are smaller than
  • the positions of the second conductive material layer 205 and the fourth conductive material layer 207 include filled dielectric materials, respectively.
  • the dielectric material is the same material as the fifth dielectric material layer 212 of the first dielectric material layer 208.
  • the shield case 203 is electrically connected to the second ground wiring 214.
  • the substrate 201 is rectangular, and the second ground wiring 214 in the second conductive material layer 205 and the fourth conductive material layer 207 is electrically connected to the inner side of the shield case 203 at a position equal to the length and width of the substrate 201.
  • the shield case 203 is grounded through the second ground wiring 214.
  • the first conductive material layer 20, the third conductive material layer 206, and the first ground wiring 213 are not connected to the shield case 203.
  • the substrate 201 is rectangular, and the length and width of the first conductive material layer 204 and the third conductive material layer 206 are smaller than the length and width of the second conductive material layer 205 and the fourth conductive material layer 207, respectively.
  • the substrate 201 may be of any regular or irregular shape, and the connection between the shielding case 203 and the second ground wiring 214 in the substrate 201 is the same as described above.
  • the long and wide edges of the first conductive material layer 204 are staggered from the position of the break 215 of the second conductive material layer 205; the position of the break 215 of the second conductive material layer 205 is third conductive
  • the long and wide edges of the material layer 206 are staggered; the long and wide edges of the third conductive material layer 206 are staggered from the position of the fracture 215 of the fourth conductive material layer 207.
  • staggering the long and wide edges of the two adjacent conductive material layers with the fracture means that the projections of the fracture and the long and wide edges on the plane where the conductive material layer is located do not overlap.
  • the long and wide edges of the first conductive material layer 204 and the third conductive material layer 206 are staggered from the fracture 215 of the second conductive material layer 205 and the fourth conductive material layer 207, thereby The electromagnetic interference signal entering the chip 202 through the fracture 215 between the multiple layers of conductive material is reduced, thereby further reducing the electromagnetic interference of the chip 202.
  • connection scheme between the chip 102 and the substrate 101 shown in FIG. 1 is only an example in the specific embodiment of the present application, and cannot be used to limit the present application.
  • the substrate 101 may be connected to any number of chips 102 using any connection scheme.
  • FIG. 3 is an integrated circuit in which a chip is disposed on an inverted surface of a substrate according to a specific embodiment of the present application. As shown in FIG. 3, it includes a substrate 301, a first chip 302, a second chip 303, and a shield case 304.
  • the first chip 302 is fixedly disposed above the substrate 301; the second chip 303 is fixedly disposed below the substrate 301.
  • the shield case 304 is disposed on the first chip 302 and the substrate 301.
  • connection relationship between the shielding case 304, the substrate 301, and the first chip 302 is the same as that shown in FIG. 1, which is not described in this application.
  • This embodiment only describes the connection between the substrate 301 and the second chip 303.
  • the type and number of the first chip 302 and the second chip 303 can be set as required.
  • An isolation material 305 is also wrapped on the surface of the second chip 303 and the bottom of the base 301.
  • the isolation material 305 is used to prevent the outer surfaces of the second chip 303 and the substrate 301 from being exposed.
  • the isolation material 305 may be the same as the isolation material shown in FIG. 1, or may be the same material as the first dielectric material layer 110 to the fifth dielectric material layer 113 in FIG. 1. .
  • the second chip 303 includes a signal input / output terminal 306 and a ground terminal 306.
  • the signal input / output terminal 306 is electrically connected to the wiring and wiring portion of the substrate 301, and is used to input and output an operating signal.
  • the ground terminal 307 is electrically connected to the ground wiring portion of the substrate 301 and is used to output a ground signal.
  • the substrate 301 includes at least one layer of conductive material and at least two layers of dielectric material, and the at least one layer of conductive material is disposed to overlap.
  • the at least two dielectric material layers respectively cover an upper surface and a lower surface of each of the at least one conductive material layer.
  • the at least one conductive material layer and the at least two dielectric material layers are the same as those shown in FIG. 1, which are not described in this application.
  • Each conductive material layer may be a metal wiring
  • the metal wiring includes a ground wiring portion (the ground wiring portion may also be referred to as a ground layer) and a wiring wiring portion.
  • the at least one layer of conductive material further includes at least one connection end 308.
  • the ground signal and / or the working signal of the first chip 302, the second chip 303, and the shield case 304 are output through the at least one connection terminal 308.
  • connection terminal 308 is divided into a ground interface and a wiring interface according to the functions it implements.
  • the ground interface is used to connect to the ground wiring portion in at least one layer of conductive material
  • the wiring interface is used to connect to the wiring in at least one layer of conductive material.
  • the wiring section is connected.
  • the signal input / output terminal 306 of the second chip 303 is electrically connected to the wiring of at least one conductive material layer in the substrate 301.
  • the ground terminal 307 of the second chip 303 is electrically connected to a ground wiring or a ground interface of at least one conductive material layer in the substrate 301.
  • the isolation material 305 filled at the bottom of the substrate 301 further includes a hole 309. At least one connection end 308 included in the substrate 301 is connected through the hole 309. The arrangement of the connection end 308 on the substrate 301 can be specifically shown in FIG. 1, which is not described in this application.
  • FIG. 1 to FIG. 3 are only some examples in the specific embodiments of the present application, and cannot be used to limit the present application.
  • the structure is electrically connected. Therefore, the electronic interference of the chip can be reduced, and the electronic product damage caused by the electrostatic discharge when the package components are in contact can be avoided.
  • the disclosed devices and structures may be implemented in other ways.
  • the device embodiments described above are merely schematic.
  • the division of the structure is only a logical function division.
  • multiple units or components may be combined or integrated.

Abstract

一种集成电路，包括基板，承载在所述基板上的芯片，以及屏蔽壳体。屏蔽壳体覆盖芯片和基板，屏蔽壳体由导电材料制成。基板中设有第一接地层，第一接地层包括第一接地部和第二接地部，第一接地层在第一接地部和第二接地部之间断开。基板底部设有第一接地接口和第二接地接口。第一接地部与所述屏蔽壳体和第一接地接口电连接，第二接地部与芯片和第二接地接口电连接。本申请通过在芯片和基板上覆盖屏蔽壳体，以及将接地层分割为第一接地部和第二接部，达到降低芯片的电磁干扰的同时避免屏蔽壳体上的静电流至第一接地部时可能对芯片造成的损坏。

Description

一种集成电路 技术领域
本申请涉及电子产品制造技术领域，尤其涉及一种集成电路。
背景技术
随着半导体产品系统化、微小化的不断发展，电子元器件(芯片)非常容易受到不同电磁辐射的干扰。电磁辐射会严重影响信号传输的连续性和准确性。因此，产品的抗电磁干扰设计变得越来越重要。电磁干扰(Electro-Magnetic Interference，EMI)通常包括射频干扰(Radio Frequency Interference)和磁场干扰等。射频干扰是由于同一产品的不同RF模块(WCDMA,LTE,WiFi/BT&GPS)相互之间的干扰。磁场干扰是电子产品硬件电路由于电流、电压的变化产生磁场的变化而产生。电子产品中电流电压频率越高，产品越小，受电磁干扰的危害越大。
常规的EMI解决方案是在产品外面加一层导电性良好的金属层/壳或导电介质(抗电磁干扰隔离层-EMI Shielding)。EMI Shielding是直接在封装体上面和侧面直接覆盖屏蔽导电介质(通过溅镀，电镀，喷涂等方式)，从而达到电磁屏蔽的效果。
电子元器件焊接在基板上，电子元器件和基板侧面附着屏蔽层(EMI Shielding)，基板含有单层或者多层铜层，每层铜层都由接线布线部和接地布线部组成。屏蔽层直接或通过其他方式与接地布线部相连接，使屏蔽层接地，以便达到更好的隔离效果。
现有的接地产品结构设计，当有发生ESD静电放电时，高压电流会通过屏蔽层流向接地布线部。而接地布线部与内部线路非常近，容易在线路中诱导出瞬间电流(强电场的快速变化)，非常容易导致电子元器件电流过载，最后使元器件电性能失效或者降低。
发明内容
根据上述技术问题，本申请提供一种集成电路。能够同时提高电子产品防电磁干扰和抗静电释放的能力。
本申请是通过如下方法实现的：
一方面，本申请具体实施例提供一种集成电路，包括基板，承载在基板上的芯片，以及屏蔽壳体，屏蔽壳体覆盖芯片和基板，屏蔽壳体由导电材料制成；基板中设有第一接地层，第一接地层包括第一接地部和第二接地部，第一接地层在第一接地部和第二接地部之间断开；基板底部设有第一接地接口和第二接地接口；第一接地部与屏蔽壳体和第一接地接口电连接，第二接地部与芯片和第二接地接口电连接。
通过在芯片和基板上覆盖屏蔽壳体，以及将接地层分割为第一接地部和第二接部，达到降低芯片的电磁干扰的同时避免屏蔽壳体上的静电流至第一接地部时可能对芯片 造成的损坏。
在一个可能的设计中，基板中还设有第二接地层，第二接地层包括第三接地部和第四接地部，第三接地部与第一接地接口电连接，第四接地部与第二接地接口电连接，第二接地层在第三接地部和第四接地部之间断开。第二接地层在第三接地部和第四接地部之间的断口，与第一接地层在第一接地部和第二接地部之间的断口错开。
通过将不同接地层中接地部之间的断口错开设置，减少通过断口进入芯片的电磁干扰信号，从而进一步降低芯片的电磁干扰。
在一个可能的设计中，基板中还设有第三接地层，第三接地层包括第五接地部，第五接地部与第二接地接口电连接且与屏蔽壳体分离。
在一个可能的设计中，芯片设置在基板上表面，屏蔽壳体包裹基板的侧部。
在一个可能的设计中，第一接地层在第一接地部和第二接地部之间的断口中填充有介质材料。
在一个可能的设计中，基板中还设有至少两层介电材料层，至少两层介电材料层与接地层层叠交替设置。
在一个可能的设计中，介电材料层的材料与填充断口的介质材料相同。
在一个可能的设计中，芯片设置在介电材料层上，芯片的地端穿过介电材料层与接地层电连接。
在一个可能的设计中，第一接地部为接地层中封闭结构的断口所包围的区域，第二接地部为接地层中封闭结构的断口所包围区域之外的区域。
在一个可能的设计中，屏蔽壳体与芯片之间还设有隔离材料。
附图说明
图1为本申请具体实施例提供的一种集成电路；
图2为本申请具体实施例提供的一种集成电路；
图3为本申请具体实施例提供的一种芯片设置在基板倒立面的集成电路。
具体实施方式
以下结合附图，详细说明本申请各实施例提供的技术方案。
图1为本申请具体实施例提供的一种集成电路，如图1所示，包括基板101、承载在基板101上的芯片102和屏蔽壳体103。
所述屏蔽壳体覆盖芯片和基板，以用于实现对芯片和基板的电磁信号屏蔽。
屏蔽壳体103可以是凹型结构。芯片和基板设置在屏蔽壳体103所形成的凹型腔体内。
在一个例子中，屏蔽壳体103包括四个侧壁和一个顶板，顶板的长和宽与基板的长和宽相等。四个侧壁分别垂直的设置在顶板的四个边上，四个侧壁的长度分别与其所设置的顶板的边的长度相等。屏蔽壳体103覆盖的设置在芯片102和基板101上。
需要说明的是，屏蔽壳体103为凹型腔体仅为本申请的一种具体实现方式。在本申请的具体实施例中，只要能够将基板101和芯片102覆盖并能够屏蔽电磁信号，均 可以是本申请具体实施例的屏蔽壳体103。
屏蔽壳体103为能够屏蔽电磁信号的材料，在一个例子中，屏蔽壳体103为金属材料。本申请通过在基板101和芯片102之上覆盖的设置屏蔽壳体，从而避免基板101和芯片102受到电磁干扰(Electro-Magnetic Interference，EMI)。
芯片102的种类和数量可以根据需要设置。
芯片102的表面可以设置有隔离材料，通过隔离材料实现屏蔽壳体103与芯片102的分离。
基板101包括至少一层导电材料层和至少两层介电材料层，该至少一层导电材料层重叠设置，该至少两层介电材料层分别覆盖该至少一层导电材料层中每层的上表面和下表面。
具体的，本申请具体实施例中的基板101包括第一导电材料层106至第四导电材料层109和第一介电材料层110至第五介电材料层113。第一导电材料层106的一面覆盖第一介电材料层110，另一面覆盖第二介电材料层111。第二导电材料层107的一面覆盖第二介电材料层111，另一面覆盖第三介电材料层112。第三导电材料层108的一面覆盖第三介电材料层112，另一面覆盖第四介电材料层113。第四导电材料层109的一面覆盖第四介电材料层113，另一面覆盖第五介电材料层114。
每个导电材料层均可以为金属布线，金属布线包括接地布线部(接地布线部也可以称为接地层)和接线布线部。其中，接线布线部与芯片102的信号输入输出端104电连接，用于为芯片102传输工作信号。接地布线部与芯片102的地端105和屏蔽壳体103电连接，用于为芯片102的地端105和屏蔽壳体103接地。本申请对接地布线部和接线布线部在每层导电材料层中的设置不进行限定。
可选的，本申请的金属布线还可以包括冗余(Dummy)布线部，冗余布线部用于提高基板101的强度。金属布线中是否包括冗余布线部、冗余布线部的位置可以在基板101设计时进行确定，本申请对此不进行限定。
在本申请的具体实施例中，芯片102可以设置在第一介电材料层110上，通过在第一介电材料层110上打孔，将芯片102的信号输入输出端104与至少一层导电层中的接线布线部电连接，将芯片102的地端105与至少一层导电层中的接地布线部电连接。
信号输入输出端104与接线布线部的连接方式及地端105与接地布线部的连接方式均可以根据具体的线路确定，本申请对此不进行限定。
每个导电材料层的接地布线部均可以分为第一接地布线115和第二接地布线116(第一接地布线也可以称为第一接地部，第二接地布线也可以称为第二接地部)。第一接地布线115和第二接地布线116之间存在断口117，断口117用于将每个导电材料层分割为互不电连接的第一接地布线115和第二接地布线116。
第一接地布线115和第二接地布线116之间的断口117内还可以填充有介质材料，介质材料为绝缘材料。在一个具体的例子中，介质材料可以是与介电材料层相同的材料。
在本申请的具体实施例中，断口117为封闭结构。断口117所包围的区域为第一接地布线115，断口117包围区域之外的区域为第二接地布线116。
屏蔽壳体103与第二接地布线116电连接。例如，基板101为矩形，第二接地布线116中与基板长、宽相等的位置还与屏蔽壳体103的内侧电连接。从而通过第二接地布线116将屏蔽壳体103接地。在一个例子中，当基板101的形状为圆形时，屏蔽壳体103为与基板101相匹配的圆筒。第二接地布线116中与基板101直径相等的位置与屏蔽壳体103电连接。
当然，上述基板101为圆形或矩形仅为本申请具体实施例中的一种举例说明。在本申请的具体实施例中，基板101可以是任意规则或不规则形状。屏蔽壳体103与第二接地布线116的连接与上述相同。
本申请通过将每个导电材料层分割为第一接地布线115和第二接地布线116，避免屏蔽壳体103上的静电流至第一接地布线115，从而避免对芯片102造成损坏。
第一导电材料层106中第一接地布线和第二接地布线之间断口的位置和第二导电材料层107中第一接地布线和第二接地布线之间断口的位置错开。第二导电材料层107中的第一接地布线和第二接地布线之间的断口位置和第三导电材料层108中的第一接地布线和第二接地布线之间断口的位置错开。第三导电材料层108中的第一接地布线和第二接地布线之间的断口的位置和第四导电材料层109中的第一接地布线和第二接地布线之间断口的位置错开。
需要说明的是，两个相邻导电材料层的断口错开是，两个相邻导电材料层的断口在导电材料层所在平面的投影不相重叠。
在本申请的具体实施例中，通过将两个相邻的导电材料层的断口的位置错开，从而减少通过至少一层导电材料层中第一接地布线和第二接地布线之间断口的位置进入芯片102的电磁干扰信号，从而进一步降低芯片的电磁干扰。
在另一个实施例中，第一导电材料层106至第四导电材料层109之间还设置有至少一个穿孔118，穿孔118用于将不同导电材料层之间的接地布线进行连接。
第四导电材料层109上还设置有至少一个连接端119，各个连接端119分别穿过第五介电材料层114。从而通过该至少一个连接端119将芯片102和屏蔽壳体103的接地信号以及芯片102的工作信号输出。
连接端119根据其所实现的功能被分为接地接口和接线接口，接地接口用于与至少一层导电材料层中的接地布线连接，接线接口用于与至少一层导电材料层中的接线布线连接。不同接线布线可以连接不同的接线接口。本申请对接线布线与接线接口的连接不进行限定。
第四导电材料层114的第一接地布线包括至少一个第一接地接口，第一接地接口与屏蔽壳体电连接。第四导电材料层114的第二接地布线包括至少一个第二接地接口，第二接地接口与芯片的地端点连接。在本申请的具体实施例中，第一接地接口可以是EMI功能引脚(PAD)，第二接地接口可以是接地PAD。EMI功能PAD和接地PAD分别用于将屏蔽壳体和/或芯片102的接地信号接地。
在本申请的具体实施例中，第四导电材料层114的每个第一接地接口与屏蔽壳体电连接的连接长度不进行限定。可选的，当第四导电材料层114的第一接地布线仅包括一个第一接地接口时，第一接地接口可以是绕断口的环形结构，第一接地接口在各个方向均与屏蔽壳体电连接。
当然，第四导电材料层114中还可以包括至少一个输入输出(input/output，I/O)PAD，I/O PAD可以用于输入/输出多种不同的信号，本申请对I/O PAD的功能和数量不进行限定。
在本申请的具体实施例中，通过在每个导电材料层上设置交错的断口117，避免静电对芯片102的损坏仅为本申请具体实施例中的一种举例。在本申请的具体实施例中，该至少一层导电材料层中的任意一层还可以采用其他设置方式。
图2为本申请具体实施例提供的一种集成电路。如图2所示，包括基板201、承载在基板201上的芯片202和屏蔽壳体203。屏蔽壳体203覆盖的设置在芯片202和基板201上。其中，屏蔽壳体203和芯片202可以与图1所示相同，本申请在此不再进行赘述。本申请仅对基板201进行描述。
基板201包括至少一层导电材料层和至少两层介电材料层，该至少一层导电材料层重叠设置，该至少两层介电材料层分别覆盖每个导电材料层的上表面和下表面。
具体的，本申请具体实施例中的基板201包括第一导电材料层204至第四导电材料层207和第一介电材料层208至第五介电材料层212。第一导电材料层204的一面覆盖第一介电材料层208，另一面覆盖第二介电材料层209。第二导电材料层205的一面覆盖第二介电材料层209，另一面覆盖第三介电材料层210。第三导电材料层206的一面覆盖第三介电材料层210，另一面覆盖第四介电材料层211。第四导电材料层207的一面覆盖第四介电材料层211，另一面覆盖第五介电材料层212。
每个导电材料层均可以为金属布线，金属布线包括接地布线部(接地布线部也可以称为接地层)和接线布线部。可选的，本申请的金属布线还可以包括冗余(Dummy)布线部。每个导电材料层的金属布线与图1相同，本申请对此不在赘述。
在本申请的具体实施例中，第二导电材料层205和第四导电材料层207的接地布线部分别可以包括第一接地布线213和第二接地布线214(第一接地布线也可以称为是第一接地部，第二接地布线也可以称为第二接地部)。第一接地布线213和第二接地布线214之间存在断口215，断口215用于将第二导电材料层205和第四导电材料层207分别分割为互不电连接的第一接地布线213和第二接地布线214。
断口215为封闭结构。断口215所包围的区域为第一接地布线213，断口215包围区域之外的区域为第二接地布线214。
第一导电材料层204和第三导电材料层206的尺寸小于第二导电材料层205和第四导电材料层207的尺寸。在一个例子中，当基板201的形状为矩形时，第二导电材料层205和第四导电材料层207的长和宽与基板201的长和宽相等。第一导电材料层204和第三导电材料层206的长和宽分别小于第二导电材料层205和第四导电材料层207的长和宽。
在本申请的具体实施例中，第一导电材料层204和第三导电材料层206可以理解为第二导电材料层205和第四导电材料层207的第一接地布线213。
第二导电材料层205和第四导电材料层207中第一接地布线213和第二接地布线214之间断口215的位置、第一导电材料层204和第三导电材料层206长和宽尺寸小于第二导电材料层205和第四导电材料层207的位置分别包括填充介质材料。在一个具体的例子中，介质材料为与第一介电材料层208之第五介电材料层212相同的材料。
屏蔽壳体203与第二接地布线214电连接。例如，基板201为矩形，第二导电材料层205和第四导电材料层207中第二接地布线214中与基板201长、宽相等的位置还与屏蔽壳体203的内侧电连接。从而通过第二接地布线214将屏蔽壳体203接地。第一导电材料层20、第三导电材料层206和第一接地布线213不与屏蔽壳体203连接。
当然，上述基板201为矩形、第一导电材料层204和第三导电材料层206的长和宽分别小于第二导电材料层205和第四导电材料层207的长和宽仅为本申请具体实施例中的一种举例说明。在本申请的具体实施例中，基板201可以是任意规则或不规则形状，屏蔽壳体203与基板201中第二接地布线214的连接与上述相同。
在本申请的具体实施例中，第一导电材料层204的长和宽的边缘与第二导电材料层205的断口215的位置错开；第二导电材料层205的断口215的位置与第三导电材料层206的长和宽的边缘错开；第三导电材料层206的长和宽的边缘与第四导电材料层207的断口215的位置错开。
需要说明的是，两个相邻导电材料层中长和宽的边缘与断口错开是指，断口与长和宽的边缘在导电材料层所在平面的投影不相重叠。
在本申请的具体实施例中，通过将第一导电材料层204和第三导电材料层206的长和宽的边缘与第二导电材料层205和第四导电材料层207的断口215错开，从而减少通过多层导电材料层之间的断口215进入芯片202的电磁干扰信号，从而进一步降低芯片202的电磁干扰。
需要说明的是，图1所示的芯片102与基板101的连接方案仅为本申请具体实施例中的一种举例，不能用于对本申请的限定。本申请具体实施例中，基板101可以采用任意连接方案与任意数量的芯片102连接。
图3为本申请具体实施例提供的一种芯片设置在基板倒立面的集成电路。如图3所示，包括基板301、第一芯片302、第二芯片303和屏蔽壳体304。其中，第一芯片302固定的设置在基板301之上；第二芯片303固定的设置在基板301之下。屏蔽壳体304覆盖的设置在第一芯片302和基板301上。
在该例子中，屏蔽壳体304、基板301和第一芯片302的连接关系与图1所示相同，本申请在此不进行赘述。本实施例仅对基板301与第二芯片303之间的连接进行描述。
第一芯片302和第二芯片303的种类和数量可以根据需要设置。
第二芯片303的表面及基本301的底部还包裹的设置了隔离材料305，通过隔离材料305避免第二芯片303和基板301的外表面暴露。在本申请的具体实施例中，该隔离材料305既可以是与图1所示的隔离材料相同，也可以与图1中第一介电材料层110至第五介电材料层113的材料相同。
第二芯片303包括信号输入输出端306和地端306。信号输入输出端306与基板301的接线布线部电连接，用于输入输出工作信号。地端307与基板301的接地布线部电连接，用于输出接地信号。
基板301包括至少一层导电材料层和至少两层介电材料层，该至少一层导电材料层重叠设置。该至少两层介电材料层分别覆盖该至少一层导电材料层中每层的上表面和下表面。该至少一层导电材料层和至少两层介电材料层与图1所示相同，本申请对 此不进行赘述。
每个导电材料层均可以为金属布线，金属布线包括接地布线部(接地布线部也可以称为接地层)和接线布线部。
该至少一层导电材料层还包括至少一个连接端308。通过该至少一个连接端308将第一芯片302、第二芯片303和屏蔽壳体304的接地信号和/或工作信号输出。
连接端308根据其所实现的功能被分为接地接口和接线接口，接地接口用于与至少一层导电材料层中的接地布线部连接，接线接口用于与至少一层导电材料层中的接线布线部连接。
第二芯片303的信号输入输出端306与基板301中至少一层导电材料层的接线布线电连接。第二芯片303的地端307与基板301中至少一层导电材料层的接地布线或接地接口电连接。
可选的，填充在基板301底部的隔离材料305还包括打孔309。通过打孔309将基板301中包括的至少一个连接端308接出。连接端308在基板301上的设置具体可以如图1所示，本申请对此不再赘述。
当然，上述图1至图3实施例仅为本申请具体实施例中的部分举例，并不能用于对本申请的限定。只要包括覆盖基板和芯片的，且基板中靠近芯片金属布线不覆盖基板和芯片的结构电连接。从而在降低芯片的电子干扰的同时还能避免封装组件接触时由于静电释放而造成的电子产品损坏。
需要说明的是，本申请提供实施例只是本申请所介绍的可选实施例，本领域技术人员在此基础上，完全可以设计出更多的实施例，因此不在此处赘述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的，能够以类似结构的结合来实现。专业技术人员可以对每个特定的部分来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的装置和结构的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和结构，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，结构的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (10)

  1. 一种集成电路，其特征在于，包括：基板，承载在所述基板上的芯片，以及屏蔽壳体，所述屏蔽壳体覆盖所述芯片和所述基板，所述屏蔽壳体由导电材料制成；
    所述基板中设有第一接地层，所述第一接地层包括第一接地部和第二接地部，所述第一接地层在所述第一接地部和第二接地部之间断开；
    所述基板底部设有第一接地接口和第二接地接口；
    所述第一接地部与所述屏蔽壳体和所述第一接地接口电连接，所述第二接地部与所述芯片和所述第二接地接口电连接。
  2. 如权利要求1所述的集成电路，其特征在于，所述基板中还设有第二接地层，所述第二接地层包括第三接地部和第四接地部，所述第三接地部与所述第一接地接口电连接，所述第四接地部与所述第二接地接口电连接，所述第二接地层在所述第三接地部和第四接地部之间断开，
    所述第二接地层在所述第三接地部和第四接地部之间的断口，与所述第一接地层在所述第一接地部和第二接地部之间的断口错开。
  3. 如权利要求1或2所述的集成电路，其特征在于，所述基板中还设有第三接地层，所述第三接地层包括第五接地部，所述第五接地部与所述第二接地接口电连接且与所述屏蔽壳体分离。
  4. 如权利要求1-3任一项所述的集成电路，其特征在于，所述芯片设置在所述基板上表面，所述屏蔽壳体包裹所述基板的侧部。
  5. 如权利要求1-4任一项所述的集成电路，其特征在于，所述第一接地层在所述第一接地部和第二接地部之间的断口中填充有介质材料。
  6. 如权利要求5所述的集成电路，其特征在于，所述基板中还设有至少两层介电材料层，所述至少两层介电材料层与接地层层叠交替设置。
  7. 如权利要求6所述的集成电路，其特征在于，所述介电材料层的材料与填充所述断口的介质材料相同。
  8. 如权利要求6所述的集成电路，其特征在于，所述芯片设置在所述介电材料层上，所述芯片的地端穿过介电材料层与接地层电连接。
  9. 如权利要求1-7任一项所述的集成电路，其特征在于，所述第一接地部为所述接地层中封闭结构的断口所包围的区域，所述第二接地部为所述接地层中封闭结构的断口所包围区域之外的区域。
  10. 如权利要求1-9任一项所述的集成电路，其特征在于，所述屏蔽壳体与芯片之间还设有隔离材料。
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