WO2019062241A1 - 一种晶圆级系统封装方法以及封装结构 - Google Patents

一种晶圆级系统封装方法以及封装结构 Download PDF

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WO2019062241A1
WO2019062241A1 PCT/CN2018/093770 CN2018093770W WO2019062241A1 WO 2019062241 A1 WO2019062241 A1 WO 2019062241A1 CN 2018093770 W CN2018093770 W CN 2018093770W WO 2019062241 A1 WO2019062241 A1 WO 2019062241A1
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wafer
wafers
plug
chip
packaging
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PCT/CN2018/093770
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English (en)
French (fr)
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刘孟彬
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中芯集成电路（宁波）有限公司
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Priority to US16/176,098 priority Critical patent/US10756056B2/en
Publication of WO2019062241A1 publication Critical patent/WO2019062241A1/zh

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Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a wafer level system packaging method and a package structure.
  • SiP System in Package
  • MEMS micro-electromechanical systems
  • optical components and other components into one unit to form a variety Functional systems or subsystems that allow heterogeneous IC integration are the best package integration technologies.
  • SoC System On Chip
  • wafer level package is a package integration process on the wafer, which greatly reduces the area of the package structure, reduces manufacturing costs, optimizes electrical performance, and manufactures batches. Other advantages can significantly reduce the workload and equipment needs.
  • An aspect of the present invention provides a wafer level system packaging method for stacking at least two wafers on which chips are formed in a stacking direction, including:
  • a plug is formed to electrically connect the chips in the two wafers.
  • Also includes:
  • a thinning process is performed on the back side of one of the wafers facing away from the outside.
  • the method further includes:
  • the back side of one of the wafers is thinned.
  • the step of forming a plug includes:
  • the plug is formed above the corresponding chip
  • the plug is formed on one side of the corresponding chip, and before forming the plug, further includes forming an interconnection, electrically connecting with the corresponding chip, and electrically connecting to the plug on the side of the corresponding chip.
  • the method further includes:
  • a redistribution interconnect structure is formed to electrically connect the plugs.
  • the redistribution interconnect structure includes: a rewiring layer and a pad, or includes a pad.
  • the method is for stacking two wafer-formed wafers together in a stacking direction.
  • the method is for stacking at least three wafer-formed wafers together in a stacking direction.
  • the method further includes:
  • one is a new wafer and the other is one of the two wafers that have been joined together.
  • the two wafers are bonded by a fusion bonding process, a silicon-silicon direct bonding process, or a bonding process.
  • the thinning process is at least one of a mechanical grinding process, a chemical mechanical grinding process, or an etching process.
  • a wafer level system package structure including:
  • At least two wafers on which chips are formed are stacked and joined together in a direction perpendicular to the surface of the wafer;
  • the plug, the chips in the two wafers bonded to each other, are electrically connected through the plug.
  • two wafers bonded to each other one of which has a front side that is oppositely joined to the other side;
  • the back of one of them is joined to the back of the other.
  • the plug is formed above the corresponding chip
  • the plug is formed on one side of the corresponding chip, and is also formed with an interconnection line electrically connected to the corresponding chip and electrically connected to the plug on the side of the corresponding chip.
  • it also includes:
  • a redistribution interconnect structure electrically connecting the plugs is located on top of the plug.
  • the redistribution interconnect structure includes: a rewiring layer and a pad, or includes a pad.
  • the method further includes forming a bonding layer at an interface of the bonded wafers.
  • the packaging method of the present invention completes package fabrication on a wafer and integrates multiple chips together, thereby achieving a combination of wafer level packaging and system packaging methods, compared to conventional packaging methods (cutting and then packaging and testing) After packaging, at least 20% of the volume of the original chip is increased.
  • at least two wafers on which the chip is formed are stacked on top of each other, stacked and bonded together, that is, the upper and lower stacked packages of the chip are implemented, and are completed on the wafer.
  • the size of the original chip can be maintained, so that the area of the package structure can be greatly reduced, and the corresponding chip is electrically connected through the plug, and the circuit wiring is short, which can effectively reduce current loss.
  • the electrical performance is optimized, and the method of the present invention is manufactured by a mass production process in the form of a wafer, and the packaging processing efficiency is higher.
  • the packaging production line is not required, so that the packaging can be significantly reduced.
  • the requirements of the device; the packaging method of the present invention directly forms the wafer with the chip into the packaging process, and the intermediate link Significantly reduced, cycle times are reduced, manufacturing costs and workload are reduced, and package efficiency and yield are improved.
  • the package structure obtained by the wafer level system packaging method of the present invention also has higher performance and yield.
  • FIG. 1A to FIG. 1E are schematic cross-sectional views showing a structure obtained by sequentially stacking two wafer-formed wafers in a stacking direction in an upper and lower stacking direction according to an embodiment of the present invention
  • 2A is a cross-sectional view showing a structure obtained by bonding a front surface of one wafer and a back surface of another wafer in an embodiment of the present invention
  • 2B is a cross-sectional view showing a structure obtained by joining back sides of two wafers in an embodiment of the present invention
  • 3A to 3C are schematic cross-sectional views showing a structure obtained by sequentially stacking three wafer-formed wafers in a stacking manner in the upper and lower stacking directions according to an embodiment of the present invention
  • 4A is a cross-sectional view showing a structure in which three wafer-formed wafers are stacked and joined together in an upper and lower stacking direction according to another embodiment of the present invention
  • 4B is a cross-sectional view showing a structure obtained by stacking and bonding three wafer-formed wafers in an upper and lower stacking direction according to still another embodiment of the present invention
  • FIG. 5 shows a flow chart of a wafer level system packaging method in accordance with an embodiment of the present invention.
  • Spatial relationship terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc. This description may be used to describe the relationship of one element or feature shown in the figures to the other elements or features. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned “on” or “below” or “below” or “under” the element or feature is to be “on” the other element or feature. Thus, the exemplary terms “below” and “include” can include both the above and the The device may be otherwise oriented (rotated 90 degrees or other orientation) and the spatial descriptors used herein interpreted accordingly.
  • composition and/or “comprising”, when used in the specification, is used to determine the presence of the features, integers, steps, operations, components and/or components, but does not exclude one or more The presence or addition of features, integers, steps, operations, components, components, and/or groups.
  • the term “and/or” includes any and all combinations of the associated listed items.
  • Embodiments of the invention are described herein with reference to cross-section illustrations of schematic representations of the preferred embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown can be expected as a result, for example, of manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the specific shapes of the regions illustrated herein, but rather include variations in the shape, for example. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implanted concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation takes place. The regions shown in the figures are, therefore, are not intended to limit the scope of the invention.
  • the present invention provides an improved wafer level system packaging method for stacking at least two wafers formed with chips in a stacking direction, as shown in the figure. As shown in 5, it mainly includes the following steps:
  • Step S1 joining two pieces of the wafers that need to be joined together
  • Step S2 after the bonding, forming a plug electrically connected to the chips in the two wafers.
  • the packaging method of the present invention completes package fabrication on a wafer and integrates multiple chips together, thereby achieving a combination of wafer level packaging and system packaging methods, compared to conventional packaging methods (cutting and then packaging and testing) After packaging, at least 20% of the volume of the original chip is increased.
  • at least two wafers on which the chip is formed are stacked on top of each other, stacked and bonded together, that is, the upper and lower stacked packages of the chip are implemented, and are completed on the wafer.
  • the size of the original chip can be maintained, so that the area of the package structure can be greatly reduced, and the corresponding chip is electrically connected through the plug, and the circuit wiring is short, which can effectively reduce current loss.
  • the electrical performance is optimized, and the method of the present invention is manufactured by a mass production process in the form of a wafer, and the packaging processing efficiency is higher.
  • the packaging production line is not required, so that the packaging can be significantly reduced.
  • the requirements of the device; the packaging method of the present invention directly forms the wafer with the chip into the packaging process, and the intermediate link Significantly reduced, cycle times are reduced, manufacturing costs and workload are reduced, and package efficiency and yield are improved.
  • FIGS. 1A to 1E show a wafer in which two chips are formed stacked on the upper and lower sides in one embodiment of the present invention.
  • the method of stacking and joining together sequentially performs a schematic cross-sectional view of the obtained structure.
  • the wafer level system packaging method of the present invention is used for stacking at least two wafers on which chips are formed in a stacking direction, for example, for wafers on which two chips are formed.
  • Stacking and joining together in the stacking direction including the following steps:
  • step 1 is performed.
  • a first wafer 100 formed with a first chip 101 and a second wafer 200 formed with a second chip 201 are provided, for example, at the first wafer 100.
  • a plurality of first chips 101 spaced apart from each other are disposed inside the front surface, and a plurality of second chips 201 spaced apart from each other are disposed inside the front surface of the second wafer 200.
  • the first wafer 100 and the second wafer 200 are formed for the completed device, and a plurality of device wafers of the first chip 101 and the plurality of second chips 201 are respectively formed.
  • the device wafer can be fabricated by using integrated circuit fabrication technology according to a corresponding layout design, such as forming a device such as NMOS and/or PMOS by deposition, etching, etc. on a semiconductor wafer, and forming a dielectric layer and a metal layer.
  • the interconnect layer and the pad on the interconnect layer are structured to fabricate the first chip 101 and the second chip 201 in an array in the semiconductor wafer.
  • the first wafer 100 and the second wafer 200 each include a semiconductor substrate
  • the semiconductor substrate may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs GaAs, InP, InGaAs or other III/V compound semiconductors, including multilayer structures of these semiconductors, etc., or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), and silicon-on-insulator (S) -SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).
  • the chip involved in the present invention may be any one of semiconductor chips, which may include a memory, a logic circuit, Active devices such as power devices, bipolar devices, individual MOS transistors, and microelectromechanical systems (MEMS), or even photovoltaic devices such as light-emitting diodes, may also be passive devices such as resistors, capacitors, and the like.
  • semiconductor chips which may include a memory, a logic circuit, Active devices such as power devices, bipolar devices, individual MOS transistors, and microelectromechanical systems (MEMS), or even photovoltaic devices such as light-emitting diodes, may also be passive devices such as resistors, capacitors, and the like.
  • a chip (eg, the first chip 101, the second chip 201, and a third chip mentioned later) is formed on the front side of the corresponding wafer by a suitable process well known to those skilled in the art, that is, formed on the semiconductor lining by a semiconductor process On the bottom, for the sake of simplicity, the chip is simply shown in the form of a box (for example, the first chip 101, the second chip 201 and the third chip mentioned later), but it is conceivable that the present invention
  • the structure of the chip involved may include a plurality of constituent elements and a metal interconnect structure or the like, wherein the metal interconnect structure may include a plurality of metal layers and contact holes electrically connecting adjacent metal layers, and adjacent chips may be Separated by a dielectric layer formed on the front surface of the wafer, a structure similar to that in which each of the first chip 101 and the second chip 201 shown in FIG. 1A is embedded in the front surface of the corresponding wafer is formed.
  • the dielectric layer may be a single dielectric layer or a multilayer dielectric layer.
  • the material of the dielectric layer may be any suitable dielectric material well known to those skilled in the art, including but not limited to SiO 2 , fluorocarbon (CF), carbon-doped silicon oxide (SiOC) or silicon carbonitride (SiCN), and the like.
  • first chip 101 and the second chip 201 may also be a plurality of chips of different structures formed in the front side of the wafer, and functions differently.
  • the front side of the wafer refers to the side of the wafer on which the chip is formed
  • the back side refers to the surface of the wafer opposite to the front side.
  • the front side and the back side of the wafer are not special. In the case of the description, reference is made to the above explanation.
  • both the first chip 101 and the second chip 201 may also be chips of the same structure and function.
  • step two is performed to join the two wafers that need to be joined together.
  • the back side of one of the two wafers that need to be bonded together may be selectively thinned before the bonding, for example, for the first wafer 100 or the second wafer 200
  • the back side is subjected to a thinning process so that the thickness of the thinned wafer reaches a target value.
  • the thickness of the thinned wafer is, for example, between 10 ⁇ m and 100 ⁇ m, and the thickness may be adjusted accordingly according to the technical node, and is not specifically limited herein.
  • the step of performing a thinning process on the back side of one of the wafers includes providing a support substrate (not shown), which may be Any suitable substrate known to those skilled in the art, such as a semiconductor substrate, a glass substrate, a ceramic substrate, etc., joins the support substrate to the front side of the wafer to be thinned, which bonding can use any suitable bonding means, such as Temporary bonding or bonding, for example, bonding the supporting substrate and the front surface of the wafer to be thinned using a bonding layer, which may be, but not limited to, an organic polymer material or an ultraviolet-densable organic material;
  • the back surface of the thinned wafer is further subjected to a thinning process, and finally the thinned wafer is separated from the supporting substrate, and a suitable removal method is selected according to the bonding method used, for example, a high temperature or ultraviolet irradiation method to make the key
  • the first wafer 100 and the second wafer 200 may be first bonded, for example, as shown in FIG. 1B, the front side of the first wafer 100 and the front side of the second wafer 200.
  • a back surface of one of the wafers (for example, the first wafer 100 or the second wafer 200) is thinned to make the thinned wafer The thickness reaches the target value.
  • the front side of one of the two wafers is oppositely bonded to the back side of the other wafer.
  • the front side of the first wafer 100 and the second wafer are The back sides of the 200 are relatively joined together, and then the back side of the wafer facing away from the outside (for example, the second wafer 200) is selectively thinned to achieve a target thickness of the thinned wafer.
  • the back and back sides of the two wafers are relatively joined together, that is, the back and back sides of the two wafers to be joined are relatively joined together, for example, as shown in FIG. 2B,
  • the back surfaces of a wafer 100 and the second wafer 200 are relatively bonded together, and the back surface of one of the wafers (for example, the first wafer 100 or the second wafer 200) is selectively thinned before bonding. In order to achieve the target value of the thickness of the thinned wafer.
  • the wafer (the first wafer 100, the second wafer 200 or the subsequent third wafer, etc.) can be processed by any suitable thinning method well known to those skilled in the art.
  • the thinning process for example, the thinning process is at least one of a mechanical grinding process, a chemical mechanical polishing process, or an etching process. To avoid repetition, the method of thinning is not described in the subsequent embodiments.
  • Bonding of the first wafer 100 and the second wafer 200 may be achieved by any suitable method, such as using a bonding process in which two wafers are passed through a fusion bonding process, silicon silicon direct bonds Bonding in a bonding process or bonding process, wherein a fusion bonding process, particularly a low temperature fusion bonding process, is preferably used to avoid failure of the device due to an excessively high bonding process, wherein the low temperature fusion bonding process
  • the temperature can be below 400 ° C, for example, the temperature of the low temperature fusion bonding process is between 100 and 250 ° C.
  • the first wafer 100 and the second wafer 200 may also be bonded together by a bonding process, such as bonding the first wafer and the second wafer together by an adhesive layer, exemplarily,
  • the adhesive layer may be an organic thin film, and the organic thin film may include various organic film layers, such as a die attach film (DAF), a dry film, or a photoresist.
  • DAF die attach film
  • the thickness of the bonding layer is set as needed, and the number of layers of the bonding layer is not limited to one layer, but may be two or more layers.
  • the relative position of the second chip 201 and the first chip 101 can be reasonably set according to the device type and size.
  • the first chip 101 and the second chip 201 can be overlapped on the upper and lower portions, or
  • the second chip 201 is disposed in an area outside the first chip 101 to completely align the second chip 201 and the first chip 101 to facilitate execution of a subsequent plug process.
  • FIG. 1C illustrates that after the first wafer 100 and the second wafer 200 are bonded, in order to reduce the size of the integrated device, the back surface of the first wafer 100 or the second wafer 200 is also performed.
  • a thinning process wherein the thinning process can be applied to the first wafer 100 or the second wafer that is intended to form the first plug and the second plug.
  • the second wafer is thinned from the back surface of the second wafer 200 to a target thickness, and the target thickness is The actual process needs to be determined, and is not specifically limited herein.
  • the first plug and the second plug are formed in the first wafer, the first crystal is opposite to the back surface of the first wafer 100.
  • the circle 100 is thinned to a target thickness which is determined according to actual process needs.
  • step three is performed to form a plug electrically connected to the chips in the two wafers.
  • a method of forming the plug includes forming a via in at least one of two wafers bonded together, for example, as shown in FIGS. 1D and 2A, in two When the wafers are bonded together, at least one of the wafers is etched from the surface of one of the wafers to form a via hole for forming a plug electrically connected to the corresponding chip, and may be in any one of the wafers Forming via holes, or forming via holes in two of the wafers, that is, etching the corresponding wafers from the exposed surfaces of the two wafers to form via holes, filling the via holes with conductive The material forms the plug and is electrically connected to the corresponding chip.
  • a plug may be formed in the surface of any one of the two wafers bonded together, for example, as shown in FIGS. 1D and 2A, at the first wafer 100 or the A plurality of first plugs 1021 and a plurality of second plugs 1022 are formed in the second wafer 200, wherein at least one of the plurality of first chips 101 electrically connects at least one of the first plugs 1021, at least one of the plurality of second chips 201 electrically connects at least one of the second plugs 1022.
  • the first plug 1021 is used to implement electrical connection between the first chip 101 and an external circuit
  • the second plug 1022 is used to implement electrical connection between the second chip 201 and an external circuit
  • FIG. 1D A case where one first chip 101 is electrically connected to one of the first plugs 1021 and one second chip 201 is electrically connected to one of the second plugs 1022 is shown, but a plurality of plugs are electrically connected to each of the other chips. The same applies to the present invention.
  • the plugs may be any suitable metal plug or through silicon via (TSV) well known to those skilled in the art.
  • the material of the metal plug may include, but is not limited to, at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, Sn, W, and Al, and the material of the through silicon via may include doping. Polysilicon or undoped polysilicon, etc.
  • the first plug 1021 and the second plug 1022 may be formed using any suitable method known to those skilled in the art, and in one example, the method of forming the first plug and the second plug includes: first in the second crystal A patterned mask layer (not shown) is formed on the back side of the circle 200.
  • the mask layer uses a photoresist mask material, and a predetermined formation is defined in the patterned photoresist mask material.
  • the etching process may be a wet etching or a dry etching process, wherein a dry method is preferably used. Etching process.
  • the patterned mask layer is removed, for example, using a ashing method to remove the photoresist mask material, and finally, a conductive material (such as a metal material or polysilicon) is formed to fill the first via hole and the second via hole to form a first plug and a second plug, wherein the physical vapor deposition method (PVD), chemical vapor deposition (CVD), sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process may be used Conductive material.
  • PVD physical vapor deposition method
  • CVD chemical vapor deposition
  • sputtering electrolytic plating
  • electroless plating electroless plating
  • the first plug 1021 extends from the back surface of the second wafer 200 toward the front surface until it is electrically connected to the first chip 101 corresponding thereto, and the second plug 1022 is from the The back surface of the second wafer 200 extends toward the front surface until it is electrically connected to the corresponding second chip 201.
  • first plug 1021 and the second plug 1022 are formed in the second wafer 200 is mainly taken as an example, but it is conceivable that the first method can also be formed on the first wafer by a similar method. Plug 1021 and second plug 1022.
  • the plug when the formed plugs have different depths, the plug may be formed by performing a photolithography process a plurality of times, including: forming a first patterned mask layer on one of the wafers Defining a position of the first plug; etching the wafer with the first patterned mask layer as a mask to form a first via having a first depth; removing the first patterned a mask layer; forming a second patterned mask layer on the surface of the wafer on which the first via hole is formed, defining a position of the second plug; using the second patterned mask layer as a mask, Etching the wafer to form a second via having a second depth; removing the second patterned mask layer; filling the first via and the second via with a conductive material forming portion
  • the first plug and the second plug are described.
  • the first depth and the second depth may be reasonably selected according to actual processes.
  • a plug may also be formed in each of the two wafers joined together, for example, the step of forming a plug includes: forming a first patterned mask on one of the wafers (eg, the first wafer) a film layer defining a position of the first plug; etching the wafer (eg, the first wafer) with the first patterned mask layer as a mask to form a first via hole; removing the first layer a patterned mask layer; filling the first via hole with a conductive material to form the first plug, and electrically connecting with the corresponding chip, wherein the corresponding chip may be the first chip on the first wafer Or a second chip on the second wafer; forming a second patterned mask layer on the other wafer (eg, the second wafer), defining a location of the second plug;
  • the mask layer is a mask, the wafer (eg, a second wafer) is etched to form a second via hole; the second patterned mask layer is removed; and the second via hole is filled
  • the plug is formed above the corresponding chip, for example, as shown in FIG. 1D, a first plug 1021 is formed over the corresponding first chip 101, and the second plug 1022 is formed in a corresponding Above the second chip 201.
  • the plug may be formed on one side of the corresponding chip, and before forming the plug, further comprising forming an interconnection (not shown), electrically connecting with the corresponding chip, and Electrically connected to the plug on one side of the corresponding chip, that is, the corresponding chip and plug are connected by an interconnect, wherein the method of forming the interconnect may be any suitable method known to those skilled in the art. Therefore, the interconnect line may include a plurality of metal layers and contact holes connecting adjacent metal layers, wherein the material of the interconnect lines may be any suitable conductive material, such as a metal material, including But not limited to copper or aluminum.
  • step four is performed to form a redistribution interconnect structure electrically connecting the plugs.
  • the surfaces of the first wafer 100 or the second wafer 200 formed with the first plugs 1021 and the second plugs 1022 are formed to be spaced apart from each other.
  • the first redistribution interconnect structure 103 wherein the first redistribution interconnect structure 103 electrically connects at least one of the first plugs 1021 and/or at least one of the second plugs 1022.
  • the rewiring interconnect structure (eg, the first redistribution interconnect structure 103 and the subsequent second redistribution interconnect structure, etc.) can be any suitable metal material well known to those skilled in the art, which can include, but is not limited to, At least one metal of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, Sn, W, and Al.
  • the first redistribution interconnect structure 103 can include a rewiring layer and pads, or include pads.
  • the first redistribution interconnect structure 103 may be formed using any suitable method, for example, forming a metal material layer to cover the back surface of the second wafer 200, wherein a physical vapor deposition method (PVD), a chemical vapor deposition method may be used. Forming the metal material layer by (CVD), sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process, and then removing a portion of the metal material layer by etching to form a plurality of spaced apart layers The first redistribution interconnect structure 103.
  • PVD physical vapor deposition method
  • CVD chemical vapor deposition method
  • first redistribution interconnect structure 103 is electrically connected to the corresponding plug in FIG. 1E, it is conceivable that the first redistribution interconnect structure may also be implemented in order to achieve more electrical connection modes. 103 electrically connects at least one first plug 1021 and at least one second plug 1022.
  • metal interconnect lines may also be formed over the first redistribution interconnect structure 103 to achieve more chip connections, wherein typically the metal interconnect lines comprise more metal layers located in different layers. And the metal layers of the different layers are electrically connected by plugs or metal plugs disposed between adjacent layers.
  • the method further includes the steps of: forming an interlayer dielectric layer 104 to cover the first redistribution interconnect structure 103 and the first crystal
  • the circle 100 or the back side of the second wafer 200 forms an interlayer dielectric layer 104 to cover the first redistribution interconnect structure 103 and the back surface of the second wafer 200.
  • the interlayer dielectric layer 104 for example, SiO 2 , fluorocarbon (CF), carbon-doped silicon oxide (SiOC), or silicon carbonitride (SiCN) or the like can be used. Alternatively, a film in which a SiCN film is formed on a fluorocarbon (CF) or the like may be used. Fluorocarbons contain fluorine (F) and carbon (C) as main components. As the fluorocarbon, a substance having an amorphous (non-crystalline) structure can also be used. As the interlayer dielectric layer 104, a porous structure such as carbon-doped silicon oxide (SiOC) can also be used.
  • the interlayer dielectric layer 104 may be formed using a chemical vapor deposition method, a physical vapor deposition method, an atomic layer deposition method, or the like.
  • the top surface of the interlayer dielectric layer 104 may be flush with the top surface of the first redistribution interconnect structure 103, or the top surface of the interlayer dielectric layer 104 may be higher than the first surface.
  • the top surface of the interconnect structure 103 is redistributed.
  • the surface of the interlayer dielectric layer 104 can also be selectively planarized to obtain a flat surface, which can be a chemical mechanical polishing or other suitable method.
  • the wafer may be cut along the scribe line to Dividing a plurality of chips integrated on a wafer into separate units, for example, each unit includes at least one first chip and at least one second chip, the unit forming a system or subsystem that provides multiple functions. This function depends on the functionality of the actual integrated chip.
  • the above steps show the main process steps required to bond the first wafer and the second wafer with the chip-formed wafers together, and more wafers can be integrated by the method of the present invention. Together, to achieve more chip packaging.
  • the packaging method of the present invention can also be used to stack and bond at least three wafers on which chips are formed in the upper and lower stacking directions.
  • FIGS. 1A to 1E, 2A, 3A to 3C, and 4A to 4B a packaging method in which at least three wafers on which chips are formed are stacked and joined together in the upper and lower stacking directions will be described with reference to FIGS. 1A to 1E, 2A, 3A to 3C, and 4A to 4B.
  • a third wafer 300 is provided.
  • At least one third wafer 300 formed with a third chip 301 may be provided, and a plurality of third chips 301 spaced apart from each other are disposed within a front surface of each of the third wafers.
  • the third wafer 300 is formed to complete the device, and a plurality of device wafers of the third chip 301 are respectively formed.
  • the device wafer can be fabricated by using integrated circuit fabrication technology according to a corresponding layout design, such as forming a device such as NMOS and/or PMOS by deposition, etching, etc. on a semiconductor wafer, and forming a dielectric layer and a metal layer.
  • the interconnect layer and the pads on the interconnect layer are structured to form a third chip 301 arranged in an array in the semiconductor wafer.
  • the third wafer 300 includes a semiconductor substrate, and the material of the semiconductor substrate may use any one or more of the semiconductor materials exemplified in the foregoing Embodiment 1.
  • the third chip 301 is formed on the front surface of the corresponding wafer by a suitable process well known to those skilled in the art to form a structure similar to that shown in FIG. 3A in which each of the third chips 301 is embedded in the front surface of the corresponding wafer. .
  • the third chip 301 can also be a plurality of chips of different structures formed in the front side of the wafer, and different functions of the chips.
  • the third chip 301 can also be a chip of the same structure and function.
  • the new wafer is continuously bonded to one of the already bonded wafers, one of the two wafers to be bonded together, one of which is a new wafer and the other is already bonded One of the two wafers together.
  • the new wafer refers to a wafer that needs to continue to be joined.
  • the new wafer refers to a third wafer 300, and the third wafer 300 is already bonded to One of the first wafer 100 and the second wafer 200 are joined together (for example, the structure shown in FIG. 1E).
  • the case where the wafer 300 is bonded to the first wafer 100 of the two wafers that have been joined together as shown in FIG. 1E mainly includes the following steps A1 to A3:
  • step A1 is performed to join the third wafer and the surface on which the first redistribution interconnect structure 103 is formed, wherein the bonding method can use the first wafer mentioned in the foregoing implementation Any one of methods of joining to the second wafer.
  • a step of forming a bonding layer 105 on the front surface of the third wafer 300 is also included before bonding.
  • the material of the bonding layer 105 comprises a silicon oxide layer, including oxidation by a thermal CVD manufacturing process or a high density plasma (HDP) or a process formed by a tetraethyl orthosilicate (TEOS) manufacturing process.
  • the material layer of silicon may also be a silicon oxide layer formed by a thermal oxidation process, or may be a silicon oxide layer prepared by a low process temperature oxide (LTO) process temperature of less than 200 ° C.
  • LTO low process temperature oxide
  • a bonding process is performed to bond the bonding layer 105 and the interlayer dielectric layer 104 together to effect bonding of the third wafer 300 and the second wafer.
  • the bonding process is a fusion bonding process, in particular, a low-temperature fusion bonding process, and a pressure can be applied during the bonding process, for example, a bonding pressure of 1 to 10 N is applied, wherein the bonding time can be 10 to 60 s. .
  • a pressure can be applied during the bonding process, for example, a bonding pressure of 1 to 10 N is applied, wherein the bonding time can be 10 to 60 s. .
  • Si-O bonds are formed to interconnect the two wafers.
  • the third wafer 300 may also be thinned to a target thickness from the back side of the third wafer 300 after bonding.
  • the target thickness is determined according to the actual process requirements, and is not specifically limited herein.
  • step A2 is performed to form a plurality of third plugs 106 spaced apart from each other in the third wafer 300, wherein a portion of the third plugs 106 are electrically connected to the first redistribution interconnect structure 103
  • the third plug 106 is electrically connected to the third chip 301.
  • the third plug 106 extends from the back surface of the third wafer 300 to the front side, and each of the first redistribution interconnect structures 103 electrically connects at least one of the third plugs 106, each of the first The three chips 301 are electrically connected to at least one of the third plugs 106, wherein a third plug 106 electrically connected to the first redistribution interconnect structure 103 extends through the third wafer and the bonding layer 105 .
  • the third plug 106 can be formed by any suitable method.
  • the third plug can be formed by referring to the forming method of the first plug and the second plug in the first embodiment.
  • step A3 is performed to form a second redistribution interconnect structure 107 on the back side of the third wafer 300.
  • the second redistribution interconnect structure may include a rewiring layer and a pad, or include a pad for connecting the first chip, the second chip, and the third chip to an external circuit, the second Redistribution interconnect structure 107 electrically connects said third plug 106.
  • the second redistribution interconnect structure 107 can be formed by any suitable method.
  • the method for forming the second redistribution interconnect structure 107 can refer to the method of the first redistribution interconnect structure 107 in the first embodiment. Make a statement.
  • the method further includes the step of sequentially bonding a plurality of wafers on the back surface of the third wafer, wherein the plurality of wafers are formed with a plurality of chips spaced apart from each other, and may include step B1 to form an interlayer a dielectric layer covering the second redistribution interconnect structure, and step B2, bonding another new wafer having a plurality of chips spaced apart from each other to the surface on which the interlayer dielectric layer is formed, for example
  • a bonding layer may be formed on the front surface of the other new wafer, and another new wafer and a surface on which the interlayer dielectric layer is formed are bonded by a bonding process to achieve a more Multi-wafer packaging, step B3, thinning another new wafer from the back side of the other new wafer to a target thickness, step B4, forming a space between the other new wafers a plurality of plugs, the partial plug electrically connecting the second redistribution interconnect structure, the partial plug electrical
  • a passivation layer 108 is formed to cover the second redistribution interconnect structure 107 and the back side of the third wafer 300.
  • the material of the passivation layer 108 may use any suitable insulating material, for example, the passivation layer 108 uses an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, which may be deposited by chemical vapor deposition,
  • the passivation layer 108 is deposited by a deposition method such as physical vapor deposition or atomic layer deposition; an insulating layer such as a layer containing polyvinylphenol, polyimide, or siloxane or the like may also be used.
  • Polyvinylphenol, polyimide, or siloxane can be effectively formed by a droplet discharge method, a printing method, or a spin coating method.
  • Siloxanes can be classified according to their structure into silica glass, alkylsiloxane polymers, alkylsilsesquioxane polymers, silsesquioxane hydride polymers, An alkylsilsesquioxane hydride polymer or the like.
  • the insulating material may be formed of a material including a polymer having a Si-N bond (polysilazane). Further, these films may be laminated to form a passivation layer.
  • the top surface of the passivation layer 108 is higher than the top surface of the second redistribution interconnect structure 107.
  • the thickness of the passivation layer may be any suitable thickness, which is not specifically limited herein.
  • the surface of the passivation layer 108 may also be selectively chemically ground after deposition of the passivation layer 108 to obtain a flat surface.
  • a passivation layer 108 can be formed to cover the redistribution interconnect structure at the top layer (the redistribution interconnect structure includes pads).
  • an opening 109 is formed in the passivation layer 108 above each of the second redistribution interconnect structures 107, the opening 109 exposing a portion of the second redistribution interconnect structure 107, that is, the pads included in the second redistribution interconnect structure 107 are exposed.
  • the opening 109 of the pad surface which may be formed using any suitable method, in one example, first forming a patterned mask on the surface of the passivation layer 108. a layer, such as a photoresist layer, defining a pattern of openings, and then etching the exposed passivation layer 108 with the patterned mask layer as a mask until a second redistribution is exposed.
  • the surface of the interconnect structure 107 is formed to form the opening 109, and then the patterned mask layer is removed, for example, by a ashing or wet etching method to remove the mask layer of the photoresist material.
  • the back surface of the third wafer 300 and the second wafer 200 may be bonded, or may be in the opposite
  • the back surface of the third wafer 300 is bonded to the first wafer 100, and the same bonding method as the above method and a method of forming the plug may be used. The formation method will not be described here.
  • the structure shown in FIG. 2A can also be bonded to the third wafer 300, and the bonding method can use the same bonding method as the foregoing method and the method of forming the plug. Referring to the method of forming the plug described above, no further details are provided herein.
  • the wafer level system packaging method of the present invention has been completed.
  • other steps may be included.
  • the wafer may be cut along the scribe line to integrate.
  • the plurality of chips on the wafer are divided into separate units, for example, each unit includes at least one first chip and at least one second chip and at least one third chip, the unit forming a system capable of providing multiple functions Or subsystem, this function depends on the functionality of the actual integrated chip.
  • the wafer level system packaging method of the present invention combines a wafer level package and a system package method, and simultaneously realizes integration of a plurality of chips and completes package manufacturing advantages on a wafer, and has a drastically reduced package.
  • the advantages of structure area, reduced manufacturing cost, optimized electrical performance, batch manufacturing, etc., can significantly reduce the workload and equipment requirements, and improve the efficiency and yield of the package.
  • Still another aspect of the present invention provides a wafer level system package structure obtained by the above packaging method.
  • the package structure of the present invention includes at least two wafers formed with chips stacked and bonded together in a direction perpendicular to the surface of the wafer, for example, as shown in FIGS. 3C, 4A, and 4B, including the first wafer 100.
  • the second wafer 200 and the third wafer 300 are provided with a plurality of first chips 101 spaced apart from each other on the front surface of the first wafer 100, and are spaced apart from each other on the front surface of the second wafer 200.
  • the plurality of second chips 201 are provided with a plurality of third chips 301 spaced apart from each other on the front surface of the third wafer 300.
  • two wafers bonded to each other one of which has a front side that is oppositely joined to the other, for example, as shown in FIGS. 1E and 3C, the front side of the first wafer 100
  • the front faces of the second wafers 200 are joined.
  • two wafers bonded to each other are bonded to each other with the front side of the other wafer, for example, the front side of the first wafer and the back side of the second wafer are relatively joined together. Or, as shown in FIG. 2A, the back side of the first wafer 100 and the back side of the second wafer 200 are relatively joined together.
  • the back side of one of the first wafers is oppositely joined to the back side of the other wafer, or, as shown in FIG. 2B, the back side of the first wafer 100 is relatively joined to the back side of the second wafer 200.
  • the package structure of the present invention further includes a plug, two chips in the wafer bonded to each other, electrically connected through the plug, for example, as shown in FIG. 3C, the first wafer 100 Bonding with the second wafer 200, the first plug 1021 is electrically connected to the first chip 101 in the first wafer 100, and the second plug 1022 is electrically connected to the second chip 201 in the second wafer 200.
  • a plurality of third plugs 106 are electrically connected to the third chip 301 in the third wafer 300, and the plurality of third plugs are further electrically connected to the second chip 201, and the plurality of third plugs 106 are further The first chip 101 is further electrically connected.
  • the plug is formed above the corresponding chip, for example, a plurality of first plugs 1021 and a plurality of second plugs 1022 are formed in the second wafer 200, wherein The first plug 1021 is formed above the corresponding first chip 101, and the second plug 1022 is formed above the corresponding second chip 201.
  • the first plug 1021 is used to realize electrical connection between the first chip 101 and an external circuit
  • the second plug 1022 is used to implement electrical connection between the second chip 201 and an external circuit
  • FIG. 3C A case where one first chip 101 is electrically connected to one of the first plugs 1021 and one second chip 201 is electrically connected to one of the second plugs 1022 is shown, but a plurality of plugs are electrically connected to each of the other chips. The same applies to the present invention.
  • the first plug 1021 extends from the back surface of the second wafer 200 toward the front surface until it is electrically connected to the corresponding first chip 101
  • the second The plug 1022 extends from the back surface of the second wafer 200 toward the front surface until it is electrically connected to the corresponding second chip 201.
  • the plug is formed on one side of the corresponding chip, and is further formed with an interconnection line electrically connected to the corresponding chip and electrically connected to the plug on one side of the corresponding chip .
  • the interconnect line may include several layers of metal layers and contact holes connecting adjacent metal layers, wherein the material of the interconnect lines may be any suitable conductive material, such as a metal material, including but not limited to copper or Aluminum and so on.
  • a redistribution interconnect structure electrically connecting the plugs is also included, located at the top of the plug.
  • a first redistribution interconnect structure 103 is formed on top of the first plug 1021 and the second plug 1022, wherein the first redistribution interconnect structure 103 electrically connects at least one of the first plugs Plug 1021 and/or at least one of said second plugs 1022.
  • first redistribution interconnect structure 103 is electrically connected to the corresponding plug in FIG. 3C, it is conceivable that the first redistribution interconnect structure 103 can also be made in order to achieve more electrical connection. At least one first plug 1021 and at least one second plug 1022 are electrically connected.
  • the first redistribution interconnect structure 103 can include a rewiring layer and pads, or include pads.
  • an interlayer dielectric layer 104 such as an interlayer dielectric layer, covering the first redistribution interconnect structure 103 and the back side of the first wafer 100 or the second wafer 200 is further included 104 covers the first redistribution interconnect structure 103 and the back side of the second wafer 200.
  • the top surface of the interlayer dielectric layer 104 may be flush with the top surface of the first redistribution interconnect structure 103, or the top surface of the interlayer dielectric layer 104 may be higher than the first surface.
  • the top surface of the interconnect structure 103 is redistributed.
  • a third wafer 300 is further included, the third wafer being bonded to a surface on which the first redistribution interconnect structure is formed, for example, the third wafer 300 and the second crystal The back of the circle 200 is joined.
  • a bonding layer 105 formed at the interface of the bonded wafers is also included.
  • the bonding layer 105 and the interlayer dielectric layer 104 are bonded together to effect bonding of the third wafer 300 and the second wafer 200.
  • a plurality of third plugs 106 spaced apart from each other are formed in the third wafer 300, wherein a portion of the third plugs 106 are electrically connected to the first redistribution interconnect structure 103, A portion of the third plug 106 electrically connects the third chip 301.
  • the back surface of the third wafer 106 extends toward the front side, and each of the first redistribution interconnect structures 103 electrically connects at least one of the third plugs 106, each of the third The chip 301 is electrically connected to at least one of the third plugs 106.
  • the third plug 106 electrically connected to the first redistribution interconnect structure 103 extends through the third wafer and the bonding layer 105.
  • a second redistribution interconnect structure 107 is formed on the back side of the third wafer 300.
  • the second redistribution interconnect structure may include a rewiring layer and a pad, or include a pad for connecting the first chip, the second chip, and the third chip to an external circuit.
  • a passivation layer covering a surface of the wafer on which the redistribution interconnect structure is formed is further formed to cover the second redistribution interconnect structure 107 and The passivation layer 108 of the back surface of the third wafer 300.
  • the passivation layer can cover a redistribution interconnect structure at the top layer (the redistribution interconnect structure includes pads).
  • an opening 109 is formed in the passivation layer 108 above each of the second redistribution interconnect structures 107, the opening 109 exposing a portion of the second redistribution interconnect structure 107.
  • the wafer level system package structure of the present invention has better performance due to the use of the wafer level system packaging method described above.

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Abstract

一种晶圆级系统封装方法以及封装结构，封装方法用于将至少两片形成有芯片（101,201）的晶圆（100,200）沿上下堆叠的方向，堆叠接合在一起，包括：将需要接合在一起的两片晶圆相接合；在接合之后，形成插塞（1021,1022），与两片晶圆中的芯片电连接。该晶圆级系统封装方法，使用晶圆级封装和系统封装方法相结合，同时实现了多种芯片的集成和在晶圆上完成封装制造的优势，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求，提高了封装的效率和良率。由该晶圆级系统封装方法制备获得的封装结构同样具有更高的性能和良率。

Description

一种晶圆级系统封装方法以及封装结构
说明书
技术领域
本发明涉及半导体技术领域，具体而言涉及一种晶圆级系统封装方法以及封装结构。
背景技术
系统封装(System in Package，简称SiP)将多个不同功能的有源元件，以及无源元件、微机电系统(MEMS)、光学元件等其他元件，组合到一个单元中，形成一个可提供多种功能的系统或子系统，允许异质IC集成，是最好的封装集成技术。相比于片上系统(System On Chip，简称SoC)封装，SiP集成相对简单，设计周期和面市周期更短，成本较低，可以实现更复杂的系统。
与传统的SiP相比，晶圆级系统封装(wafer level package,简称WLP)是在晶圆上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。
鉴于晶圆级系统封装的显著优势，如何能够更好的实现晶圆级系统封装一直是业界内研究的热点。
发明内容
鉴于晶圆级系统封装的显著优势，如何能够更好的实现晶圆级系统封装是本发明要解决的技术问题。
本发明一方面提供一种晶圆级系统封装方法，用于将至少两片形成有芯片的晶圆沿上下堆叠的方向，堆叠接合在一起，包括：
将需要接合在一起的两片所述晶圆相接合；
在所述接合之后，形成插塞，与两片所述晶圆中的芯片电连接。
示例性地，将两片所述晶圆的正面与正面相对接合在一起，或者，将其中一个的正面与另一个的背面相对接合在一起，进行所述接合步骤之后，形成所述插塞之前，还包括：
对其中一个背面朝外的晶圆背面进行减薄工艺。
示例性地，将所述两片晶圆的背面与背面相对接合在一起，进行所述接合步骤之前，还包括：
对其中一个晶圆的背面进行减薄工艺。
示例性地，所述形成插塞的步骤包括：
在接合在一起的两片所述晶圆的其中至少一个晶圆内形成通孔；
在所述通孔中填充导电材料形成所述插塞，与对应的所述芯片电连接。
示例性地，所述插塞形成在对应芯片的上方；
或者，所述插塞形成在对应芯片的一侧，在形成所述插塞之前，还包括，形成互连线，与对应的芯片电连接，以及与对应芯片一侧的插塞电连接。
示例性地，在形成所述插塞之后，还包括：
形成再分布互连结构，电连接所述插塞。
示例性地，所述再分布互连结构包括：再布线层和焊盘，或者，包括焊盘。
示例性地，所述方法用于将两片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起。
示例性地，所述方法用于将至少三片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起。
示例性地，所述方法还包括：
继续将新的所述晶圆与已经接合在一起的晶圆的其中一个接合，
所述需要接合在一起的两个晶圆中，其中一个为新的晶圆，另一个为已经接合在一起的两个晶圆中的其中一个。
示例性地，两片晶圆通过熔融键合工艺、硅硅直接键合工艺或者粘接工艺相键合。
示例性地，所述减薄工艺为:机械研磨工艺、化学机械研磨或者刻蚀工艺中的至少一种。
本发明再一方面还提供一种晶圆级系统封装结构，包括：
至少两片形成有芯片的晶圆，沿垂直晶圆表面的方向堆叠接合在一起；
插塞，相互接合在一起的两片所述晶圆中的芯片，通过所述插塞电连接。
示例性地，相互接合在一起的两片所述晶圆，其中一个的正面与另一个的正面相对接合在一起；
或者，其中一个的正面与另一个的背面相对接合在一起；
或者，其中一个的背面与另一个的背面相对接合在一起。
示例性地，所述插塞形成在对应芯片的上方；
或者，所述插塞形成在对应芯片的一侧，并且还形成有互连线，所述互连线与对应的芯片电连接，以及与对应芯片一侧的所述插塞电连接。
示例性地，还包括：
电连接所述插塞的再分布互连结构，位于所述插塞的顶部。
示例性地，所述再分布互连结构包括：再布线层和焊盘，或者，包括焊盘。
示例性地，还包括：形成在相接合的所述晶圆的界面处的键合层。
本发明的封装方法在晶圆上完成封装制造并且将多个芯片集成在一起，因此实现了晶圆级封装和系统封装方法的结合，相比传统封装方式(先切割再进行封装和测试，而封装后至少增加原芯片20％的体积)，本申请将至少两片形成有芯片的晶圆沿上下堆叠的方法，堆叠接合在一起，也即实现芯片的上下堆叠封装，并在晶圆上完整封装后再切割成独立的多芯片模组，能够保持原芯片的大小，因此能够大幅减小封装结构的面积，通过插塞电连接相应芯片，电路布线的线路短，可有效减少电流损耗，因此优化了电性能，由于本发明的方法以晶圆形式的批量生产工艺进行制造，封装加工效率更高；另外，由于能够充分利用晶圆的制造设备，无需另建封装生产线，因此可明显的降低设备的需求；本发明的封装方法将形成有芯片的晶圆直接进入封装工序，中间环节大大减少，周期缩短很多，降低制造成本和工作量，提高了封装的效率和良率。由本发明的晶圆级系统封装方法制备获得的封装结构同样具有更高的性能和良率。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附 图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1A至图1E示出了本发明一个具体实施方式将两片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起的方法依次实施所获得结构的剖面示意图；
图2A示出了本发明一个具体实施方式将一片晶圆的正面和另一片晶圆的背面接合所获得的结构的剖面示意图；
图2B示出了本发明一个具体实施方式将两片晶圆的背面相接合所获得的结构的剖面示意图；
图3A至图3C示出了本发明一个具体实施方式将三片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起的方法依次实施所获得结构的剖面示意图；
图4A示出了本发明另一个具体实施方式将三片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起所获得结构的剖面示意图；
图4B示出了本发明再一个具体实施方式将三片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起所获得结构的剖面示意图；
图5示出了本发明一个具体实施方式的晶圆级系统封装方法的流程图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与 之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样， 通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
为了彻底理解本发明，将在下列的描述中提出详细步骤和结构，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
鉴于晶圆级系统封装的显著优势，本发明提出一种改进了的晶圆级系统封装方法，用于将至少两片形成有芯片的晶圆沿上下堆叠的方向，堆叠接合在一起，如图5所示，其主要包括以下步骤：
步骤S1，将需要接合在一起的两片所述晶圆相接合；
步骤S2，在所述接合之后，形成插塞，与两片所述晶圆中的芯片电连接。
本发明的封装方法在晶圆上完成封装制造并且将多个芯片集成在一起，因此实现了晶圆级封装和系统封装方法的结合，相比传统封装方式(先切割再进行封装和测试，而封装后至少增加原芯片20％的体积)，本申请将至少两片形成有芯片的晶圆沿上下堆叠的方法，堆叠接合在一起，也即实现芯片的上下堆叠封装，并在晶圆上完整封装后再切割成独立的多芯片模组，能够保持原芯片的大小，因此能够大幅减小封装结构的面积，通过插塞电连接相应芯片，电路布线的线路短，可有效减少电流损耗，因此优化了电性能，由于本发明的方法以晶圆形式的批量生产工艺进行制造，封装加工效率更高；另外，由于能够充分利用晶圆的制造设备，无需另建封装生产线，因此可明显的降低设备的需求；本发明的封装方法将形成有芯片的晶圆直接进入封装工序，中间环节大大减少，周期缩短很多，降低制造成本和工作量，提高了封装的效率和良率。
实施例一
下面，参考图1A至图1E对本发明的晶圆级系统封装方法做详细描述，其中，图1A至图1E示出了本发明一个具体实施方式将两片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起的方法依次实施所获得结构的剖面示意图。
作为示例，本发明的晶圆级系统封装方法，用于将至少两片形成有芯片的晶圆沿上下堆叠的方向，堆叠接合在一起，例如，用于将两片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起，包括以下步骤：
首先，执行步骤一，如图1A所示，提供形成有第一芯片101的第一晶圆100和形成有第二芯片201的第二晶圆200，例如，在所述第一晶圆100的正面以内设置有彼此间隔的多个第一芯片101，在所述第二晶圆200的正面以内设置有彼此间隔的多个第二芯片201。
第一晶圆100和第二晶圆200为完成器件制作，分别形成有多个第一芯片101和多个第二芯片201的器件晶圆。该器件晶圆可以采用集成电路制作技术根据相应的布图设计进行制作，例如在半导体晶圆上通过沉积、刻蚀等工作形成诸如NMOS和/或PMOS等的器件，以及介质层和金属层构成的互连层和位于互连层之上的焊盘等结构，从而在半导体晶圆中制作呈阵列排布的第一芯片101和第二芯片201。
具体地，所述第一晶圆100、第二晶圆200均包括半导体衬底，半导体衬底可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP、InGaAs或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等，或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。
示例性地，在本发明中所涉及的芯片(例如所述第一芯片101、第二芯片201和后续提及的第三芯片)可以是任意一种半导体芯片，其可以包括存储器、逻辑电路、功率器件、双极器件、单独的MOS晶体管、微机电系统(MEMS)等有源器件，甚至也可以是发光二极管等光电器件，其也可以为无源器件，例如电阻、电容等。
芯片(例如所述第一芯片101、第二芯片201和后续提及的第三芯片)通过本领域技术人员熟知的适合的工艺形成在相应晶圆的正面，也即通过半导体工艺形成在半导体衬底上，在此为了简便，仅以一方框的形式简单示出了芯片(例如所述第一芯片101、第二芯片201和后续提到的第三芯片)，但可以想到的是本发明中所涉及的芯片的结构可以包括多个构成元件以及金属互连结构等等，其中，金属互连 结构可以包括多层金属层以及电连接相邻金属层的接触孔，相邻的芯片之间可以由形成在晶圆的正面的介电层隔开，形成类似如图1A所示的每个所述第一芯片101和第二芯片201嵌入在相应晶圆的正面内的结构。
介电层可以是单层介电层也可以是由多层介电层组成，在一个示例中，介电层的材料可以是本领域技术人员熟知的任何适合的介电材料，包括但不限于SiO 2、碳氟化合物(CF)、掺碳氧化硅(SiOC)或碳氮化硅(SiCN)等等。
值得一提的是，第一芯片101和第二芯片201还可以是形成在晶圆正面以内的多个不同结构的芯片，功能不同的芯片。
另外，本发明中晶圆的正面是指晶圆形成有芯片的一面，而所述背面则是指与所述正面相背的晶圆的表面，本发明中晶圆的正面以及背面在无特别说明的情况下均参照上述解释。
示例性地，第一芯片101和第二芯片201两者也可以是结构和功能相同的芯片。
接着，执行步骤二，将需要接合在一起的两片所述晶圆相接合。
示例性地，在进行接合之前，还可以选择性地对需要接合在一起的两片晶圆中的一个的背面进行减薄工艺，例如，对第一晶圆100或者对第二晶圆200的背面进行减薄工艺，以使减薄后的晶圆的厚度达到目标值。
值得一提的是，在本发明中，减薄后的晶圆的厚度例如在10μm至100μm之间，也可以根据技术节点的不同，对该厚度进行相应调整，在此不做具体限定。
在一个示例中，对其中一个晶圆(例如第一晶圆100或者第二晶圆200)的背面进行减薄工艺的步骤包括：提供支撑基底(未示出)，所述支撑基底可以是本领域技术人员熟知的任何适合的基底，例如半导体衬底、玻璃基底、陶瓷基底等，将所述支撑基底与待减薄的晶圆的正面进行接合，该接合可以使用任何适合的接合方式，例如临时键合或者粘接等，例如使用键合胶层将支撑基底和待减薄的晶圆的正面接合，键合胶层可以是但不限于是有机高分子材料或可紫 外变性的有机材料；再对待减薄的晶圆的背面进行减薄工艺，最后将减薄后的晶圆与支撑基底分离，根据所使用的接合方式选择适合的去除方法，例如，高温或者紫外照射的方式，使键合胶层变性失去粘性，从而将支撑基底剥离。
在一个示例中，可以首先将第一晶圆100和第二晶圆200相接合，例如，如图1B所示，将所述第一晶圆100的正面和所述第二晶圆200的正面相接合；并在进行所述接合步骤之后，形成插塞之前，对其中一个晶圆(例如第一晶圆100或者第二晶圆200)背面进行减薄工艺，以使减薄后的晶圆的厚度达到目标值。
在另一个示例中，将所述两片晶圆中，其中一个的正面与另一个的背面相对接合在一起，例如，如图2A所示，将第一晶圆100的正面与第二晶圆200的背面相对接合在一起，然后，再选择性地对背面朝外的晶圆(例如第二晶圆200)的背面进行减薄工艺，以使减薄后的晶圆的厚度达到目标值。
在再一个示例中，将所述两片晶圆的背面与背面相对接合在一起，也即将需要接合的两片晶圆的背面与背面相对接合在一起，例如，如图2B所示，将第一晶圆100和第二晶圆200的背面相对接合在一起，并且在接合之前先选择性地对其中一个晶圆(例如第一晶圆100或者第二晶圆200)的背面进行减薄工艺以使减薄后的晶圆的厚度达到目标值。
值得一提地是，在本发明中，可以使用本领域技术人员熟知的任何适合的减薄方法对晶圆(第一晶圆100、第二晶圆200或者后续的第三晶圆等)进行减薄，例如所述减薄工艺为:机械研磨工艺、化学机械研磨或者刻蚀工艺中的至少一种，为避免重复，在后续的实施例中不再对减薄的方法进行赘述。
可以通过任何适合的方法实现所述第一晶圆100和所述第二晶圆200的接合，例如使用键合(bonding)工艺，其中，两片晶圆通过熔融键合工艺、硅硅直接键合工艺或者粘接工艺相键合，其中，较佳地使用熔融键合，特别是低温熔融键合工艺，以避免温度过高的键合工艺导致器件的失效，其中，低温熔融键合工艺的温度可以低于400℃，例如，低温熔融键合工艺的温度介于100～250℃之间。
在一个示例中，第一晶圆100和第二晶圆200还可以通过粘接工艺接合在一起，例如通过粘接层将第一晶圆和第二晶圆粘接在一起，示例性地，所述粘接层可以为有机薄膜，有机薄膜可以包括各种有机膜层，例如芯片连接薄膜(die attach film，DAF)、干膜(dry film)或光阻等。粘接层的厚度根据需要设置，并且粘接层的层数也不限于一层，而可以是两层或更多层。
其中，第二芯片201和第一芯片101的相对位置可以根据器件类型和尺寸进行合理的设置，例如，可以使所述第一芯片101和所述第二芯片201上下部分重叠，或者，所述第二芯片201设置在所述第一芯片101之外的区域，以使所述第二芯片201和第一芯片101完全错开，以便于后续插塞工艺的执行。
图1C示出了在将第一晶圆100和第二晶圆200接合之后，为了减小集成后器件的尺寸，还对所述第一晶圆100或所述第二晶圆200的背面进行减薄工艺，其中，所述减薄工艺可以应用于预定形成所述第一插塞和所述第二插塞的所述第一晶圆100或所述第二晶圆。例如，预定在所述第二晶圆200中形成第一插塞和第二插塞，则自所述第二晶圆200的背面对第二晶圆进行减薄至目标厚度，该目标厚度根据实际工艺需要而定，在此不做具体限定，或者，预定在所述第一晶圆中形成第一插塞和第二插塞，则自所述第一晶圆100的背面对第一晶圆100进行减薄至目标厚度，该目标厚度根据实际工艺需要而定。
接着，执行步骤三，形成插塞，与两片所述晶圆中的芯片电连接。
在一个示例中，形成所述插塞的方法包括：在接合在一起的两片所述晶圆的其中至少一个晶圆内形成通孔，例如，如图1D和图2A所示，在两片晶圆接合在一起时，从一侧晶圆的表面开始，蚀刻至少其中一个晶圆以形成通孔，该通孔用于形成与对应芯片电连接的插塞，可以在其中任意一个晶圆内形成通孔，或者，也可以在其中两个晶圆内均形成通孔，也即，通过从两个晶圆露出的表面开始蚀刻相应晶圆以形成通孔，在所述通孔中填充导电材料形成所述插塞，与对应的芯片电连接。
在一个示例中，可以在接合在一起的两片晶圆中的任意一个晶圆 的表面内形成插塞，例如，如图1D和图2A所示，在所述第一晶圆100或者所述第二晶圆200中形成间隔设置的多个第一插塞1021和多个第二插塞1022，其中，所述多个第一芯片101中的至少一个电连接至少一个所述第一插塞1021，所述多个第二芯片201中的至少一个电连接至少一个所述第二插塞1022。
具体地，所述第一插塞1021用于实现第一芯片101和外部电路的电连接，所述第二插塞1022用于实现第二芯片201和外部电路的电连接，尽管图1D中仅示出了一个第一芯片101电连接一个所述第一插塞1021，一个第二芯片201电连接一个所述第二插塞1022的情况，但是对于其他的每个芯片电连接多个插塞的情况，也同样适用于本发明。
在本发明中所涉及的插塞(例如第一插塞1021、第二插塞1022和后续的第三插塞)可以是本领域技术人员熟知的任何适合的金属插塞或者硅通孔(TSV)，金属插塞的材料可以包括但不限于Ag、Au、Cu、Pd、Cr、Mo、Ti、Ta、Sn、W和Al中的至少一种金属，而硅通孔的材料可以包括掺杂的多晶硅或者未掺杂的多晶硅等。
可以使用本领域技术人员熟知的任何适合的方法形成第一插塞1021和第二插塞1022，在一个示例中，形成第一插塞和第二插塞的方法包括：可以首先在第二晶圆200的背面形成图案化的掩膜层(未示出)，较佳地，所述掩膜层使用光刻胶掩膜材料，在图案化的光刻胶掩膜材料中定义了预定形成的第一插塞和第二插塞的图案，然后以所述图案化的掩膜层为掩膜，刻蚀部分第二晶圆200，直到露出部分所述第一芯片以形成第一通孔，以及蚀刻部分所述第二晶圆200，直到露出部分所述第二芯片以形成第二通孔，该刻蚀工艺可以是湿法刻蚀或者干法刻蚀工艺，其中较佳地使用干法刻蚀工艺。随后，将图案化的掩膜层去除，例如使用灰化的方法去除光刻胶掩膜材料，最后，形成导电材料(例如金属材料或多晶硅)填充第一通孔和第二通孔，以形成第一插塞和第二插塞，其中，可以使用物理气相沉积方法(PVD)、化学气相沉积方法(CVD)、溅射、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺形成所述导电材料。
示例性地，所述第一插塞1021自所述第二晶圆200的背面向所 述正面延伸直到与其所对应的所述第一芯片101电连接，所述第二插塞1022自所述第二晶圆200的背面向所述正面延伸直到与其所对应的所述第二芯片201电连接。
在此主要以在第二晶圆200中形成第一插塞1021和第二插塞1022的情况为例进行说明，但是可以想到的是也可以通过类似的方法在第一晶圆上形成第一插塞1021和第二插塞1022。
在一个示例中，在形成的插塞具有不同的深度时，可以通过多次执行光刻工艺的方法，形成所述插塞，包括：在其中一片晶圆上形成第一图形化的掩膜层，定义第一插塞的位置；以所述第一图形化的掩膜层为掩膜，刻蚀所述晶圆，形成具有第一深度的第一通孔；去除所述第一图形化的掩膜层；继续在形成有第一通孔的晶圆的表面形成第二图形化的掩膜层，定义第二插塞的位置；以所述第二图形化的掩膜层为掩膜，刻蚀所述晶圆，形成具有第二深度的第二通孔；去除所述第二图形化的掩膜层；在所述第一通孔和所述第二通孔中填充导电材料形成所述第一插塞和所述第二插塞。其中，第一深度和第二深度的大小可以根据实际工艺进行合理选择。
在一个示例中，还可以在接合在一起的两个晶圆内分别形成插塞，例如形成插塞的步骤包括：在其中一片晶圆(例如第一晶圆)上形成第一图形化的掩膜层，定义第一插塞的位置；以所述第一图形化的掩膜层为掩膜，刻蚀所述晶圆(例如第一晶圆)，形成第一通孔；去除所述第一图形化的掩膜层；在所述第一通孔中填充导电材料形成所述第一插塞，与对应的芯片电连接，其中该对应的芯片可以是第一晶圆上的第一芯片也可以是第二晶圆上的第二芯片；在另一片晶圆(例如第二晶圆)上形成第二图形化的掩膜层，定义第二插塞的位置；以所述第二图形化的掩膜层为掩膜，刻蚀所述晶圆(例如第二晶圆)，形成第二通孔；去除所述第二图形化的掩膜层；在所述第二通孔中填充导电材料形成所述第二插塞，与对应的芯片电连接。
示例性地，所述插塞形成在对应芯片的上方，例如，如图1D所示，第一插塞1021形成在对应的第一芯片101的上方，所述第二插塞1022形成在对应的第二芯片201的上方。
在一个示例中，还可以是，所述插塞形成在对应芯片的一侧，在 形成所述插塞之前，还包括，形成互连线(未示出)，与对应的芯片电连接，以及与对应芯片一侧的插塞电连接，也即相对应的芯片和插塞之间通过互连线相连接，其中形成互连线的方法可以是本领域技术人员公知的任何适合的方法，在此不做赘述，其中，所述互连线可以包括若干层金属层以及连接相邻金属层的接触孔，其中，所述互连线的材料可以是任意适合的导电材料，例如金属材料，包括但不限于铜或者铝等。
接着，执行步骤四，形成再分布互连结构，电连接所述插塞。
示例性地，如图1E所示，在所述第一晶圆100或者所述第二晶圆200形成有所述第一插塞1021和所述第二插塞1022的表面形成彼此间隔的多个第一再分布互连结构103，其中，所述第一再分布互连结构103电连接至少一个所述第一插塞1021和/或至少一个所述第二插塞1022。
再布线互连结构(例如第一再分布互连结构103和后续的第二再分布互连结构等)可以是本领域技术人员熟知的任何适合的金属材料，所述金属材料可以包括但不限于Ag、Au、Cu、Pd、Cr、Mo、Ti、Ta、Sn、W和Al中的至少一种金属。
示例性地，所述第一再分布互连结构103可以包括再布线层和焊盘，或者，包括焊盘。
可以使用任何适合的方法形成所述第一再分布互连结构103，例如，形成金属材料层以覆盖第二晶圆200的背面，其中，可以使用物理气相沉积方法(PVD)、化学气相沉积方法(CVD)、溅射、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺形成所述金属材料层，再通过刻蚀的方法去除部分所述金属材料层，以形成间隔设置的多个第一再分布互连结构103。
尽管图1E中仅示出了第一再分布互连结构103电连接对应的插塞的情况，但是可以想到的是，为了实现更多的电连接方式，还可以使第一再分布互连结构103电连接至少一个第一插塞1021和至少一个第二插塞1022。
值得注意的是，还可以在第一再分布互连结构103上方形成金属互连线，以实现更多芯片的连接，其中，通常金属互连线包括由更多 位于不同层的金属层构成，以及不同层的金属层通过设置在相邻层之间的插塞或金属插塞电连接。
在一个示例中，在形成所述第一再分布互连结构103之后，还包括以下步骤：形成层间介电层104，以覆盖所述第一再分布互连结构103以及所述第一晶圆100或者所述第二晶圆200的背面，例如形成层间介电层104，以覆盖所述第一再分布互连结构103以及所述第二晶圆200的背面。
层间介电层104可以使用例如SiO 2、碳氟化合物(CF)、掺碳氧化硅(SiOC)、或碳氮化硅(SiCN)等。或者，也可以使用在碳氟化合物(CF)上形成了SiCN薄膜的膜等。碳氟化合物以氟(F)和碳(C)为主要成分。碳氟化合物也可以使用具有非晶体(非结晶性)构造的物质。层间介电层104还可以使用例如掺碳氧化硅(SiOC)等多孔质构造。
可以使用化学气相沉积法、物理气相沉积法、原子层沉积法等方法形成所述层间介电层104。
其中，所述层间介电层104的顶面可以和所述第一再分布互连结构103的顶面齐平，或者，所述层间介电层104的顶面高于所述第一再分布互连结构103的顶面。
还可选择性地对层间介电层104的表面进行平坦化，以获得平坦的表面，所述平坦化的方法可以是化学机械研磨或者其他适合的方法。
至此，完成了对本发明的两片晶圆相接合的方法的关键步骤的介绍，对于完整的方法还可能包括其他的步骤，例如封装完成后，还可以沿切割道对晶圆进行切割工艺，以将集成在晶圆上的多个芯片分割为各自独立的单元，例如每个单元均包括至少一个第一芯片和至少一个第二芯片，该单元形成一个可提供多种功能的系统或子系统，该功能取决于实际集成的芯片的功能。
实施例二
上述步骤示出了将第一晶圆和第二晶圆两个形成有芯片的晶圆相接合集成在一起所需的主要工艺步骤，而利用本发明的方法还可以将更多的晶圆集成在一起，以实现更多个芯片的封装。本发明的封装 方法还可以用于将至少三片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起。
下面，参考图1A至图1E、图2A、图3A至图3C以及图4A至图4B对将至少三片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起的封装方法进行描述。
首先，如图3A所示，提供第三晶圆300。
在一个示例中，还可以提供至少一个形成有第三芯片301的第三晶圆300，在每个所述第三晶圆的正面以内设置有彼此间隔的多个第三芯片301。
第三晶圆300为完成器件制作，分别形成有多个第三芯片301的器件晶圆。该器件晶圆可以采用集成电路制作技术根据相应的布图设计进行制作，例如在半导体晶圆上通过沉积、刻蚀等工作形成诸如NMOS和/或PMOS等的器件，以及介质层和金属层构成的互连层和位于互连层之上的焊盘等结构，从而在半导体晶圆中制作呈阵列排布的第三芯片301。
具体地，所述第三晶圆300包括半导体衬底，所述半导体衬底的材料可以使用前述实施一中所示例的半导体材料中的任意一种或多种。
所述第三芯片301通过本领域技术人员熟知的适合的工艺形成在相应晶圆的正面，形成类似如图3A所示的每个所述第三芯片301嵌入在相应晶圆的正面内的结构。
值得一提的是，第三芯片301还可以是形成在晶圆正面以内的多个不同结构的芯片，功能不同的芯片。
示例性地，第三芯片301也可以是结构和功能相同的芯片。
接着，继续将新的所述晶圆与已经接合在一起的晶圆的其中一个接合，所述需要接合在一起的两个晶圆中，其中一个为新的晶圆，另一个为已经接合在一起的两个晶圆中的其中一个。
其中，新的晶圆是指需要继续接合的晶圆，示例性地，如图3B所示，所述新的晶圆是指一个第三晶圆300，将第三晶圆300和已经接合在一起的第一晶圆100和第二晶圆200的其中一个接合(例如图 1E所示的结构)。
在此仅以将一个所述第三晶圆300与如图1E所示的已经接合在一起的两个晶圆中的第二晶圆200接合的方法进行说明，该方法同样适用于将第三晶圆300和如图1E所示的已经接合在一起的两个晶圆中的第一晶圆100相接合的情况，主要包括以下步骤A1至A3：
首先，执行步骤A1，将所述第三晶圆和形成有所述第一再分布互连结构103的表面相接合，其中，接合方法可以使用前述实施一中所提到的将第一晶圆和第二晶圆相接合的方法中的任意一种。
在一个示例中，为了实现熔融键合工艺，在接合之前，还包括在在所述第三晶圆300的正面形成键合层105的步骤。
其中，所述键合层105的材料包括氧化硅层，包括利用热化学气相沉积(thermal CVD)制造工艺或高密度等离子体(HDP)或者由正硅酸乙酯(TEOS)制造工艺形成的氧化硅的材料层，也可以是由热氧化工艺形成的氧化硅层，还可以是采用低工艺温度氧化方法(Low process temperature oxide，LTO)制备的所述氧化硅层，工艺温度小于200℃。
在一个示例中，进行键合工艺，将所述键合层105和所述层间介电层104键合在一起，以实现第三晶圆300和第二晶圆的接合。
该键合工艺为熔融键合，特别是为低温熔融键合工艺，并且在键合过程中还可以施加压力，例如施加的键合压力为1～10N，其中，键合时间可以为10～60s。熔融键合过程中，形成Si-O键实现两片晶圆的互连。
在一个示例中，在接合之后，还可以自所述第三晶圆300的背面对所述第三晶圆300进行减薄至目标厚度。该目标厚度根据实际工艺需要而定，在此不做具体限定。
接着，执行步骤A2，在所述第三晶圆300中形成彼此间隔的多个第三插塞106，其中，部分所述第三插塞106与所述第一再分布互连结构103电连接，部分所述第三插塞106电连接所述第三芯片301。
所述第三插塞106自所述第三晶圆300的背面向正面延伸，每个所述第一再分布互连结构103电连接至少一个所述第三插塞106，每个所述第三芯片301电连接至少一个所述第三插塞106，其中，与所 述第一再分布互连结构103电连接的第三插塞106贯穿所述第三晶圆以及所述键合层105。
值得一提的是，可以使用任何适合的方法形成所述第三插塞106，例如可以参考前述实施例一中第一插塞和第二插塞的形成方法形成该第三插塞。
随后，执行步骤A3，在所述第三晶圆300的背面形成第二再分布互连结构107。
具体地，该第二再分布互连结构可以包括再布线层和焊盘，或者包括焊盘，用于将第一芯片、第二芯片和第三芯片引出与外部电路实现连接，所述第二再分布互连结构107电连接所述第三插塞106。
可以使用任何适合的方法形成所述第二再分布互连结构107，第二再分布互连结构107的形成方法可以参考前述实施例一中第一再分布互连结构107的方法，在此不做赘述。
在一个示例中，还包括在所述第三晶圆的背面依次再接合多个晶圆的步骤，该多个晶圆中均形成有彼此间隔的多个芯片，可以包括步骤B1，形成层间介电层，以覆盖所述第二再分布互连结构，步骤B2，将正面设置有彼此间隔的多个芯片的另一新的晶圆与形成有层间介电层的表面相接合，示例性地，还可在该另一新的晶圆的正面形成键合层，利用键合工艺将该另一新的晶圆和形成有所述层间介电层的表面相接合，以实现更多晶圆的封装，步骤B3，自该另一新的晶圆的背面对该另一新的晶圆进行减薄至目标厚度，步骤B4，在该另一新的晶圆中形成彼此间隔的多个插塞，部分插塞电连接所述第二再分布互连结构，部分插塞电连接形成在该另一新的晶圆中的芯片，步骤B5，在该另一新的晶圆的背面形成再分布互连结构，该金属层至少电连接一个所述插塞。可以依次循环执行步骤B1至步骤B5，从而实现多于3个晶圆的接合以及封装。其中新的晶圆均是指需要继续与其它晶圆接合的晶圆。
在一个示例中，如图3C所示，形成钝化层108，以覆盖所述第二再分布互连结构107以及所述第三晶圆300的背面。
所述钝化层108的材料可以使用任何适合的绝缘材料，例如所述钝化层108使用诸如氧化硅层、氮化硅层、或氮氧化硅层的无机绝缘 层，可通过化学气相沉积、物理气相沉积或原子层沉积等沉积方法沉积形成所述钝化层108；还可以使用诸如包含聚乙烯苯酚、聚酰亚胺、或硅氧烷等的层的绝缘层等。聚乙烯苯酚、聚酰亚胺、或硅氧烷可有效地通过微滴排放法、印刷术或旋涂法形成。硅氧烷根据其结构可被分类成二氧化硅玻璃、烷基硅氧烷聚合物、烷基倍半硅氧烷(alkylsilsesquioxane)聚合物、倍半硅氧烷氢化物(silsesquioxane hydride)聚合物、烷基倍半硅氧烷氢化物(alkylsilsesquioxane hydride)聚合物等。此外，绝缘材料可用包括具有Si-N键的聚合物(聚硅氨烷)的材料形成。此外，可层叠这些膜以形成钝化层。
示例性地，所述钝化层108的顶面高于所述第二再分布互连结构107的顶面。所述钝化层的厚度可以是任意适合的厚度，在此不做具体限定。
示例性地，在沉积钝化层108后还可以选择性的对钝化层108的表面进行化学机械研磨，以获得平坦的表面。
在一个示例中，在将多于三个的晶圆封装在一起时，可以形成钝化层108，以覆盖位于顶层的再分布互连结构(该再分布互连结构包括焊盘)。
随后，继续如图3C所示，在每个所述第二再分布互连结构107上方的所述钝化层108中形成开口109，所述开口109露出部分所述第二再分布互连结构107，也即露出第二再分布互连结构107中包括的焊盘。
为了实现焊盘与外部电路的连接，需要露出焊盘表面的开口109，可以使用任何适合的方法形成所述开口109，在一个示例中，首先在钝化层108的表面形成图案化的掩膜层，例如光刻胶层，该图案化的掩膜层定义有开口的图案，然后再以该图案化的掩膜层为掩膜，刻蚀露出的钝化层108，直到露出第二再分布互连结构107的表面，以形成所述开口109，随后，将图案化的掩膜层去除，例如通过灰化或者湿法刻蚀的方法去除光刻胶材质的掩膜层。
在一个示例中，如图4A所示，还可以在对第三晶圆300的背面进行减薄之后，将第三晶圆300的背面和第二晶圆200接合，或者，将还可以在对第三晶圆300的背面进行减薄之后，将第三晶圆300的 背面和第一晶圆100接合，可以使用与前述方法相同的接合方法以及形成插塞的方法也可以参照前述插塞的形成方法，在此不做赘述。
在一个示例中，如图4B所示，还可以将如图2A所示的结构和第三晶圆300相接合，其接合方法可以使用与前述方法相同的接合方法以及形成插塞的方法也可以参照前述插塞的形成方法，在此不做赘述。
至此，完成了对本发明的晶圆级系统封装方法的关键步骤的介绍，对于完整的方法还可能包括其他的步骤，例如封装完成后，还可以沿切割道对晶圆进行切割工艺，以将集成在晶圆上的多个芯片分割为各自独立的单元，例如每个单元均包括至少一个第一芯片和至少一个第二芯片和至少一个第三芯片，该单元形成一个可提供多种功能的系统或子系统，该功能取决于实际集成的芯片的功能。
综上所述，本发明的晶圆级系统封装方法，使用晶圆级封装和系统封装方法相结合，同时实现了多种芯片的集成和在晶圆上完成封装制造优势，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求，提高了封装的效率和良率。
实施例三
本发明再一方面还提供一种晶圆级系统封装结构，所述晶圆级系统封装结构基于前述封装方法制备获得。
下面参考图1E、图3C、图4A和图4B对本发明的封装结构进行解释和说明。
作为示例，本发明的封装结构包括至少两片形成有芯片的晶圆，沿垂直晶圆表面的方向堆叠接合在一起，例如，如图3C、图4A和图4B所示，包括第一晶圆100、第二晶圆200以及第三晶圆300，在所述第一晶圆100的正面设置有彼此间隔的多个第一芯片101，在所述第二晶圆200的正面设置有彼此间隔的多个第二芯片201，在所述第三晶圆300的正面设置有彼此间隔的多个第三芯片301。
在一个示例中，相互接合在一起的两片所述晶圆，其中一个的正面与另一个的正面相对接合在一起，例如，如图1E和图3C所示、第一晶圆100的正面和第二晶圆200的正面相接合。
在一个示例中，相互接合在一起的两片所述晶圆，其中一个的正面与另一个的背面相对接合在一起，例如，第一晶圆的正面和第二晶圆的背面相对接合在一起，或者，如图2A所示，第一晶圆100的背面和第二晶圆200的背面相对接合在一起。
在一个示例中，其中一个的背面与另一个的背面相对接合在一起，或者，如图2B所示，第一晶圆100的背面与第二晶圆200的背面相对接合在一起。
在一个示例中，本发明的封装结构还包括插塞，相互接合在一起的两片所述晶圆中的芯片，通过所述插塞电连接，例如如图3C所示，第一晶圆100和第二晶圆200相接合，第一插塞1021电连接所述第一晶圆100中的第一芯片101，第二插塞1022电连接所述第二晶圆200中的第二芯片201，而若干个第三插塞106电连接所述第三晶圆300中的第三芯片301，若干个第三插塞还进一步电连接所述第二芯片201，若干个第三插塞106还进一步电连接所述第一芯片101。
在一个示例中，所述插塞形成在对应芯片的上方，例如，在所述第二晶圆200中形成有间隔设置的多个第一插塞1021和多个第二插塞1022，其中，所述第一插塞1021形成在对应的第一芯片101的上方，所述第二插塞1022形成在对应的第二芯片201的上方。
具体地，所述第一插塞1021用于实现第一芯片101和外部电路的电连接，所述第二插塞1022用于实现第二芯片201和外部电路的电连接，尽管图3C中仅示出了一个第一芯片101电连接一个所述第一插塞1021，一个第二芯片201电连接一个所述第二插塞1022的情况，但是对于其他的每个芯片电连接多个插塞的情况，也同样适用于本发明。
示例性地，如图1E所示，所述第一插塞1021自所述第二晶圆200的背面向所述正面延伸直到与其所对应的所述第一芯片101电连接，所述第二插塞1022自所述第二晶圆200的背面向所述正面延伸直到与其所对应的所述第二芯片201电连接。
在一个示例中，所述插塞形成在对应芯片的一侧，并且还形成有互连线，所述互连线与对应的芯片电连接，以及与对应芯片一侧的所述插塞电连接。其中，所述互连线可以包括若干层金属层以及连接相 邻金属层的接触孔，其中，所述互连线的材料可以是任意适合的导电材料，例如金属材料，包括但不限于铜或者铝等。
示例性地，还包括电连接所述插塞的再分布互连结构，位于所述插塞的顶部。例如，在第一插塞1021和所述第二插塞1022的顶部形成有第一再分布互连结构103，其中，所述第一再分布互连结构103电连接至少一个所述第一插塞1021和/或至少一个所述第二插塞1022。
尽管图3C中仅示出了第一再分布互连结构103电连接对应插塞的情况，但是可以想到的是，为了实现更多的电连接方式，还可以使第一再分布互连结构103电连接至少一个第一插塞1021和至少一个第二插塞1022。
示例性地，所述第一再分布互连结构103可以包括再布线层和焊盘，或者，包括焊盘。
在一个示例中，还包括覆盖所述第一再分布互连结构103以及所述第一晶圆100或者所述第二晶圆200的背面的层间介电层104，例如层间介电层104覆盖所述第一再分布互连结构103以及所述第二晶圆200的背面。
其中，所述层间介电层104的顶面可以和所述第一再分布互连结构103的顶面齐平，或者，所述层间介电层104的顶面高于所述第一再分布互连结构103的顶面。
在一个示例中，还包括第三晶圆300，所述第三晶圆和形成有所述第一再分布互连结构的表面相接合，例如，将所述第三晶圆300和第二晶圆200背面相接合。
在一个示例中，还包括形成在相接合的所述晶圆的界面处的键合层105。
在一个示例中，所述键合层105和所述层间介电层104键合在一起，以实现第三晶圆300和第二晶圆200的接合。
示例性地，在所述第三晶圆300中形成有彼此间隔的多个第三插塞106，其中，部分所述第三插塞106与所述第一再分布互连结构103电连接，部分所述第三插塞106电连接所述第三芯片301。
所述第三插塞106所述第三晶圆300的背面向正面延伸，每个所 述第一再分布互连结构103电连接至少一个所述第三插塞106，每个所述第三芯片301电连接至少一个所述第三插塞106。其中，与所述第一再分布互连结构103电连接的第三插塞106贯穿所述第三晶圆以及所述键合层105。
示例性地，在所述第三晶圆300的背面形成有第二再分布互连结构107。该第二再分布互连结构可以包括再布线层和焊盘，或者包括焊盘，用于将第一芯片、第二芯片和第三芯片引出与外部电路实现连接。
在一个示例中，覆盖形成有所述再分布互连结构的晶圆的表面的钝化层，例如，如图3C所示，还形成有覆盖所述第二再分布互连结构107以及所述第三晶圆300的所述背面的钝化层108。
在一个示例中，在将多于三个的晶圆封装在一起时，所述钝化层可以覆盖位于顶层的再分布互连结构(该再分布互连结构包括焊盘)。
示例性，在每个所述第二再分布互连结构107上方的所述钝化层108中形成有开口109，所述开口109露出部分所述第二再分布互连结构107。
本发明的晶圆级系统封装结构由于使用了前述的晶圆级系统封装方法制备获得，因而具有更好的性能。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (18)

  1. 一种晶圆级系统封装方法，用于将至少两片形成有芯片的晶圆沿上下堆叠的方向，堆叠接合在一起，其特征在于，所述方法包括：
    将需要接合在一起的两片所述晶圆相接合；
    在所述接合之后，形成插塞，与两片所述晶圆中的芯片电连接。
  2. 如权利要求1所述的封装方法，其特征在于，
    将两片所述晶圆的正面与正面相对接合在一起，或者，将其中一个的正面与另一个的背面相对接合在一起，进行所述接合步骤之后，形成所述插塞之前，还包括：
    对其中一个背面朝外的晶圆背面进行减薄工艺。
  3. 如权利要求1所述的封装方法，其特征在于，将所述两片晶圆的背面与背面相对接合在一起，进行所述接合步骤之前，还包括：
    对其中一个晶圆的背面进行减薄工艺。
  4. 如权利要求1所述的封装方法，其特征在于，所述形成插塞的步骤包括：
    在接合在一起的两片所述晶圆的其中至少一个晶圆内形成通孔；
    在所述通孔中填充导电材料形成所述插塞，与对应的所述芯片电连接。
  5. 如权利要求1所述的封装方法，其特征在于，所述插塞形成在对应芯片的上方；
    或者，所述插塞形成在对应芯片的一侧，在形成所述插塞之前，还包括，形成互连线，与对应的芯片电连接，以及与对应芯片一侧的插塞电连接。
  6. 如权利要求1所述的封装方法，其特征在于，在形成所述插塞之后，还包括：
    形成再分布互连结构，电连接所述插塞。
  7. 如权利要求6所述的封装方法，其特征在于，所述再分布互连结构包括：再布线层和焊盘，或者，包括焊盘。
  8. 如权利要求1所述的封装方法，其特征在于，所述方法用于将两片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起。
  9. 如权利要求1所述的封装方法，其特征在于，所述方法用于 将至少三片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起。
  10. 如权利要求9所述的封装方法，其特征在于，所述方法还包括：
    继续将新的所述晶圆与已经接合在一起的晶圆的其中一个接合，
    所述需要接合在一起的两个晶圆中，其中一个为新的晶圆，另一个为已经接合在一起的两个晶圆中的其中一个。
  11. 如权利要求1所述的封装方法，其特征在于，两片晶圆通过熔融键合工艺、硅硅直接键合工艺或者粘接工艺相键合。
  12. 如权利要求2或3所述的封装方法，其特征在于，所述减薄工艺为:机械研磨工艺、化学机械研磨或者刻蚀工艺中的至少一种。
  13. 一种晶圆级系统封装结构，其特征在于，包括：
    至少两片形成有芯片的晶圆，沿垂直晶圆表面的方向堆叠接合在一起；
    插塞，相互接合在一起的两片所述晶圆中的芯片，通过所述插塞电连接。
  14. 如权利要求13所述的晶圆级系统封装结构，其特征在于，相互接合在一起的两片所述晶圆，其中一个的正面与另一个的正面相对接合在一起；
    或者，其中一个的正面与另一个的背面相对接合在一起；
    或者，其中一个的背面与另一个的背面相对接合在一起。
  15. 如权利要求13所述的晶圆级系统封装结构，其特征在于，所述插塞形成在对应芯片的上方；
    或者，所述插塞形成在对应芯片的一侧，并且还形成有互连线，所述互连线与对应的芯片电连接，以及与对应芯片一侧的所述插塞电连接。
  16. 如权利要求13所述的晶圆级系统封装结构，其特征在于，还包括：
    电连接所述插塞的再分布互连结构，位于所述插塞的顶部。
  17. 如权利要求16所述的晶圆级系统封装结构，其特征在于，所述再分布互连结构包括：再布线层和焊盘，或者，包括焊盘。
  18. 如权利要求13所述的晶圆级系统封装结构，其特征在于， 还包括：形成在相接合的所述晶圆的界面处的键合层。
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