WO2012041034A1 - 3d集成电路结构及其形成方法 - Google Patents

3d集成电路结构及其形成方法 Download PDF

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Publication number
WO2012041034A1
WO2012041034A1 PCT/CN2011/071166 CN2011071166W WO2012041034A1 WO 2012041034 A1 WO2012041034 A1 WO 2012041034A1 CN 2011071166 W CN2011071166 W CN 2011071166W WO 2012041034 A1 WO2012041034 A1 WO 2012041034A1
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layer
wafer
integrated circuit
stress relief
substrate
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PCT/CN2011/071166
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English (en)
French (fr)
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朱慧珑
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中国科学院微电子研究所
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Priority to US13/380,022 priority Critical patent/US8796852B2/en
Publication of WO2012041034A1 publication Critical patent/WO2012041034A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to the field of semiconductor manufacturing technology, and in particular, to a 3D integrated circuit structure and a method of forming the same. Background technique
  • the current 3D IC (Integrated Circuit) integration is described as a system level architecture formed by a combination of multiple wafers, each of which contains a stack of multiple planar device layers and is via silicon. Through holes (TSV, Through-Silicon- Via) are connected to each other in the Z direction. With the application of 3D, the TSV size will continue to decrease, the thickness of the silicon layer will continue to be thinner, and 3D integrated circuits will be more and more widely used.
  • TSV Through holes
  • An object of the present invention is to solve at least one of the above problems in the prior art.
  • embodiments of the present invention provide a 3D integrated circuit structure and a method of fabricating the same to improve the performance of a 3D integrated circuit.
  • an embodiment of the present invention provides a 3D integrated circuit structure, the integrated circuit structure including a first wafer, wherein the first wafer includes: a substrate; formed at the bottom of the village, a through hole formed in the dielectric layer, a conductive material layer formed in the through hole; a stress releasing layer surrounding the through hole; and a first interconnect structure connecting the device and the through hole.
  • an embodiment of the present invention provides a method of forming a 3D integrated circuit, the method comprising the steps of: A.
  • the first wafer comprises: a substrate, a semiconductor device And a dielectric layer, wherein the device is formed on the substrate, the dielectric layer is formed on the substrate and the device; B, forming a through hole and stress release through the substrate and the dielectric layer a layer, wherein the stress relief layer surrounds the via hole; C. filling the via hole to form a conductive material layer; D. forming a first interconnect structure connecting the device and the via hole.
  • a stress relief layer is provided in the via hole to release a portion of the via hole between the conductive material and the surrounding semiconductor (such as silicon) due to CTE (Coefficient of Thermal Expansion, temperature) The expansion coefficient) does not match the resulting stress, thereby improving the performance of the MOSFET device and its correspondingly constructed 3D integrated circuit.
  • FIG. 1 and FIG. 1b are schematic cross-sectional views showing different stages of a process for manufacturing a 3D integrated circuit wafer according to a first embodiment of the present invention
  • FIGS. 2-6 are partial structural views of a 3D integrated circuit formed using the wafer of the embodiment of Figs. la and lb;
  • FIG. 7a-7e are schematic cross-sectional views showing different stages of a process for fabricating a 3D integrated circuit wafer according to a second embodiment of the present invention.
  • Figures 8 and 9 are partial schematic views of a 3D integrated circuit formed using the wafer of the embodiment of Figures 7a-7e. detailed description
  • the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • Embodiments of the present invention describe a method of first bonding a wafer and then forming a via (e.g., a TSV via) to form a 3D integrated circuit.
  • a via e.g., a TSV via
  • FIGS la to lb there is shown a cross-sectional structure at various stages in the fabrication of a 3D integrated circuit wafer of an embodiment of the present invention.
  • the wafer 1 includes a substrate 202.
  • the semiconductor substrate 202 is exemplified by bulk silicon, so that the via hole formed below becomes a through-silicon via, but in practical applications, the village bottom can be Any suitable semiconductor substrate material may be included, but is not limited to silicon, germanium, silicon germanium, SOI (silicon on insulator), silicon carbide, gallium arsenide or any III/V compound semiconductor.
  • the substrate 202 can include various doping configurations in accordance with design requirements well known in the art (e.g., p-type substrate or n-type substrate). Additionally, the substrate 202 can optionally include an epitaxial layer that can be altered by stress to enhance performance.
  • the wafer 1 further includes: a semiconductor device 214 formed on the substrate 202, and a dielectric layer 204 formed on the substrate 202 and the semiconductor device 214, which may be an oxide layer, such as may be deposited by art.
  • the process is formed on the village bottom 202 with a thickness ranging from 100 to 300 nm.
  • a back via interconnect (BEOL) structure 216, a via 224 over the back interconnect structure 216, and its metal interconnect 228 are formed over the wafer structure formed in FIG.
  • Back channel interconnection Structure 216 may be a copper interconnect formed using a metal wiring process.
  • Semiconductor device 214 and its subsequent interconnect structure 216 are formed in dielectric layer 204, where vias 224, vias 224, and metal interconnects 228, which are formed over back via interconnect structure 216, may be utilized in the art. Any method suitable for use is not limited in the present invention.
  • the wafer 2 is provided with a via 252 which is connected to the back channel interconnection 253 of the semiconductor device 255 formed on the wafer 2.
  • the semiconductor device 255, the back via interconnect 253, and the via 252 of the wafer 2 can be constructed identically to the wafer 1, that is, the semiconductor device 255 is disposed over the dielectric layer 256 above the SOI layer, and the via 252 is disposed over the dielectric layer 256. 258.
  • the wafer 1 is turned over and bonded to the wafer 2 through the metal interconnection 228 to form a device structure as shown in FIG.
  • the forming step of the TSV hole includes: first forming a photoresist pattern identical to the via hole and the stress relief channel pattern to be formed, and then etching the substrate 202 of the wafer 1 and the dielectric layer where the semiconductor device 214 is located according to the photoresist pattern. 204, forming a through hole 217 whose outer wall is the stress channel isolation layer 219, and a stress relief layer channel 215 surrounding the through hole 217.
  • the stress relief layer channel 215 acts as a stress relief layer, as shown in FIG.
  • the stress relief layer may be unfilled (ie, only contains air), or may be filled with a soft material, for example, a combination of one or more soft materials including a polymer, a rubber, and a plastic, thereby using a conductive material in the subsequent use.
  • a soft material for example, a combination of one or more soft materials including a polymer, a rubber, and a plastic, thereby using a conductive material in the subsequent use.
  • the filling of the through holes can effectively release the mechanical stress generated by the conductive material and reduce the influence of stress on other parts of the entire wafer.
  • a dielectric material such as a nitride layer is preferably deposited on the above device, for example, chemical vapor deposition or other methods, as shown in Fig. 4.
  • the nitride layer on the above device is etched, for example, dry or wet etched, and a thin nitride layer 211 is left on the upper portion of the stress relief channel 215 to form a device structure as shown in FIG.
  • the stress relief layer includes a stress relief channel 215 and a nitride layer 211.
  • a dielectric material such as the nitride layer 211
  • an insulating layer 218 is formed on the sidewall of the stress channel isolation layer 219.
  • an oxide or a spacer material such as Si 3 N 4 may be deposited in the via hole 217, thereby enhancing the insulation of the via hole 217.
  • a barrier layer 220 may be deposited on the sidewall of the insulating layer 218. The barrier layer 220 may prevent the metal conductive material filled in the via hole 217 from migrating outward in the subsequent process, and enter the semiconductor device to destroy the performance of the MOSFET transistor 214.
  • the material of the barrier layer 220 includes a combination of one or more of Ru, Ta, TaN, Ti, TiN, TaSiN, TiSiN, TiW, and WN.
  • a conductive material is filled in the via hole 217 to form a conductive plug 222, such as a metal of copper (Cu), aluminum (A1) or tungsten (W), or a conductive polymer, a metal silicide or the like, thereby forming The TSV hole for the 3D integrated circuit chip interconnect shown in FIG.
  • the stress relief channel 215 is not covered with the dielectric material, other suitable methods such as patterned photoresist protection, etc., are required before filling the via 217 with the conductive material.
  • the stress relief channel 215 is shielded and filled with a conductive material.
  • the conductive plug 222 may be a metal material, and then the entire wafer surface is planarized, such as chemical mechanical polishing (CMP), to form a TSV hole.
  • CMP chemical mechanical polishing
  • the formation of the TSV holes may be any suitable process in the prior art, which is not limited in the present invention.
  • Embodiments of the present invention describe a method of forming vias (e.g., TSV vias) and then bonding the wafers to form a 3D integrated circuit.
  • vias e.g., TSV vias
  • FIGS 7a through 7e there are shown cross-sectional structures at various stages in the fabrication of a 3D integrated circuit wafer in accordance with an embodiment of the present invention.
  • the wafer includes a substrate 2.
  • the village bottom 2 is exemplified by bulk silicon, but the material thereof can refer to the village bottom 202 in the first embodiment.
  • the wafer further includes: a semiconductor device 14 formed on the substrate 2, and a dielectric layer 4 formed on the substrate 2 and the semiconductor device 14.
  • the dielectric layer 4 may be an oxide layer, for example, formed on the substrate 2 by a deposition process well known in the art, and has a thickness ranging from 100 to 300 nm.
  • a metal oxide semiconductor is built over the wafer structure formed in Figure 7a.
  • the back via interconnect structure 16 may be a copper interconnect formed using a metal wiring process.
  • the semiconductor device 14 and its subsequent interconnect structure 16 are formed in the dielectric layer 4, where the semiconductor device 14 and its subsequent interconnect structure 16 can be constructed using any suitable method known in the art.
  • Fig. 7c shows a cross-sectional structural view of further forming a through silicon via (TSV) in the semiconductor structure shown in Fig. 7b. Prior to forming the TSV holes, the wafer was flipped over so that the bottom of the wafer was up, and Figures 7c-7e were both bottom-up wafer placement.
  • TSV through silicon via
  • the step of forming the TSV hole includes: first removing the dielectric layer 4 where the substrate 2 and the semiconductor device 14 are located, forming a via hole 17 having the outer wall as the stress channel isolation layer 19, and a stress releasing layer surrounding the via hole 17, wherein the stress releasing layer A stress relief channel 15 is included.
  • the stress relieving layer ie, the stress relief channel 15 in this embodiment
  • the specific formation method of the TSV hole of the present embodiment is the same as that of the first embodiment of the present invention, and is merely summarized as a cylinder, and similarly, the dielectric material may be partially covered on the stress relief passage 15 to protect it.
  • the via hole 17 and the stress channel isolation layer 19 may be formed by photolithography bonding etching. Then, a dielectric material such as a nitride layer is preferably deposited on the above device, for example, chemical vapor deposition or the like may be employed. Next, the nitride layer on the above device is etched, and a thin nitride layer 11 is left on the upper portion of the stress relief channel 15.
  • the stress relief layer includes a stress relief channel 15 and a nitride layer 11.
  • An insulating layer 18 may first be formed on the sidewalls of the stress channel isolation layer 19, for example, an insulating material such as an oxide or a nitride such as Si 3 N 4 is deposited in the via hole 17. Then, optionally, a barrier layer 20 may be deposited on the sidewall of the insulating layer 18. The barrier layer 20 may prevent the conductive material filled in the via hole 17 from migrating outward in the subsequent process, and enter the semiconductor device to damage the semiconductor device. 14 performance.
  • the material of the barrier layer 20 includes a combination of one or more of Ru, Ta, TaN, Ti, TiN, TaSiN, TiSiN, TiW, and WN.
  • a conductive material is filled in the via hole 17 to form a conductive plug 22, wherein the conductive material includes a metal such as copper (Cu), aluminum (A1) or tungsten (W), and may also be a conductive polymer, a metal silicide, or the like. Etc., thereby forming TSV holes for 3D integrated circuit die interconnects.
  • the conductive plug 22 is a metal material, and then the entire wafer structure is planarized, such as chemical mechanical polishing (CMP), to form TSV holes.
  • CMP chemical mechanical polishing
  • the formation of the TSV holes may be any suitable process in the prior art, which is not limited in the present invention.
  • Figure 7d shows a schematic structural view of an interconnect structure connecting a semiconductor device 14 and a TSV via, wherein the interconnect structure includes vias 24 formed over the corresponding back-via interconnect structure 16 of the MOSFET transistor 14, and connection vias 24 and TSVs. Metal interconnects 28 of the holes.
  • the interconnect structure can connect the TSV vias to the semiconductor device 14.
  • a 3D integrated circuit structure can be realized.
  • the TSV holes at the bottom of the corresponding wafer need to be ground or thinned to expose the metal material in the TSV hole. To make the corresponding conductive connection.
  • the bottom of the wafer is ground or thinned to expose the conductive plugs 22 in the TSV holes at the bottom of the wafer.
  • Figures 8 and 9 show a partial structure of a 3D integrated circuit of a second embodiment formed using the wafer 3 of the embodiment of Figures 7a-7e.
  • the 3D integrated circuit structure includes a wafer 3, wherein the wafer 3 comprises: a substrate 2; a semiconductor device 14 formed on the substrate, and a dielectric layer 4 formed on the substrate 2 and the device 14; A through hole 17 is formed in the dielectric layer 4, a conductive material layer is formed in the through hole 17, a stress releasing layer surrounding the through hole 17, and a first interconnection structure connecting the device 14 and the through hole 17.
  • the stress relief layer may be the stress relief channel 15 .
  • the stress relief layer may include a combination of any one or more of air, polymer, rubber, and plastic covering at least a portion of the stress relief passage 15.
  • the stress relief layer may include a dielectric material 11 covering at least a portion of the stress relief channel 15 .
  • the conductive material layer comprises an inner conductive plug 22 and an outer barrier layer 20.
  • the material of the barrier layer 20 includes a combination of any one or more of Ru, Ta, TaN, Ti, TiN, TaSiN, TiSiN, TiW, and WN.
  • the 3D integrated circuit structure further includes a stress channel isolation layer 19 formed between the via hole 17 and the stress relief layer.
  • the sidewall of the via 17 has an insulating layer 18 which isolates the via 17 from the layer of conductive material which enhances the isolation between the layer of conductive material and other structures on the wafer.
  • FIG. 8 a schematic diagram of the connection of the wafer 3 forming the 3D integrated circuit with the external power source 300 is shown, in which the exposed conductive plug 22 of the wafer 3 is connected to the external power source 300, thereby being integrated for 3D. Circuit power supply.
  • a connection diagram of the wafer 3 and another wafer 4 of the 3D integrated circuit is shown.
  • the wafer 4 is provided with via holes 42, which are connected to the rear via interconnection 43 of the semiconductor device 45 built on the wafer 4.
  • the semiconductor device 45, the subsequent via 43 and the via 42 of the wafer 4 are constructed identically to the wafer 3, i.e., the semiconductor device 45 is disposed over the dielectric layer 46 above the silicon layer 44, and the via 42 is disposed over the dielectric layer 46. 48.
  • the wafer 3 is connected to the via 42 through its interconnect structure (ie, the via 24 and the metal interconnect 28), thereby connecting the TSV via of the wafer 3 to the wafer 4, that is, connecting the wafer 3 in a top-to-bottom form.
  • the wafer 4 a multi-wafer stack structure of the 3D integrated circuit is realized.
  • a stress channel release layer is provided to release a stress generated by a conductive material in a portion of the via hole, thereby reducing a CTE mismatch with a surrounding semiconductor such as silicon. The stress, thereby improving the performance of the semiconductor device and the correspondingly constructed 3D integrated circuit.

Description

3D集成电路结构及其形成方法
本申请要求于 2010 年 9 月 30 日提交中国专利局、 申请号为 201010502039.5、发明名称为" 3D集成电路结构及其形成方法 "的中国专利申请 的优先权， 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种 3D集成电路结构及其 形成方法。 背景技术
目前的 3D IC ( Integrated Circuit, 集成电路） 集成被描述为一种系统 级架构， 由多个晶片 （wafer ) 结合形成， 其中每个晶片的内部含有多个平 面器件层的叠层， 并经由硅通孔（ TSV, Through -Silicon- Via )在 Z方向相 互连接。 伴随 3D的应用， TSV尺寸将不断变小， 硅层厚度也将不断地变 薄， 3D集成电路也将得到越来越广泛的应用。
在形成 3D集成电路结构的部分工艺过程中， 例如在形成 TSV孔的工 艺中， 需要在形成的通孔中填充导电材料， 例如铜、 铝、 钨等， 由于需要 将导电材料填充到 TSV通孔中， 这会引起严重的热-机械应力， 从而可能造成 TSV通孔及其周围的半导体结构产生裂缝， 以及由于电流的变化造成器件失 效等问题。 发明内容
本发明的目的旨在至少解决现有技术中的上述问题之一， 为此， 本发 明的实施例提出一种 3D集成电路结构及其制造方法， 以提高 3D集成电路 的性能。
根据本发明的一个方面， 本发明实施例提出了一种 3D集成电路结构， 所述集成电路结构包括第一晶片， 其中第一晶片包括： 村底； 形成在所述 所述村底、 所述介质层形成的通孔， 所述通孔内形成有导电材料层； 包围 所述通孔的应力释放层； 以及连接所述器件与所述通孔的第一互连结构。 根据本发明的另一方面，本发明的实施例提出一种形成 3D集成电路的 方法， 所述方法包括以下步骤： A、 提供第一晶片， 其中所述第一晶片包 括： 村底、 半导体器件以及介质层， 其中， 所述器件形成在所述村底上， 所述介质层形成在所述村底及器件上； B、 形成贯穿所述村底以及所述介 质层的通孔和应力释放层， 其中所述应力释放层将所述通孔包围； C、 填 充所述通孔以形成导电材料层； D、 形成连接所述器件与所述通孔的第一 互连结构。
在本发明中， 对于构建在介质层上的半导体器件， 通过在通孔中设置 应力释放层可以释放一部分通孔中导电材料与周围半导体（如硅）之间由于 CTE ( Coefficient of Thermal Expansion , 温度膨胀系数） 不匹配产生的应力， 从而提高 M0SFET器件及其相应构成的 3D集成电路的性能。
本发明附加的方面和优点将在下面的描述中部分给出， 部分将从下面 的描述中变得明显， 或通过本发明的实践了解到。 附图说明
本发明的上述和 /或附加的方面和优点从下面结合附图对实施例的描 述中将变得明显和容易理解， 其中：
图 la和图 lb为本发明的第一实施例在制造 3D集成电路的晶片过程中 不同阶段的截面结构示意图；
图 2-6为利用图 la和图 lb的实施例的晶片形成的 3D集成电路的部分 结构示意图；
图 7a-7e为本发明的第二实施例在制造 3D集成电路的晶片过程中不同 阶段的截面结构示意图；
图 8和图 9为利用图 7a-7e的实施例的晶片形成的 3D集成电路的部分 结构示意图。 具体实施方式
下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其 中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功 能的元件。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本发 明， 而不能解释为对本发明的限制。 构。 为了筒化本发明的公开， 下文中对特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以 在不同例子中重复参考数字和 /或字母。 这种重复是为了筒化和清楚的目 的， 其本身不指示所讨论各种实施例和 /或设置之间的关系。 此外， 本发明 提供了的各种特定的工艺和材料的例子， 但是本领域普通技术人员可以意 识到其他工艺的可应用于性和 /或其他材料的使用。 另外， 以下描述的第一 特征在第二特征之"上"的结构可以包括第一和第二特征形成为直接接触的 实施例， 也可以包括另外的特征形成在第一和第二特征之间的实施例， 这 样第一和第二特征可能不是直接接触。
第一实施例
本发明实施例描述了先键合晶片， 再形成通孔（如 TSV孔）以形成 3D 集成电路的方法。 参考图 la到图 lb, 该图显示了在制造本发明实施例的 3D集成电路晶片过程中不同阶段的截面结构。
如图 la所示， 该晶片 1包括村底 202, 本发明实施例中， 该半导体村 底 202以体硅为例， 故以下形成的通孔成为硅通孔， 但实际应用中， 村底 可以包括任何适合的半导体村底材料， 具体可以是但不限于硅、 锗、 锗化 硅、 SOI (绝缘体上硅）、碳化硅、 砷化镓或者任何 III/V族化合物半导体等。 根据现有技术公知的设计要求 （例如 p型村底或者 n型村底） ， 村底 202 可以包括各种掺杂配置。 此外， 村底 202 可以可选地包括外延层， 可以被 应力改变以增强性能。 该晶片 1还包括： 形成在村底 202上的半导体器件 214, 以及形成在村底 202以及半导体器件 214上的介质层 204, 该介质层 204 可以是氧化层， 例如可以通过本领域公知的沉积工艺形成在村底 202 上， 厚度范围在 100-300nm之间。 通过上述步骤， 从而得到图 la所示的晶 片结构。
如图 lb所示， 在图 la形成的晶片结构上方构建后道互连（BEOL )结 构 216、 后道互连结构 216上方的过孔 224及其金属互连线 228。 后道互连 结构 216可以是利用金属布线工艺形成的铜互连。 半导体器件 214及其后 道互连结构 216形成于介质层 204中， 这里构建后道互连结构 216、 后道 互连结构 216上方的过孔 224及其金属互连线 228可以利用本领域公知的 任何适于使用的方法， 本发明对此不作限定。
之后， 如图 2所示， 晶片 2上设置有过孔 252, 过孔 252与晶片 2上 构建的半导体器件 255的后道互连 253连接。 晶片 2的半导体器件 255、 后道互连 253以及过孔 252的构建可以与晶片 1相同， 即半导体器件 255 设置在 SOI层上方的介质层 256 , 过孔 252设置在介质层 256上方的介质 层 258中。 然后， 将晶片 1翻转后与晶片 2通过金属互连线 228键合在一 起， 形成如图 2所述的器件结构。
图 3至图 6显示了在图 2所示半导体结构中进一步形成 TSV孔的剖面 结构图。 TSV孔的形成步骤包括： 首先形成与需要形成的通孔和应力释放 通道图形相同的光刻胶图案，然后根据光刻胶图案并刻蚀晶片 1的村底 202 以及半导体器件 214所在的介质层 204, 形成外壁为应力通道隔离层 219 的通孔 217 , 以及包围通孔 217的应力释放层通道 215。 其中应力释放层通 道 215即可作为应力释放层， 如图 3所示。 对所述应力释放层可以不进行 填充（即仅包含空气） ， 也可以填充包括软材料， 例如包括聚合物、 橡胶、 塑料中的一种或多种软材料的组合， 从而在后续采用导电材料填充通孔时 能够有效释放导电材料产生的机械应力， 减少应力对整个晶片中其他部分 的影响。
接着， 优选在上述器件上沉积一层介质材料， 如氮化物层， 例如可以 采用化学气相沉积或其他方法， 具体结构如图 4所示。 接着， 对上述器件 上的氮化物层进行刻蚀， 例如干法或湿法刻蚀， 并在应力释放通道 215 的 上部保留一层薄氮化物层 211 , 形成如图 5 所示的器件结构。 其中， 应力 释放层包括应力释放通道 215 以及氮化物层 211。 需指出的是， 在应力释 放通道 215 上部覆盖介质材料（如氮化物层 211 ) , 可以防止后续在通孔 中填充导电材料时保护应力释放层不被污染， 但此步骤不是必须的。
然后在应力通道隔离层 219 的侧壁上形成绝缘层 218 , 例如可以将氧 化物或者 Si3N4等隔离材料沉积到通孔 217中，从而加强了通孔 217的绝缘 性能。 接着， 在绝缘层 218的侧壁上可沉积阻挡层 220, 阻挡层 220可以 防止后续工艺中填充到通孔 217 中的金属导电材料向外迁移， 而进入半导 体器件中从而破坏 MOSFET晶体管 214的性能。 在一个实施例中， 阻挡层 220 的材料包括 Ru、 Ta、 TaN、 Ti、 TiN、 TaSiN、 TiSiN、 TiW 以及 WN 中的一种或多种的组合。
最后， 在通孔 217中填充导电材料以形成导电塞 222, 例如铜 （Cu ) 、 铝 （A1 ) 或者钨 （W ) 的金属， 也可以是导电聚合物、 金属硅化物等等， 从而形成如图 6所示的用于 3D集成电路晶片互连的 TSV孔。
对于本发明的其他实施例， 需指出的是， 如果应力释放通道 215上部 没有覆盖介质材料， 则向通孔 217填充导电材料之前， 需采用如图案化的 光刻胶保护等等其他合适的方法遮住应力释放通道 215 , 再进行导电材料 填充。 在本发明实施例中， 导电塞 222可以为金属材料， 然后对整个晶片 表面进行平坦化处理， 如化学机械抛光（CMP ) , 从而形成 TSV孔。 关于 TSV孔的形成可以是现有任意合适的工艺方法， 本发明对此不作限定。
第二实施例
本发明实施例描述了先形成通孔（如 TSV通孔） ， 再键合晶片以形成 3D集成电路的方法。 参考图 7a到图 7e, 该图显示了在制造本发明实施例 的 3D集成电路晶片过程中不同阶段的截面结构。
参考图 7a所示，该晶片包括村底 2。参考图 7a所示，本发明实施例中， 村底 2 以体硅为例， 但其材料可以参考第一实施例中的村底 202。 该晶片 还包括： 形成在村底 2上的半导体器件 14, 以及形成在村底 2以及半导体 器件 14上的介质层 4。 其中， 介质层 4可以是氧化物层， 例如通过本领域 公知的沉积工艺形成在村底 2上， 厚度范围在 100-300nm之间。 通过上述 步骤， 从而得到图 7a所示的晶片结构。
如图 7b 所示， 在图 7a 形成的晶片结构上方构建金属氧化物半导体
( MOS ) 器件 14及其后道互连 （BEOL ) 结构 16, 后道互连结构 16可以 是利用金属布线工艺形成的铜互连。 半导体器件 14及其后道互连结构 16 形成于介质层 4中， 这里构建半导体器件 14及其后道互连结构 16可以利 用本领域公知的任何适于使用的方法。 图 7c显示了在图 7b所示半导体结构中进一步形成硅通孔 （TSV ) 的 剖面结构图。 在形成 TSV孔之前， 先将晶片翻转过来， 使晶片底部向上， 图 7c-7e均为底部向上的晶片放置。 TSV孔的形成步骤包括： 首先去除村底 2及半导体器件 14所在的介质层 4,形成外壁为应力通道隔离层 19的通孔 17, 以及包围通孔 17的应力释放层， 其中， 应力释放层包括应力释放通道 15。 对 所述应力释放层 （即本实施例中的应力释放通道 15 ) 可以不进行填充 （即 仅包含空气） ， 也可以填充包括聚合物、 橡胶、 塑料中的一种或多种软材 料的组合。 本实施例 TSV孔的具体形成方法与本发明第一实施例的方法相 同， 此处仅作筒要概述， 并且同样地， 可以优选地在应力释放通道 15上部 分覆盖介质材料以对其进行保护。 如图 7c所示， 其中通孔 17和应力通道隔 离层 19可以通过光刻结合刻蚀形成。 然后， 优选在上述器件上沉积一层介 质材料， 如氮化物层， 例如可以采用化学气相沉积等方法。 接着， 对上述 器件上的氮化物层进行刻蚀，并在应力释放通道 15的上部保留一薄层氮化 物层 11。 应力释放层包括应力释放通道 15以及氮化物层 11。 然后在应力 通道隔离层 19 的侧壁上首先可以形成绝缘层 18, 例如将氧化物或者氮化 物 （如 Si3N4 ) 等绝缘材料沉积到通孔 17 中。 接着， 可选地， 还可以在绝 缘层 18的侧壁上沉积阻挡层 20, 阻挡层 20可以防止后续工艺中填充到通 孔 17 中的导电材料向外迁移， 进入半导体器件中从而破坏半导体器件 14 的性能。 在本发明的实施例中， 阻挡层 20的材料包括 Ru、 Ta、 TaN、 Ti、 TiN、 TaSiN、 TiSiN、 TiW以及 WN中的一种或多种的组合。
最后， 在通孔 17 中填充导电材料以形成导电塞 22, 其中， 导电材料 包括例如铜 （Cu ) 、 铝（A1 )或者钨（W ) 的金属， 也可以是导电聚合物、 金属硅化物等等， 从而形成用于 3D集成电路晶片互连的 TSV孔。 在本发 明实施例中，导电塞 22为金属材料，然后对整个晶片结构进行平坦化处理， 如化学机械抛光（CMP ) , 从而形成 TSV孔。 关于 TSV孔的形成可以是 现有任意合适的工艺方法， 本发明对此不作限定。
图 7d显示了连接半导体器件 14与 TSV孔的互连结构的结构示意图， 其中互连结构包括形成在 MOSFET晶体管 14对应的后道互连结构 16上方 的过孔 24、 以及连接过孔 24与 TSV孔的金属互连线 28。 这样， 通过上述 互连结构可以将 TSV孔与半导体器件 14连接起来。 从而， 通过进一步将 该晶片上的互连结构与其他晶片对应的互连结构进行多晶片连接， 则可以 实现 3D集成电路结构。
为了将图 7d结构的晶片与其他晶片连接形成 3D集成电路， 或者为形 成的 3D集成电路供电， 需要将对应的晶片底部的 TSV孔进行研磨或者打 薄处理， 从而暴露出 TSV孔中的金属材料以进行相应的导电连接。
如图 7e所示， 对晶片底部进行研磨或减薄处理， 从而暴露晶片底部的 TSV孔中的导电塞 22。
通过上述步骤， 即得到图 7e所示用于 3D集成电路的晶片 3。
图 8、图 9给出了利用图 7a-7e实施例的晶片 3形成的第二实施例的 3D 集成电路的部分结构。
如图 8所示，则为根据本发明的一个实施例得到的一个 3D集成电路结 构。 其中， 该 3D集成电路结构包括晶片 3 , 其中晶片 3包括： 村底 2; 形 成在村底上的半导体器件 14, 以及形成在村底 2及器件 14上的介质层 4; 贯穿村底 2、 介质层 4形成的通孔 17 , 通孔 17内形成有导电材料层； 包围 通孔 17的应力释放层； 以及连接器件 14与通孔 17的第一互连结构。
其中， 应力释放层可以为应力释放通道 15。 并且， 应力释放层中可以 包括至少覆盖应力释放通道 15 —部分的空气、 聚合物、 橡胶、 塑料中的任 一种或多种的组合。 优选地， 应力释放层中可以包括至少覆盖应力释放通 道 15—部分的介质材料 11。
其中， 导电材料层包括内层导电塞 22和外层阻挡层 20。 阻挡层 20的 材料包括 Ru、 Ta、 TaN、 Ti、 TiN、 TaSiN、 TiSiN、 TiW以及 WN中的任 一种或多种的组合。
优选地， 该 3D集成电路结构中还包括形成于通孔 17与应力释放层之 间的应力通道隔离层 19。 优选地， 通孔 17的侧壁上有绝缘层 18, 绝缘层 18将通孔 17与导电材料层之间隔离， 该绝缘层能加强导电材料层与晶片 上其他结构之间的隔离作用。
在图 8中，显示了形成 3D集成电路的晶片 3与外部电源 300的连接示 意图， 其中晶片 3暴露的导电塞 22连接到外部电源 300, 从而为 3D集成 电路供电。
在图 9中，除了显示 3D集成电路的晶片 3与外部电源 300的连接之外， 还显示了晶片 3与 3D集成电路的另一个晶片 4的连接示意图。如图 9所示， 晶片 4上设置有过孔 42, 过孔 42与晶片 4上构建的半导体器件 45的后道 互连 43连接。 晶片 4的半导体器件 45、 后道互连 43以及过孔 42的构建 与晶片 3相同， 即半导体器件 45设置在硅层 44上方的介质层 46, 过孔 42 设置在介质层 46上方的介质层 48中。
这样， 晶片 3通过其互连结构 （即过孔 24以及金属互连线 28 ) 与过 孔 42连接， 从而将晶片 3的 TSV孔连接到晶片 4上， 即以顶对底的形式 连接晶片 3和晶片 4, 实现 3D集成电路的多晶片堆叠结构。
在本发明中， 对于构建在硅村底上的半导体器件， 通过设置应力通道 释放层以释放一部分通孔中的导电材料产生的应力，减少了与周围半导体（如 硅）之间 CTE不匹配产生的应力， 从而提高半导体器件及相应构成的 3D集 成电路的性能。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言， 可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多 种变化、 修改、 替换和变型， 本发明的范围由所附权利要求及其等同限定。

Claims

权 利 要 求
1. 一种 3D集成电路结构， 其特征在于， 所述集成电路结构包括第一 晶片， 其中第一晶片包括：
村底；
形成在所述村底上的半导体器件， 以及形成在所述村底及所述器件上 的介质层；
贯穿所述村底、 所述介质层形成的通孔， 所述通孔内形成有导电材料 层；
包围所述通孔的应力释放层； 以及
连接所述器件与所述通孔的第一互连结构。
2. 如权利要求 1所述的集成电路结构， 其特征在于， 所述应力释放层 包括应力释放通道。
3. 如权利要求 2所述的集成电路结构， 其特征在于， 所述应力释放层 中包括至少覆盖所述应力释放通道一部分的空气、 聚合物、 橡胶、 塑料中 的任一种或多种的组合。
4. 如权利要求 2或 3所述的集成电路结构， 其特征在于， 所述应力释 放层中包括至少覆盖所述应力释放通道一部分的介质材料。
5. 如权利要求 1所述的集成电路结构， 其特征在于， 所述导电材料层 包括内层导电塞和外层阻挡层。
6. 如权利要求 5所述的集成电路结构， 其特征在于， 所述阻挡层的材 料包括 Ru、 Ta、 TaN、 Ti、 TiN、 TaSiN、 TiSiN、 TiW以及 WN中的任一 种或多种的组合。
7. 如权利要求 1所述的集成电路结构， 其特征在于， 还包括形成于所 述通孔与应力释放层之间的应力通道隔离层。
8. 如权利要求 1所述的集成电路结构， 其特征在于， 所述通孔的侧壁 上有绝缘层， 所述绝缘层将所述通孔与导电材料层之间隔离。
9. 如权利要求 1-3、 5-8中任一项所述的集成电路结构， 其特征在于， 还包括第二晶片， 所述第二晶片包括： 村底； 形成在所述村底上的半导体 连接所述器件的第二互连结构； 其中， 所述第一晶片通过其所述第一互连 结构连接到所述第二晶片的所述第二互连结构上。
10. 一种形成 3D集成电路的方法， 其特征在于， 包括以下步骤：
A、 提供第一晶片， 其中所述第一晶片包括： 村底、 半导体器件以及介 质层， 其中， 所述器件形成在所述村底上， 所述介质层形成在所述村底及 器件上；
B、形成贯穿所述村底以及所述介质层的通孔和应力释放层， 其中所述 应力释放层将所述通孔包围；
C、 填充所述通孔以形成导电材料层；
D、 形成连接所述器件与所述通孔的第一互连结构。
11. 如权利要求 10所述的方法， 其特征在于， 所述步骤 B包括： 根据需要形成的通孔和应力释放层的图形形成光刻胶图案；
根据所述光刻胶图案对所述村底和介质层进行刻蚀， 以形成通孔和应 力释放通道；
其中， 所述应力释放通道形成应力释放层， 所述通孔和应力释放层之 间为应力通道隔离层。
12. 如权利要求 11所述的方法， 所述步骤 B与步骤 C之间还包括： 采 用空气、 聚合物、 橡胶、 塑料中的任一种或多种的组合填充所述应力释放 通道。
13. 如权利要求 11或 12所述的方法， 所述步骤 B与步骤 C之间还包
14. 如权利要求 10所述的方法， 其特征在于， 所述步骤 B与步骤 C之 间， 进一步包括： 在所述通孔内壁形成绝缘层。
15. 如权利要求 10所述的方法， 其特征在于， 所述步骤 D包括： 在所述通孔内壁形成外层阻挡层；
在所述外层阻挡层内形成内层导电塞。
16. 如权利要去 15所述的方法， 其特征在于， 所述阻挡层的材料包括 Ru、 Ta、 TaN、 Ti、 TiN、 TaSiN、 TiSiN、 TiW 以及 WN 中的任一种或多 种的组合。
17. 如权利要求 10-12、 14-16中任一项所述的方法， 其特征在于， 还 包括：
提供第二晶片， 其中所述第二晶片包括： 村底、 半导体器件、 介质层 以及第二互连结构， 其中， 所述器件形成在所述村底上， 所述介质层形成 在所述村底及器件上， 所述第二互连结构形成在所述介质层中且连接所述 器件；
将所述第一晶片的所述第一互连结构连接到所述第二晶片的所述第二 互连结构上。
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