TWI646643B - 用於著陸在不同接觸區階層的接觸方案 - Google Patents

用於著陸在不同接觸區階層的接觸方案 Download PDF

Info

Publication number
TWI646643B
TWI646643B TW106132446A TW106132446A TWI646643B TW I646643 B TWI646643 B TW I646643B TW 106132446 A TW106132446 A TW 106132446A TW 106132446 A TW106132446 A TW 106132446A TW I646643 B TWI646643 B TW I646643B
Authority
TW
Taiwan
Prior art keywords
contact
level
crossover
forming
item
Prior art date
Application number
TW106132446A
Other languages
English (en)
Other versions
TW201909362A (zh
Inventor
卡斯坦Ｋ 彼得斯
彼得 貝爾斯
Original Assignee
美商格芯（美國）集成電路科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商格芯（美國）集成電路科技有限公司 filed Critical 美商格芯（美國）集成電路科技有限公司
Application granted granted Critical
Publication of TWI646643B publication Critical patent/TWI646643B/zh
Publication of TW201909362A publication Critical patent/TW201909362A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5221—Crossover interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本揭露係關於一種半導體結構，特別是，係關於用於著陸在半導體結構之不同接觸區階層上的接觸方案及製造方法。該結構包括：在該結構之第一階層處之一第一接觸；在該結構之第二較高階層處之一跨接接觸；一蝕刻停止層，其具有在該第一接觸上方之一開口且部份囊封該跨接接觸，其中一開口暴露該跨接接觸；與在該第一階層處之該第一接觸及在該第二較高階層處之該跨接接觸通過該等開口電接觸之接觸。

Description

用於著陸在不同接觸區階層的接觸方案
本揭露係關於一種半導體結構，特別是，係關於用於著陸在半導體結構之不同接觸區階層上的接觸方案及製造方法。
電晶體為現代數位處理器及記憶裝置之基本裝置元件，且已發現在各種電子領域中之數種應用，包括：資料處理、資料儲存、及高功率應用。目前，用於不同的應用中，存在各種電晶體類型及設計。例如，各種電晶體類型包括雙極性接面電晶體(BJT)、接面場效電晶體(JFET)、金屬氧化物半導體場效電晶體(MOSFET)、垂直通道或溝槽場效電晶體、及超接面或多汲極電晶體。
在電晶體之MOSFET族群內，全空乏型絕緣體上矽(FDSOI)平台可達成良好的性能而不增加功率消耗及成本。在一FDSOI平台中，在一絕緣層(例如：埋入式氧化物(BOX)層)上形成一半導體層(諸如矽、鍺、矽鍺等)，接著將其在一半導體裝置上形成。該FDSOI平台之空乏區域覆蓋該半導體層，其可達成高切換速度。
在本揭露之一態樣中，一結構包括：在該結構之第一階層處 之一第一接觸；在該結構之第二較高階層處之一跨接接觸；一蝕刻停止層，其具有在該第一接觸上方之一開口且部份囊封該跨接接觸，其中一開口暴露該跨接接觸；以及與在該第一階層處之該第一接觸及在該第二較高階層處之該跨接接觸通過該等開口電接觸之接觸。
在本揭露之一態樣中，一方法包括：在一結構之第一階層處形成一第一接觸；在該結構之第二較高階層處形成一跨接接觸；形成一蝕刻停止層，其具有在該第一接觸上方之一開口及在該跨接接觸上方之一開口；以及形成接觸，其與在該第一階層處之該第一接觸及在該第二較高階層處之該跨接接觸通過該蝕刻停止層之該等開口電接觸。
在本揭露之一態樣中，一方法包括：在一基板上形成一閘極結構；在該基板上形成一抬升式源極/汲極區域；在一第一階層處形成對該閘極結構之一第一接觸；在該第一階層處形成對該抬升式源極/汲極區域之一第二接觸；相對於該第一階層，在一第二較高階層處形成對該第二接觸區域之一跨接接觸；以及形成雙鑲嵌銅接線結構，其著陸在該第一階層處之該第一接觸上及在該第二較高階層處之該跨接接觸上。
5‧‧‧結構
10‧‧‧層間介電質(ILD)
15‧‧‧接觸
20‧‧‧接觸
25‧‧‧障壁層
30‧‧‧矽化物區域
35‧‧‧側壁
40‧‧‧覆蓋層
45‧‧‧閘極結構
50‧‧‧抬升式源極/汲極
55‧‧‧絕緣體上矽(SOI)基板
60‧‧‧埋入式氧化物(BOX)層
65‧‧‧蝕刻停止層
70‧‧‧層間介電層(ILD)
75‧‧‧硬遮罩
77‧‧‧開口
80‧‧‧襯裡材料
85‧‧‧跨接接觸
90‧‧‧絕緣材料
95‧‧‧材料
97‧‧‧開口
99‧‧‧通孔
99'‧‧‧溝槽
99"‧‧‧溝槽
100‧‧‧硬遮罩
105‧‧‧有機平坦化層(OPL)
110‧‧‧金屬
115‧‧‧金屬
本揭露藉由本揭露之例示性實施例之非限制實例參照所述諸圖式描述在以下之實施方式中。
圖1顯示根據本揭露之態樣之進入結構及各別製造過程。
圖2顯示根據本揭露之態樣之除其它特徵外具一蝕刻停止層之結構及各別之製造過程。
圖3顯示根據本揭露之態樣之除其它特徵外具鎢填充之結構及各別之製造過程。
圖4顯示根據本揭露之態樣之除其它特徵外平坦化鎢填充後之結構及各別之製造過程。
圖5顯示根據本揭露之態樣之除其它特徵外具一插塞之結構及各別之製造過程。
圖6顯示根據本揭露之態樣之除其它特徵外具在該插塞及其它表面上之一蝕刻停止層之結構及各別之製造過程。
圖7顯示根據本揭露之態樣之除其它特徵外具低介電膜、硬遮罩、及金屬之結構及各別之製造過程。
圖8顯示根據本揭露之態樣之除其它特徵外具平坦化材料之結構及各別之製造過程。
圖9顯示根據本揭露之態樣之除其它特徵外具形成至二個不同階層之接觸通孔之結構及各別之製造過程。
圖10顯示根據本揭露之態樣之除其它特徵外具在一較高階層處及一較低階層處之金屬填充之結構及各別之製造過程。
本揭露係關於一種半導體結構，且特定而言，係關於用於著陸在半導體結構之不同接觸區階層上的接觸方案及製造方法。更特定而言，本揭露係關於一半導體結構，其中中段(MOL)構造具有局部互連(例如：跨接件)及閘極飛跨特徵，其等併入一閘極階層上之該層間介電質(ILD)內。有利地，本揭露提供藉由提供在兩個不同階層上之通孔結構以接線/連接的益處。
在數個MOL方法中，鎢(即W)層置於後續階層中，其與通孔階層V0處之銅通孔接觸。由於通孔蝕刻極度敏感，該銅通常可僅著陸在相同的下層階層上。相比之下，本揭露使該銅通孔可著陸在不同之MOL階層上。在特定實施例中，氮化物襯裡可作為在兩個不同階層上之一蝕刻停止層。例如，可使用一氮化物襯裡來覆蓋一較低接線階層且囊封一較高接線階層。在一ILD層中蝕刻一通孔，其使用該蝕刻停止層使其可著陸在兩 個不同階層上之金屬接觸上。在實施例中，該半導體結構可係全空乏型絕緣體上矽(FDSOI)技術，但本文亦考量塊體CMOS裝置。
本揭露之半導體結構可使用數種不同工具以數種方式製造。但一般而言，使用該等方法及工具以形成尺寸在微米及奈米等級之結構。用來製造本揭露之半導體結構之方法(即技術)已採用自積體電路(IC)技術。例如，該等結構建構在晶圓上且以在晶圓之頂部上藉由光微影製程圖案化之材料膜實現。尤其，半導體結構之製造使用三個基本的建構區塊：(i)在一基板上沉積薄膜材料，(ii)在該等膜之頂部上藉由光微影成像施加圖案化遮罩，及(iii)選擇性地對該遮罩蝕刻該等膜。
圖1顯示根據本揭露之態樣之進入結構及各別製造過程。更特定而言，圖1之結構5包括在一埋入式氧化物(BOX)層60上形成之一絕緣體上矽(SOI)基板55。在實施例中，該SOI基板55之半導體材料可以包含(但不限於)Si、SiGe、SiGeC、SiC、GaAs、InAs、InP、及任何其它III/V或II/VI複合半導體。儘管圖1顯示一SOI基板55，本文亦考量塊材基板。在該基板55上形成一抬升式源極/汲極50。除其它實例外，該抬升式源極/汲極50可在該基板55上磊晶生長。
使用本技術領域中具有通常知識者已知之習知沉積及圖案化製程在該基板55上形成一閘極結構45。該閘極結構45可包括例如閘極介電材料及多晶矽或其它金屬或金屬合金。側壁35可在該閘極結構45上形成。該等側壁35可係使用習知沉積技術(例如：化學氣相沉積法(CVD))沉積之例如氮化物材料。可在該閘極結構45及該抬升式源極/汲極50之一頂表面上形成矽化物區域30。除其它實例外，該矽化物區域30可藉由沉積一金屬層及退火該金屬層以將該金屬轉化成矽化物來形成。
圖1進一步顯示一覆蓋層40沉積在該基板55、該矽化物30、及該絕緣層60之暴露部份上方。在實施例中，該覆蓋層可係一氮化物覆蓋層，其使用例如CVD之習知沉積方法沉積。在該覆蓋層40上方沉積 一層間介電質(ILD)10。該層間介電質(ILD)10可包括二氧化矽(SiO2)或四 乙基正矽酸鹽(TEOS)，但亦可使用其它材料。作為一實例，通過ILD 10形 成接觸15及接觸20，其與該源極/汲極50及該閘極結構45之矽化物區域 30接觸。可藉由習知微影、蝕刻及沉積製程，接著藉由一化學機械平坦化 (CMP)製程形成該等接觸15、接觸20。該等接觸15、接觸20可以鎢(即 W)填充，以一障壁層/襯裡25(例如：TaN/TiN)鋪襯裡。進一步地，該接觸 15係與該接觸20在同一階層。
在圖2中，在該等接觸15、接觸20上方沉積一蝕刻停止層65。該蝕刻停止層65可藉由習知沉積方法(例如：CVD)沉積。在實施例中，該蝕刻停止層65可係氮化矽(SiN)，但本文亦考量其它選擇性材料。除其它實例外，使用CVD製程在該蝕刻停止層65上方沉積一層間介電層70。在實施例中，該層間介電層(ILD)70可係四乙基正矽酸鹽(TEOS)或其它絕緣材料。
再參照圖2，除其它實例外，可使用CVD製程在該層間介電層70上沉積一硬遮罩75。可沉積該硬遮罩75用於中段(MOL)局部互連/飛跨特徵。在實施例中，該硬遮罩75可包括一光微影光阻且為抗反射性。如進一步顯示，可使用習知的微影及蝕刻製程(例如：反應性離子蝕刻(RIE))將硬遮罩75圖案化(例如：開口77)。
如圖3所示，蝕刻該層間介電質(ILD)70以形成一開口，其在該蝕刻停止層65上停止。接著進行一第二蝕刻製程以移除該蝕刻停止層65之部份，暴露該下層接觸15。在該經蝕刻ILD 70上方沉積一襯裡材料80並與該接觸15接觸。在一實施例中，該襯裡材料80可係例如TaN/TiN。在沉積該襯裡材料80後，鎢材料85填充該餘留開口以與該接觸15電接觸。
在圖4中，對該填充材料85進行化學機械平坦化(CMP)。在實施例中，該填充材料85為一跨接/飛跨特徵(即：跨接接觸85)，其為該等接觸15、接觸20上之一階層。該跨接接觸85與該接觸15電接觸。在圖 5中，如箭頭所指示藉由一濕式氧化物蝕刻製程移除該ILD 70。在實施例中，該濕式氧化物移除製程可係一氫氟酸(HF)蝕刻製程，其在該蝕刻停止層65上停止。以此方式，在該濕式氧化物移除製程期間下層特徵可受到保護。此製程亦將由該填充材料產生鎢插塞，例如：特徵85(即：跨接接觸85)。
在圖6中，可再沉積在蝕刻製程期間之任何移除之該蝕刻停止層65。例如，藉由一沉積製程增厚該蝕刻停止層65，其覆蓋該接觸20且現亦囊封該插塞85(即：跨接/飛跨)。除其它實例外，可藉由一CVD製程沉積該蝕刻停止層65。在實施例中，該蝕刻停止層65可係SiN。
在圖7中，使用例如一CVD製程在該蝕刻停止層65上方沉積一絕緣材料90(例如：低k介電質)。在實施例中，該絕緣材料90可係SiCOH或其它絕緣材料。例如，該絕緣材料90可係一低k介電質(BLOK)。對該絕緣材料90進行一CMP製程。在該低k介電材料上沉積一材料95(例如：TiN)及一硬遮罩100。使用習知微影及蝕刻製程在該材料95及該硬遮罩100中形成至少一開口97。可藉由習知剝離劑及/或蝕刻製程移除該微影堆疊之任何硬遮罩及/或其它材料。
除其它實例外，在圖8中藉由CVD製程在該材料95上沉積一有機平坦化層(OPL)105。該有機平坦化層(OPL)105亦沉積在該等開口97內及該材料90上方。在該OPL 105上沉積一硬遮罩100(例如：光微影堆疊)，接著對其進行微影製程。尤其，該微影製程為一溝槽優先通孔最後方案。
在圖9中，在該OPL 105中形成一通孔99，其在兩個不同階層上之該蝕刻停止層65處停止。使用一第二蝕刻製程利用該硬遮罩材料95之通孔99之一圖案化開口在該絕緣材料90中形成溝槽99'及溝槽99"。在實施例中，該通孔99及該等溝槽99'、溝槽99"之圖案化可為一雙鑲嵌製程，其亦移除該蝕刻停止層65之一部份(形成一開口)以暴露該插塞85及該接觸20兩者。
在圖10中，進行一電鍍製程以鋪襯裡並填充該等通孔及該等溝槽99、溝槽99'、溝槽99"。尤其，該電鍍製程包括沉積一障壁層、一金屬晶種層及電鍍製程。在完成該電鍍製程後，在該等通孔及該等溝槽99、溝槽99'、溝槽99"之空間內沉積一金屬110、金屬115。除其它實例外，該障壁層之沉積可使用一電漿輔助化學氣相沉積(PECVD)製程完成。在一實施例中，該障壁層可係氮化鈦(TiN)或氮化鉭(TaN)中之一者，但可使用其它材料。作為一實例，該金屬110、金屬115可為銅(Cu)，其接觸在不同階層處之鎢接觸20、鎢接觸85(例如在第一階層處之鎢接觸20及在第二較高階層處之鎢接觸85)。接著該金屬材料可進行一平坦化製程，例如CMP，因此在一較高階層處形成一金屬化層/接線層110及在一較低階層處形成一接觸115，其分別接觸該鎢插塞(即：跨接接觸)85及該接觸20。即，該等接觸金屬110、接觸金屬115著陸在兩個不同之階層上，直接著陸並接觸在兩個不同接觸85、接觸20上。該金屬化層/接線層110及該接觸115可係延伸至該結構較高階層的雙鑲嵌結構。
上述之方法用在積體電路晶片之製造。所得積體電路晶片可以原晶圓形式(即，作為一單一晶圓，其具有多個未封裝晶片)、作為一裸晶粒、或以封裝形式由製造者分配。在後者情況下，該晶片係安裝在一單一晶片封裝中(諸如一塑膠載體，具有固定在母板或其它較高級載體之導線)或在一多晶片封裝中(諸如一陶瓷載體，其具有表面互連或埋入互連之任一者或兩者)。接著在任何情況下，該晶片與其它晶片、離散電路元件、及/或其它信號處理裝置整合為(a)一中間產品，諸如母板，或(b)一最終產品任一者之部分。該最終產品可係任何產品，其包括積體電路晶片，範圍自玩具及其它低端應用至具有顯示器、鍵盤或其它輸入裝置之先進電腦產品，以及一中央處理器。
本揭露之各種實施例之描述已針對說明之目的而呈現，但未意欲詳盡或限制所揭示之實施例。在不背離本描述實施例之範疇與精神下 之許多修正及變化對於所屬技術領域中具有通常知識者為顯而易見的。本文所用術語經選擇以最佳地解釋該等實施例之原理、實施應用或優於市場上所見之技術的技術改善，或可使其他所屬技術領域中具有通常知識者了解本文揭示之實施例。

Claims (20)

  1. 一種半導體元件的結構，其包含：一第一接觸，在該結構之一第一階層處；一跨接接觸，在該結構之一第二較高階層處；一蝕刻停止層，其具有在該第一接觸上方之一開口且部份囊封該跨接接觸，其中一開口暴露該跨接接觸；以及多個接觸，與在該第一階層處之該第一接觸及在該第二較高階層處之該跨接接觸通過該等開口電接觸。
  2. 如申請專利範圍第1項所述之結構，其中該跨接接觸與在與該第一接觸相同之階層處之一第二接觸電接觸。
  3. 如申請專利範圍第2項之結構，其中該跨接接觸係一鎢插塞結構。
  4. 如申請專利範圍第2項所述之結構，其中該第一接觸與一閘極結構電接觸且該第二接觸與在該結構之該第一階層處之該閘極結構之一源極/汲極電接觸。
  5. 如申請專利範圍第4項所述之結構，其中該源極/汲極區域係一抬升式源極/汲極區域。
  6. 如申請專利範圍第5項所述之結構，其中該等接觸係延伸至該結構之不同階層之銅。
  7. 如申請專利範圍第1項所述之結構，其中該第一接觸及該跨接接觸係鎢。
  8. 如申請專利範圍第1項所述之結構，其中該等接觸係雙鑲嵌結構，延伸至該結構之較高階層。
  9. 如申請專利範圍第1項所述之結構，其中該等接觸係與該跨接接觸和該第一接觸為不同之材料。
  10. 一種半導體元件的製造方法，其包含：在一結構之一第一階層處形成一第一接觸；在該結構之一第二較高階層處形成一跨接接觸；形成一蝕刻停止層，其具有在該第一接觸上方之一開口及在該跨接接觸上方之一開口；以及形成多個接觸，該等接觸與在該第一階層處之該第一接觸及在該第二較高階層處之該跨接接觸通過該蝕刻停止層之該等開口電接觸。
  11. 如申請專利範圍第10項所述之方法，進一步包含：在該第一階層處形成一第二接觸，該第一接觸接觸一閘極結構及該第二接觸接觸一抬升式源極/汲極區域。
  12. 如申請專利範圍第11項所述之方法，其中形成該跨接接觸以與該第二接觸電連接，以及該第一接觸、該第二接觸、及該跨接接觸具有相同材料。
  13. 如申請專利範圍第11項所述之方法，其中藉由一雙鑲嵌製程形成該等接觸，其填充有與該跨接接觸及該第一接觸直接接觸之一銅材料。
  14. 如申請專利範圍第10項所述之方法，其中以該蝕刻停止層囊封該跨接接觸，且在該第一階層上在該蝕刻停止層之另一開口中形成該跨接接觸。
  15. 如申請專利範圍第10項所述之方法，進一步包含在該蝕刻停止層上方形成一層間介電質。
  16. 如申請專利範圍第15項所述之方法，進一步包含藉由一濕式氧化物蝕刻製程蝕刻該層間介電質，其在該蝕刻停止層上停止以允許該跨接接觸之囊封及該蝕刻停止層之增厚。
  17. 一種半導體元件的製造方法，其包含：在一基板上形成一閘極結構；在該基板上形成一抬升式源極/汲極區域；在一第一階層處形成對該閘極結構之一第一接觸；在該第一階層處形成對該抬升式源極/汲極區域之一第二接觸；相對於該第一階層處，在一第二較高階層處形成對該第二接觸區域之一跨接接觸；以及形成一雙鑲嵌銅接線結構，其著陸在該第一階層處之該第一接觸上及在該第二較高階層處之該跨接接觸上。
  18. 如申請專利範圍第17項所述之方法，進一步包含以一蝕刻停止層囊封該跨接接觸。
  19. 如申請專利範圍第17項所述之方法，其中該雙鑲嵌銅接線結構之形成包括經由在該第一接觸之一頂表面上及該跨接接觸之一停止表面上之該蝕刻停止層蝕刻。
  20. 如申請專利範圍第17項所述之方法，其中該跨接接觸、該第一接觸、及該第二接觸包括鎢材料。
TW106132446A 2017-07-25 2017-09-21 用於著陸在不同接觸區階層的接觸方案 TWI646643B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/658,570 2017-07-25
US15/658,570 US10157774B1 (en) 2017-07-25 2017-07-25 Contact scheme for landing on different contact area levels

Publications (2)

Publication Number Publication Date
TWI646643B true TWI646643B (zh) 2019-01-01
TW201909362A TW201909362A (zh) 2019-03-01

Family

ID=64604817

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106132446A TWI646643B (zh) 2017-07-25 2017-09-21 用於著陸在不同接觸區階層的接觸方案

Country Status (4)

Country Link
US (1) US10157774B1 (zh)
CN (1) CN109300876B (zh)
DE (1) DE102017219677B4 (zh)
TW (1) TWI646643B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10804140B2 (en) * 2018-03-29 2020-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect formation and structure
US10978388B2 (en) * 2018-10-08 2021-04-13 International Business Machines Corporation Skip via for metal interconnects
US11244859B2 (en) * 2019-10-10 2022-02-08 International Business Machines Corporation Interconnects having a via-to-line spacer for preventing short circuit events between a conductive via and an adjacent line
CN113130380B (zh) * 2019-12-30 2024-01-26 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11114153B2 (en) * 2019-12-30 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. SRAM devices with reduced coupling capacitance
US20220254927A1 (en) * 2021-02-11 2022-08-11 Taiwan Semiconductor Manfacturing Co., Ltd. Gate contact and via structures in semiconductor devices
US11728272B2 (en) * 2021-03-31 2023-08-15 Taiwan Semiconductor Manufacturing Company Limited Plasma-damage-resistant interconnect structure and methods for manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103378033A (zh) * 2012-04-27 2013-10-30 台湾积体电路制造股份有限公司 衬底通孔及其形成方法
TW201725682A (zh) * 2016-01-14 2017-07-16 台灣積體電路製造股份有限公司 積體電路

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5451543A (en) 1994-04-25 1995-09-19 Motorola, Inc. Straight sidewall profile contact opening to underlying interconnect and method for making the same
US6071784A (en) * 1997-08-29 2000-06-06 Advanced Micro Devices, Inc. Annealing of silicon oxynitride and silicon nitride films to eliminate high temperature charge loss
US7042095B2 (en) * 2002-03-29 2006-05-09 Renesas Technology Corp. Semiconductor device including an interconnect having copper as a main component
US6746914B2 (en) * 2002-05-07 2004-06-08 Chartered Semiconductor Manufacturing Ltd. Metal sandwich structure for MIM capacitor onto dual damascene
DE10324433B4 (de) * 2003-05-28 2007-02-08 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Substratkontakts für ein SOI-Halbleiterbauteil
US8042095B2 (en) 2004-08-13 2011-10-18 National Instruments Corporation Application development environment with features for increasing the ease and efficiency of viewing function help text
KR100755365B1 (ko) * 2005-02-15 2007-09-04 삼성전자주식회사 엠. 아이. 엠 커패시터들 및 그 형성방법들
KR100629270B1 (ko) * 2005-02-23 2006-09-29 삼성전자주식회사 낸드형 플래시 메모리 소자 및 그 제조방법
JP2010205908A (ja) * 2009-03-03 2010-09-16 Toshiba Corp 半導体装置およびその製造方法
JP2012043868A (ja) * 2010-08-16 2012-03-01 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
KR101908358B1 (ko) * 2011-05-24 2018-12-11 삼성전자주식회사 금속 플러그를 갖는 반도체 소자 및 그 형성 방법
JP2013165224A (ja) * 2012-02-13 2013-08-22 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法
US8921226B2 (en) * 2013-01-14 2014-12-30 United Microelectronics Corp. Method of forming semiconductor structure having contact plug
US9129876B2 (en) * 2013-05-28 2015-09-08 United Microelectronics Corp. Image sensor and process thereof
US9431296B2 (en) * 2014-06-26 2016-08-30 International Business Machines Corporation Structure and method to form liner silicide with improved contact resistance and reliablity
US9748232B2 (en) * 2014-12-31 2017-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US20160336183A1 (en) 2015-05-14 2016-11-17 Globalfoundries Inc. Methods, apparatus and system for fabricating finfet devices using continuous active area design
US9685368B2 (en) * 2015-06-26 2017-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure having an etch stop layer over conductive lines
US9780199B2 (en) * 2015-09-23 2017-10-03 United Microelectronics Corp. Method for forming semiconductor device
US10032828B2 (en) 2016-07-01 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor memory device and method for fabricating the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103378033A (zh) * 2012-04-27 2013-10-30 台湾积体电路制造股份有限公司 衬底通孔及其形成方法
TW201725682A (zh) * 2016-01-14 2017-07-16 台灣積體電路製造股份有限公司 積體電路

Also Published As

Publication number Publication date
DE102017219677A1 (de) 2019-01-31
US10157774B1 (en) 2018-12-18
DE102017219677B4 (de) 2021-03-11
CN109300876B (zh) 2022-03-04
CN109300876A (zh) 2019-02-01
TW201909362A (zh) 2019-03-01

Similar Documents

Publication Publication Date Title
TWI646643B (zh) 用於著陸在不同接觸區階層的接觸方案
US10224280B2 (en) Backside device contact
KR101742925B1 (ko) 다마신 구조물의 구조물 및 형성방법
US7626257B2 (en) Semiconductor devices and methods of manufacture thereof
US20220208749A1 (en) Semiconductor devices and methods of manufacture thereof
US20210111119A1 (en) Via Structure and Methods Thereof
US8846452B2 (en) Semiconductor device package and methods of packaging thereof
TWI671852B (zh) 用於共用基板的電路的隔離結構
TW202143335A (zh) 封裝半導體元件及其形成方法
WO2012041034A1 (zh) 3d集成电路结构及其形成方法
CN108511386B (zh) 分段式防护环及芯片边缘密封件
TW202141655A (zh) 半導體裝置及其製造方法
CN104051328A (zh) 用于半导体器件制造的图案化方法
US10096689B2 (en) Low end parasitic capacitance FinFET
TW202145484A (zh) 半導體裝置
TWI729283B (zh) 接觸結構
TWI809525B (zh) 在環繞式閘極電晶體之間具有氣隙之半導體元件及其製備方法
US10204861B2 (en) Structure with local contact for shorting a gate electrode to a source/drain region
US20230187510A1 (en) Angled via for tip to tip margin improvement
TWI798887B (zh) 著陸墊下方具有氣隙的半導體元件及其製備方法
TW202343728A (zh) 具有複合瓶狀矽穿孔的半導體元件結構及其製備方法