CN109300876A - 位于不同接触区域层级上的接触方案 - Google Patents

位于不同接触区域层级上的接触方案 Download PDF

Info

Publication number
CN109300876A
CN109300876A CN201711017950.5A CN201711017950A CN109300876A CN 109300876 A CN109300876 A CN 109300876A CN 201711017950 A CN201711017950 A CN 201711017950A CN 109300876 A CN109300876 A CN 109300876A
Authority
CN
China
Prior art keywords
contact
level
bridging
etching stopping
stopping layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201711017950.5A
Other languages
English (en)
Other versions
CN109300876B (zh
Inventor
C·K·彼得斯
P·巴尔斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Publication of CN109300876A publication Critical patent/CN109300876A/zh
Application granted granted Critical
Publication of CN109300876B publication Critical patent/CN109300876B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5221—Crossover interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明涉及位于不同接触区域层级上的接触方案。本公开涉及半导体结构，更具体地，涉及用于位于半导体结构的不同接触区域层级上的接触方案及其制造方法。该结构包括：在结构的第一层级处的第一接触；在结构的第二、更高层级处的跨接接触；蚀刻停止层，其具有在第一接触之上的开口，并且部分地包封跨接接触并具有暴露跨接接触的开口；以及通过开口与第一层级处的第一接触和第二、更高层级处的跨接接触电接触的接触。

Description

位于不同接触区域层级上的接触方案
技术领域
本公开涉及半导体结构，更具体地，涉及用于位于半导体结构的不同接触区域层级上的接触方案及其制造方法。
背景技术
晶体管是现代数字处理器和存储器件的基本器件元件，并且已经在包括数据处理、数据存储和大功率应用的各种电子领域中发现了许多应用。目前，存在可用于不同应用的各种晶体管类型和设计。各种晶体管类型包括例如双极结型晶体管(BJT)、结型场效应晶体管(JFET)、金属氧化物半导体场效应晶体管(MOSFET)、垂直沟道或沟槽场效应晶体管、以及超结或多漏极晶体管。
在MOSFET家族的晶体管中，完全耗尽的绝缘体上硅(FDSOI)平台能够在不增加功耗和成本的情况下实现良好的性能。在FDSOI平台中，诸如硅、锗、硅锗等的半导体层形成在例如掩埋氧化物层(BOX)层的绝缘体层上，该绝缘体层进而形成在半导体器件上。FD SOI平台的耗尽区覆盖半导体层，这可以实现高切换速度。
发明内容
在本公开的一个方面中，一种结构包括：在结构的第一层级处的第一接触；在结构的第二、更高层级处的跨接接触；蚀刻停止层，其具有在第一接触之上的开口，并且部分地包封跨接接触并具有暴露跨接接触的开口；以及通过开口与第一层级处的第一接触和第二、更高层级处的跨接接触电接触的接触。
在本公开的一方面，一种方法包括：在结构的第一层级形成第一接触；在结构的第二、更高层级处形成跨接接触；形成在第一接触之上具有开口并且开口在跨接接触之上的蚀刻停止层；以及通过蚀刻停止层的开口形成与第一层级处的第一接触和第二、更高层级处的跨接接触电接触的接触。
在本公开的一个方面，一种方法包括：在衬底上形成栅极结构；在衬底上形成凸起的源极/漏极区域；在第一层级处形成到栅极结构的第一接触；在第一层级处形成到凸起的源极/漏极区域的第二接触；在相对于第一层级的第二、更高层级处形成到第二接触区域的跨接接触；以及形成位于第一层级处的第一接触上和第二、更高层级处的跨接接触上的双镶嵌铜布线结构。
附图说明
在下面的详细描述中通过本公开的示例性实施例的非限制性示例参考所述多个附图来描述本公开。
图1示出了根据本公开的方面的进入结构和相应的制造工艺。
图2示出了根据本公开的方面的具有除其它特征之外的蚀刻停止层的结构以及相应的制造工艺。
图3示出了根据本公开的方面的具有除其它特征之外的钨填充的结构以及相应的制造工艺。
图4示出了根据本公开的方面的除其它特征之外的钨填充的平坦化之后的结构以及相应的制造工艺。
图5示出了根据本公开的方面的具有除其它特征之外的塞的结构以及相应的制造工艺。
图6示出了根据本公开的方面的具有在除其它特征之外的塞和其它表面上的蚀刻停止层的结构以及相应的制造工艺。
图7示出了根据本公开的方面的具有除其它特征之外的低介电膜、硬掩模和金属的结构以及各自的制造工艺。
图8示出了根据本公开的方面的具有除其它特征之外的平坦化材料的结构以及相应的制造工艺。
图9示出了根据本公开的方面的具有除其它特征之外的形成到两个不同层级的接触过孔的结构以及相应的制造工艺。
图10示出了根据本公开的方面的具有除其它特征之外的金属填充在更高层级和更低层级的结构以及相应的制造工艺。
具体实施方式
本公开涉及半导体结构，更具体地，涉及用于位于半导体结构的不同接触区域层级上的接触方案及其制造方法。更具体地，本公开涉及以下的半导体结构：其中中段制程(MOL)结构具有包含到栅极层级之上的层间电介质(ILD)中的局部互连(例如，跨接)和栅极架桥特征。有利地，本公开通过在两个不同的层级上提供过孔结构来提供布线/连接的益处。
在几种MOL方法中，钨(即，W)层被放置在随后的层级中，该层级与在过孔层级V0处的铜过孔接触。由于过孔蚀刻非常敏感，所以铜通常只能位于相同的下伏层级上。相反，本公开允许铜过孔位于不同的MOL层级上。在具体实施例中，氮化物衬里可以用作两个不同层级上的蚀刻停止层。例如，氮化物衬里可以用于覆盖更低的布线层级并包封更高的布线层级。使用蚀刻停止层在ILD层中蚀刻过孔，以使得它可以位于两个不同的层级上的金属接触上。在实施例中，半导体结构可以是完全耗尽的绝缘体上硅(FDSOI)技术，尽管在此也考虑了体CMOS器件。
本公开的半导体结构可以使用多种不同的工具以多种方式制造。通常，方法和工具用于形成尺寸在微米和纳米级的结构。已经从集成电路(IC)技术中采用了用于制造本公开的半导体结构的方法，即技术。例如，这些结构构建在晶片上，并且通过在晶片顶部上通过光刻工艺图案化的材料的膜来实现。具体地半导体结构的制造使用三个基本构建块：(i)在衬底上沉积材料的薄膜，(ii)通过光刻成像在膜的顶部上施加图案化掩模，以及(iii)将膜选择性地蚀刻到掩模。
图1示出了根据本公开的方面的进入结构和相应的制造工艺。更具体地，图1的结构5包括形成在掩埋氧化物(BOX)层60上的绝缘体上硅(SOI)衬底55。在实施例中，SOI衬底55的半导体材料可以是但不限于Si、SiGe、SiGeC、SiC、GaAs、InAs、InP和任何其它III/V或II/VI化合物半导体。尽管图1示出了SOI衬底55，但在此还考虑了体衬底。凸起的源极/漏极50形成在衬底55上。除了其它的示例之外，凸起的源极/漏极50可以外延生长在衬底55上。
使用本领域技术人员已知的常规沉积和图案化工艺在衬底55上形成栅极结构45。栅极结构45可以包括例如栅极介电材料和多晶或其它金属或金属合金。侧壁35可以形成在栅极结构45上。侧壁35可以是例如氮化物材料，使用例如化学气相沉积(CVD)的常规沉积技术来沉积。硅化物区域30可以形成在栅极结构45和凸起的源极/漏极50的顶表面上。除了其它的示例之外，硅化物区域30可以通过沉积金属层并退火金属层以将金属转变为硅化物而形成。
图1还示出了沉积在衬底55、硅化物30和绝缘体层60的暴露部分之上的覆盖层40。在实施例中，覆盖层可以是使用常规沉积方法(例如，CVD)沉积的氮化物覆盖层。层间电介质(ILD)10沉积在覆盖层40之上。层间电介质(ILD)10可以包括二氧化硅(SiO2)或原硅酸四乙酯(TEOS)，尽管可以使用其它材料。作为示例，接触15和20穿过ILD10形成，与源极/漏极50和栅极结构45的硅化物区域30接触。接触15、20可以通过常规光刻、蚀刻和沉积工艺以及随后是化学机械平坦化(CMP)工艺而形成。接触15、20可以用钨(即，W)填充，衬有阻挡层/衬里25(例如，Tan/TiN)。此外，接触15处于与接触20相同的层级。
在图2中，蚀刻停止层65沉积在接触15、20之上。蚀刻停止层65可以通过常规沉积方法(例如，CVD)来沉积。在实施例中，蚀刻停止层65可以是氮化硅(SiN)，尽管在此考虑了其它可选择材料。除了其它的示例之外，层间电介质层70使用CVD工艺沉积在蚀刻停止层65之上。在实施例中，层间电介质层(ILD)70可以是原硅酸四乙酯(TEOS)或其它绝缘体材料。
仍然参考图2，除了其它示例之外，硬掩模75可以使用CVD工艺沉积在层间电介质层70上。硬掩模75被沉积以用于中段制程(MOL)局部互连/架桥(flyover)特征。在实施例中，硬掩模75可以包括光刻抗蚀剂并且是抗反射的。如进一步所示，硬掩模75可以使用常规光刻和蚀刻工艺(例如，反应离子蚀刻(RIE))来图案化(例如，开口77)。
如图3所示，层间电介质(ILD)70被蚀刻以形成在蚀刻停止层65上停止的开口。然后第二蚀刻工艺被执行以去除蚀刻停止层65的部分，暴露下面的接触15。衬里80沉积在蚀刻的ILD70之上并与接触15接触。在一个实施例中，衬里80可以是例如TaN/TiN。在衬里80被沉积之后，钨材料85填充剩余的开口以与接触15电接触。
在图4中，填充材料85经受化学机械平坦化(CMP)。在实施例中，填充材料85是作为在接触15、20上面的一个层级的跨接/架桥特征(即，跨接接触85)。跨接接触85与接触15电接触。在图5中，通过如箭头所示的湿氧化物蚀刻工艺去除ILD70。在实施例中，湿氧化物去除工艺可以是在蚀刻停止层65上停止的氢氟酸(HF)蚀刻工艺。以这种方式，可以在湿氧化物去除工艺期间保护下面的特征。该过程也将从填充材料产生钨塞，例如特征85(即，跨接接触85)。
在图6中，在蚀刻工艺中的任何去除的蚀刻停止层65可以被重新沉积。例如，蚀刻停止层65通过沉积工艺被加厚，其覆盖接触20并且现在也包封塞85(即，跨接/架桥)。除了其它示例之外，蚀刻停止层65可以通过CVD工艺沉积。在实施例中，蚀刻停止层65可以是SiN。
在图7中，绝缘体材料90(例如，低k介电)使用例如CVD工艺沉积在蚀刻停止层65之上。在实施例中，绝缘体材料90可以是SiCOH或其它绝缘材料。例如，绝缘体材料90可以是低k介电(BLOK)。绝缘体材料90经受CMP工艺。例如TiN的材料95和硬掩模100沉积在低k介电材料上。至少一个开口97使用常规光刻和蚀刻工艺形成在材料95和硬掩模100中。光刻叠层的任何硬掩模和/或其它材料通过常规的剥离剂和/或蚀刻方法可以去除。
在图8中，除了其它示例之外，有机平坦化层(OPL)105通过CVD工艺沉积在材料95上。平坦化层(OPL)105还沉积在开口97内以及在材料90之上。硬掩模100(例如，光刻叠层)沉积在OPL 105上，其然后经受光刻工艺。特别地，光刻工艺是沟槽在先，过孔在后的方案。
在图9中，过孔99形成在OPL 105中，停止在两个不同的层级上的蚀刻停止层65处。使用采用硬掩模材料95的过孔99的图案化开口的第二蚀刻工艺，在绝缘体材料90中形成沟槽99'和99”。在实施例中，过孔99和沟槽99'、99”的图案化可以是双镶嵌(dual damascene)工艺，其还去除蚀刻停止层65的部分(形成开口)以暴露塞85和接触20两者。
在图10中，执行镀敷工艺以加衬和填充过孔和沟槽99、99'、99”。具体地，镀敷工艺包括阻挡层、金属种子层的沉积和电镀工艺。在镀敷工艺完成之后，金属110、115沉积在过孔和沟槽99、99'、99”的空的空间内。除了其它实施例之外，阻挡层的沉积可以使用等离子体增强化学气相沉积(PECVD)工艺来实现。在实施例中，阻挡层可以是氮化钛(TiN)或氮化钽(TaN)之一，尽管可以使用其它材料。金属110、115可以是铜(Cu)，作为一个示例，接触在不同的层级处的钨接触20、85(例如，在第一层级处的钨接触20和在第二、更高层级处的钨接触85)。然后，金属材料可以经受平坦化工艺(例如CMP)，因此形成在较高层级处的金属化层/布线层110以及在较低层级处的接触115，分别接触钨塞(即，跨接接触)85和接触20。也就是说，接触金属110、115位于两个不同的层级上，直接位于并接触在两个不同的接触85、20上。金属化层/布线层110和接触115可以是延伸到结构的更高层级的结构的双镶嵌结构。
如上所述的方法用于集成电路芯片的制造。所得到的集成电路芯片可以由制造商以原始晶片形式(也就是说，作为具有多个未封装芯片的单个晶片)作为裸芯片或以封装形式分发。在后一种情况下，芯片安装在单个芯片封装(诸如塑料载体，具有固定到母板或其它更高级别载体的引线)或多芯片封装(诸如具有单面或双面表面互连或掩埋互连的陶瓷载体)中。在任何情况下，芯片然后与其它芯片、分立电路元件和/或其它信号处理设备集成，作为(a)中间产品(诸如母板)或(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其它低端应用到具有显示器、键盘或其它输入设备以及中央处理器的高级计算机产品。
为了说明的目的，已经呈现了本公开的各种实施例的描述，但并不旨在穷举或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。选择在此所使用的术语是为了最好地解释实施例的原理、对市场中发现的技术的实际应用或技术改进，或使得本领域普通技术人员能够理解在此所公开的实施例。

Claims (20)

1.一种结构，包括：
第一接触，在所述结构的第一层级处；
跨接接触，在所述结构的第二、更高层级处；
蚀刻停止层，其具有在所述第一接触之上的开口，并且部分地包封所述跨接接触并具有暴露所述跨接接触的开口；以及
接触，其通过所述开口与所述第一层级处的所述第一接触和所述第二、更高层级处的所述跨接接触电接触。
2.根据权利要求1所述的结构，其中，所述跨接接触与在与所述第一接触相同层级处的第二接触电接触。
3.根据权利要求2所述的结构，其中，所述跨接接触是钨塞结构。
4.根据权利要求2所述的结构，其中，在所述结构的所述第一层级处，所述第一接触与栅极结构电接触以及所述第二接触与所述栅极结构的源极/漏极电接触。
5.根据权利要求4所述的结构，其中，所述源极/漏极区域是凸起的源极/漏极区域。
6.根据权利要求5所述的结构，其中，所述接触是延伸到所述结构的不同层级的铜。
7.根据权利要求1所述的结构，其中，所述第一接触和所述跨接接触是钨。
8.根据权利要求1所述的结构，其中，所述接触是延伸到所述结构的更高层级的双镶嵌结构。
9.根据权利要求1所述的结构，其中，所述接触是与所述跨接接触和所述第一接触不同的材料。
10.一种方法，包括：
在结构的第一层级处形成第一接触；
在所述结构的第二、更高层级处形成跨接接触；
形成具有所述第一接触之上的开口和所述跨接接触之上的开口的蚀刻停止层；以及
通过所述蚀刻停止层的所述开口形成与所述第一层级处的所述第一接触和所述第二、更高层级处的所述跨接接触电接触的接触。
11.根据权利要求10所述的方法，还包括在所述第一层级处形成第二接触，所述第一接触接触栅极结构以及所述第二接触接触凸起的源极/漏极区域。
12.根据权利要求11所述的方法，其中，所述跨接接触被形成为与所述第二接触电连接，并且所述第一接触、所述第二接触和所述跨接接触具有相同的材料。
13.根据权利要求11所述的方法，其中，所述接触由双镶嵌工艺形成，其填充有与所述跨接接触和所述第一接触直接接触的铜材料。
14.根据权利要求10所述的方法，其中，所述跨接接触被所述蚀刻停止层包封，并且所述跨接接触形成在所述第一层级之上的所述蚀刻停止层的另一开口中。
15.根据权利要求10所述的方法，还包括在所述蚀刻停止层之上形成层间电介质。
16.根据权利要求15所述的方法，还包括通过在所述蚀刻停止层上停止的湿氧化物蚀刻工艺来蚀刻所述层间电介质以允许所述跨接接触的包封和所述蚀刻停止层的加厚。
17.一种方法，包括：
在衬底上形成栅极结构；
在所述衬底上形成凸起的源极/漏极区域；
在第一层级处形成到所述栅极结构的第一接触；
在所述第一层级处形成到所述凸起的源极/漏极区域的第二接触；
在相对于所述第一层级的第二、更高层级处形成到所述第二接触区域的跨接接触；以及
形成位于所述第一层级处的所述第一接触上和所述第二、更高层级处的所述跨接接触上的双镶嵌铜布线结构。
18.根据权利要求17所述的方法，还包括用蚀刻停止层包封所述跨接接触。
19.根据权利要求17所述的方法，其中，所述双镶嵌铜布线结构的形成包括通过所述第一接触的顶表面上和所述跨接接触的停止表面上的所述蚀刻停止层进行蚀刻。
20.根据权利要求17所述的方法，其中，所述跨接接触、所述第一接触和所述第二接触包括钨材料。
CN201711017950.5A 2017-07-25 2017-10-26 位于不同接触区域层级上的接触方案 Active CN109300876B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/658570 2017-07-25
US15/658,570 US10157774B1 (en) 2017-07-25 2017-07-25 Contact scheme for landing on different contact area levels

Publications (2)

Publication Number Publication Date
CN109300876A true CN109300876A (zh) 2019-02-01
CN109300876B CN109300876B (zh) 2022-03-04

Family

ID=64604817

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711017950.5A Active CN109300876B (zh) 2017-07-25 2017-10-26 位于不同接触区域层级上的接触方案

Country Status (4)

Country Link
US (1) US10157774B1 (zh)
CN (1) CN109300876B (zh)
DE (1) DE102017219677B4 (zh)
TW (1) TWI646643B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10804140B2 (en) 2018-03-29 2020-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect formation and structure
US10978388B2 (en) * 2018-10-08 2021-04-13 International Business Machines Corporation Skip via for metal interconnects
US11244859B2 (en) * 2019-10-10 2022-02-08 International Business Machines Corporation Interconnects having a via-to-line spacer for preventing short circuit events between a conductive via and an adjacent line
US11114153B2 (en) * 2019-12-30 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. SRAM devices with reduced coupling capacitance
CN113130380B (zh) * 2019-12-30 2024-01-26 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US12002885B2 (en) * 2021-02-11 2024-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Gate contact and via structures in semiconductor devices
US11728272B2 (en) * 2021-03-31 2023-08-15 Taiwan Semiconductor Manufacturing Company Limited Plasma-damage-resistant interconnect structure and methods for manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012043868A (ja) * 2010-08-16 2012-03-01 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
CN103378033A (zh) * 2012-04-27 2013-10-30 台湾积体电路制造股份有限公司 衬底通孔及其形成方法
US20140199837A1 (en) * 2013-01-14 2014-07-17 United Microelectronics Corp. Method of forming semiconductor structure having contact plug
US20160190124A1 (en) * 2014-12-31 2016-06-30 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device structure and method for forming the same
CN106298733A (zh) * 2015-06-26 2017-01-04 台湾积体电路制造股份有限公司 具有导线上方的蚀刻停止层的互连结构
CN106972038A (zh) * 2016-01-14 2017-07-21 台湾积体电路制造股份有限公司 集成电路及形成电阻式随机存取存储器单元的方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5451543A (en) 1994-04-25 1995-09-19 Motorola, Inc. Straight sidewall profile contact opening to underlying interconnect and method for making the same
US6071784A (en) * 1997-08-29 2000-06-06 Advanced Micro Devices, Inc. Annealing of silicon oxynitride and silicon nitride films to eliminate high temperature charge loss
US7042095B2 (en) * 2002-03-29 2006-05-09 Renesas Technology Corp. Semiconductor device including an interconnect having copper as a main component
US6746914B2 (en) * 2002-05-07 2004-06-08 Chartered Semiconductor Manufacturing Ltd. Metal sandwich structure for MIM capacitor onto dual damascene
DE10324433B4 (de) * 2003-05-28 2007-02-08 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Substratkontakts für ein SOI-Halbleiterbauteil
US8042095B2 (en) 2004-08-13 2011-10-18 National Instruments Corporation Application development environment with features for increasing the ease and efficiency of viewing function help text
KR100755365B1 (ko) * 2005-02-15 2007-09-04 삼성전자주식회사 엠. 아이. 엠 커패시터들 및 그 형성방법들
KR100629270B1 (ko) * 2005-02-23 2006-09-29 삼성전자주식회사 낸드형 플래시 메모리 소자 및 그 제조방법
JP2010205908A (ja) * 2009-03-03 2010-09-16 Toshiba Corp 半導体装置およびその製造方法
KR101908358B1 (ko) * 2011-05-24 2018-12-11 삼성전자주식회사 금속 플러그를 갖는 반도체 소자 및 그 형성 방법
JP2013165224A (ja) * 2012-02-13 2013-08-22 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法
US9129876B2 (en) * 2013-05-28 2015-09-08 United Microelectronics Corp. Image sensor and process thereof
US9431296B2 (en) * 2014-06-26 2016-08-30 International Business Machines Corporation Structure and method to form liner silicide with improved contact resistance and reliablity
US20160336183A1 (en) 2015-05-14 2016-11-17 Globalfoundries Inc. Methods, apparatus and system for fabricating finfet devices using continuous active area design
US9780199B2 (en) * 2015-09-23 2017-10-03 United Microelectronics Corp. Method for forming semiconductor device
US10032828B2 (en) 2016-07-01 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor memory device and method for fabricating the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012043868A (ja) * 2010-08-16 2012-03-01 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
CN103378033A (zh) * 2012-04-27 2013-10-30 台湾积体电路制造股份有限公司 衬底通孔及其形成方法
US20140199837A1 (en) * 2013-01-14 2014-07-17 United Microelectronics Corp. Method of forming semiconductor structure having contact plug
US20160190124A1 (en) * 2014-12-31 2016-06-30 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device structure and method for forming the same
CN106298733A (zh) * 2015-06-26 2017-01-04 台湾积体电路制造股份有限公司 具有导线上方的蚀刻停止层的互连结构
CN106972038A (zh) * 2016-01-14 2017-07-21 台湾积体电路制造股份有限公司 集成电路及形成电阻式随机存取存储器单元的方法

Also Published As

Publication number Publication date
CN109300876B (zh) 2022-03-04
US10157774B1 (en) 2018-12-18
TW201909362A (zh) 2019-03-01
DE102017219677B4 (de) 2021-03-11
TWI646643B (zh) 2019-01-01
DE102017219677A1 (de) 2019-01-31

Similar Documents

Publication Publication Date Title
CN109300876A (zh) 位于不同接触区域层级上的接触方案
US7626257B2 (en) Semiconductor devices and methods of manufacture thereof
US20220208749A1 (en) Semiconductor devices and methods of manufacture thereof
US6943067B2 (en) Three-dimensional integrated semiconductor devices
US9385216B2 (en) Monolithically integrated active snubber
US9589983B2 (en) Efficient buried oxide layer interconnect scheme
US8796852B2 (en) 3D integrated circuit structure and method for manufacturing the same
CN103633042B (zh) 半导体器件封装件及其封装方法
US9953857B2 (en) Semiconductor device with buried local interconnects
KR20160141687A (ko) 다마신 구조물의 구조물 및 형성방법
TWI671852B (zh) 用於共用基板的電路的隔離結構
CN106409812A (zh) 半导体器件结构及其形成方法
CN108511386B (zh) 分段式防护环及芯片边缘密封件
TW201919247A (zh) 半導體裝置結構
CN108183087B (zh) 用于形成应力降低装置的方法
KR20170010710A (ko) 반도체 디바이스 및 그 제조 방법
US10096689B2 (en) Low end parasitic capacitance FinFET
US11114338B2 (en) Fully aligned via in ground rule region
US10833149B2 (en) Capacitors
US20230170253A1 (en) Dual-damascene fav interconnects with dielectric plug
CN102637656A (zh) 穿硅通孔结构及其形成方法
US20230187510A1 (en) Angled via for tip to tip margin improvement

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20201207

Address after: California, USA

Applicant after: Lattice core USA Inc

Address before: Grand Cayman Islands

Applicant before: GF

GR01 Patent grant
GR01 Patent grant