CN103633042B - 半导体器件封装件及其封装方法 - Google Patents

半导体器件封装件及其封装方法 Download PDF

Info

Publication number
CN103633042B
CN103633042B CN201310368204.6A CN201310368204A CN103633042B CN 103633042 B CN103633042 B CN 103633042B CN 201310368204 A CN201310368204 A CN 201310368204A CN 103633042 B CN103633042 B CN 103633042B
Authority
CN
China
Prior art keywords
chip
semiconductor
opening
semiconductor chip
device region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201310368204.6A
Other languages
English (en)
Other versions
CN103633042A (zh
Inventor
迪特里希·博纳特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN103633042A publication Critical patent/CN103633042A/zh
Application granted granted Critical
Publication of CN103633042B publication Critical patent/CN103633042B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5221—Crossover interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29157—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32501—Material at the bonding interface
    • H01L2224/32502—Material at the bonding interface comprising an eutectic alloy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32505—Material outside the bonding interface, e.g. in the bulk of the layer connector
    • H01L2224/32506—Material outside the bonding interface, e.g. in the bulk of the layer connector comprising an eutectic alloy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82053—Bonding environment
    • H01L2224/82095—Temperature settings
    • H01L2224/82096—Transient conditions
    • H01L2224/82097—Heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8382—Diffusion bonding
    • H01L2224/8383—Solid-solid interdiffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开了一种半导体器件封装件及其封装方法。在本发明的一种实施方式中，形成半导体器件的方法包括在半导体基板的第一区中形成器件区，以及在半导体基板的第二区中形成开口。所述方法还包括将半导体芯片放置在开口内以及在半导体芯片和器件区之上形成第一金属化层。

Description

半导体器件封装件及其封装方法
技术领域
本发明通常涉及封装，更具体地，涉及一种半导体器件封装件及其封装方法。
背景技术
半导体器件被用于很多电子应用及其他的应用中。半导体器件包括集成电路或者分立器件，这些集成电路或分立器件通过将许多类型的薄膜材料沉积在半导体晶片上并图案化该薄膜材料而形成于半导体晶片上。
在半导体器件技术中，需要将许多不同的功能整合到单个芯片上，例如，在同一芯片的模拟和数字电路、功率器件和逻辑器件或其他器件上制备。在这类应用中，很多不同的元件被集成在单个芯片上。然而，这类集成带来了其他需要克服的挑战。可替换地，可在独立芯片中形成不同类型的电路并将其封装在一起。然而，多芯片封装有很多使半导体器件性能下降的影响。
发明内容
根据本发明的一种实施方式，一种形成半导体器件的方法包括在半导体基板内形成开口；在所述开口处将半导体芯片附接至所述半导体基板；以及单一化所述半导体基板。
根据本发明的另一实施方式，一种形成半导体器件的方法包括在半导体基板的第一区中形成器件区；以及在所述半导体基板的第二区中形成开口。所述方法还包括将半导体芯片放置在所述开口内；以及在所述半导体芯片和所述器件区上形成第一金属化层。
根据本发明另一实施方式，一种半导体器件包括器件区，被设置在半导体基板内；开口，在所述半导体基板内并靠近所述器件区；以及半导体芯片，被设置在所述开口中。所述半导体芯片在所述开口处被附接至所述半导体基板。
附图说明
为更全面地理解本发明及其优势，现结合附图参考以下描述，其中：
图1（包括图1A和图1B）示出了根据本发明一种实施方式的半导体器件，其中，图1A示出了顶视图，以及图1B示出了截面视图；
图2（包括图2A和图2B）示出了根据本发明实施方式的半导体器件，其中，图2A示出了顶视图，以及图2B示出了截面视图；
图3示出了根据本发明一种实施方式的半导体器件；
图4（包括图4A和图4B）示出了根据本发明实施方式的在形成器件区后的半导体器件，其中，图4A示出了截面视图，以及图4B示出了顶视图；
图5示出了根据本发明实施方式的在形成芯片开口后的半导体器件；
图6（包括图6A至图6C）示出了根据本发明实施方式的集成电路芯片的形成；
图7示出了根据本发明实施方式的将半导体芯片放置在第一基板的芯片开口内时的半导体器件；
图8示出了根据本发明实施方式的在将半导体芯片附接至第一基板后的半导体器件；
图9示出了根据本发明一种实施方式的用电介质材料填充基板与半导体芯片之间的空间后的半导体器件；
图10（包括图10A和图10B）示出了根据本发明一种实施方式的形成外接触片后的半导体器件；
图11示出了根据本发明的可替换实施方式的将之前在另一基板上形成的半导体芯片附接至第一基板后的半导体器件；
图12示出了根据本发明的可替换实施方式的用电介质材料填充半导体芯片与第一基板间的空隙或者空间后的半导体器件；以及
图13示出了根据本发明的可替换实施方式的在第一基板和半导体芯片上形成金属化层之后的半导体器件。
除非另有说明，否则不同图中的相应数字和符号通常指的是相对应的部分。绘制附图是为了清楚地示出实施方式的相关方面，且不一定按比例绘制。
具体实施方式
下面将详细讨论各种实施方式的制作与使用。然而，应理解，本发明提供了很多可适用的创造性概念，这些创造性概念在很多具体背景中均能够被体现出来。所讨论的具体实施方式仅是对制作和使用本发明的具体方式的说明，且并不限定本发明的范围。
许多应用都需要集成大量不同的电路。例如，功率芯片常常与功率模块中的逻辑芯片结合。然而，这些不同电路中的很多电路可能需要使用不可兼容的工艺。另外，它们可能需要会导致生产成本大幅增加的复杂的集成。因此，在这类情况下，多个芯片可被分别制作并封装在一起。这类封装增加了封装成本，并且也增加了寄生效应，且减少了热电机械稳定性，所有这些会导致结合的封装件的性能下降。通过描述一种将具有独立制作工艺的优势相结合而不增加多芯片封装的成本和性能下降的工艺，本发明的实施方式克服了这些问题。
将用图1描述本发明的结构实施方式。将使用图2至图3来描述其他结构实施方式。将用图4至图10描述一种制作半导体器件的方法。将用图11至图13描述制作半导体器件的其他实施方式。
图1（包括图1A至图1B）示出了根据本发明实施方式的半导体器件。图1A示出了顶视图，以及图1B示出了截面图。
参照图1A，半导体器件包括第一电路1、第二电路2以及第三电路3。第二电路2布置在第一电路1与第三电路3之间。在各种实施方式中，第一电路1和第二电路2可包括电源电路。在一种实施方式中，第一电路1可以是分立的半导体器件，第三电路3可以是分立的半导体器件，而第二电路2可包括集成电路。在一种实施方式中，第一电路1和第三电路3可将电力提供给第二电路2。
在各种实施方式中，第二电路2不同于第一电路1和第三电路3。在一种实施方式中，第二电路2包括一种不同于第一电路1和第三电路3的半导体材料。例如，第二电路2可包括在锗、碳化硅、诸如氮化镓、砷化镓的III-V、II-IV族化合物上形成的器件，而第一电路1和第三电路3可包括在硅上形成的器件。在另一实施方式中，第二电路2包括与第一电路1和第三电路3不同的金属化方案。例如，第一电路1和第三电路3可包括两个金属层，而第二电路2可包括多于四个的金属层，例如，十个金属层。
第一电路1和第三电路3通过隔离区30隔离，而第二电路2可通过芯片隔离区40隔离。在一种实施方式中，隔离区30可环绕第一电路1和第三电路3，而芯片隔离区40可环绕第二电路2。
参照图1B，在一种实施方式中，隔离区30可被布置在第一电路1和第三电路3周围以作为浅沟槽隔离。所述芯片隔离区40可被布置在第二电路2的周围，例如作为深沟槽隔离结构。第二电路2可通过导电性粘结层50被耦接至基板10。在一种或多种实施方式中，导电性粘结层50包括铝和硅。在一种或多种实施方式中，导电性粘结层50包括硅化物。在一种或多种实施方式中，导电性粘结层50包括钨、钛、钽、钴以及其他。在一种实施方式中，导电性粘结层50包括共晶材料。例如，在一种实施方式中，导电性粘结层50包括共晶体，该共晶体包括铝和硅。在一种实施方式中，所述隔离区30可被布置在第一电路1和第三电路3周围作为浅沟槽隔离。
图2（包括图2A至图2B）示出了根据本发明实施方式的半导体器件。图2A示出了顶视图，以及图2B示出了截面视图。
与前述实施方式中的实施方式有所不同，在该实施方式中，第一电路1围绕或环绕第二电路2，使得隔离区30围绕第一电路1和第一电路2。正如前述实施方式，芯片隔离区40围绕第二电路2。
图3示出了根据本发明实施方式的半导体器件。
与前述实施方式有所不同，第二电路2形成于第一电路1的一侧，使得第二电路2被第一电路1从两侧环绕。因此，在该实施方式中，第一电路1被形成为“L”形区域。在一种实施方式中，沿着第二电路2的一侧，可形成与隔离区30相邻或接触的芯片隔离区40。
图4至图10示出了根据本发明实施方式形成半导体器件的一种实施方式。
图4（包括图4A和图4B）示出了根据本发明实施方式的在形成器件区后的半导体器件，其中，图4A示出了截面视图，以及其中，图4B示出了顶视图。
图4A示出了带有第一区11、第二区12以及第三区13的第一基板10。第二区12被布置于第一区11与第三区13之间。例如，第一基板10可包括具有（100）表面的体硅基板。在各种实施方式中，第一基板10可包括绝缘体上半导体（SOI）材料，诸如氧化物上硅。在一种或多种实施方式中，第一基板10可包括其他半导体材料，诸如SiGe、SiC、石墨烯，包括诸如GaN、GaAs、GaP、GaSb、InP、InSb、SbAs的化合物半导体以及其组合物的。在一种或多种实施方式中，基板10可采用n型或p型掺杂剂来掺杂以减小电阻，并可包括外延层。
在各种实施方式中，隔离区30可被形成于基板10中。例如，诸如氮化硅的硬掩膜层（这里未示出）可被形成于第一基板10之上并被图案化以暴露出隔离区。第一基板10的暴露部分随后可被蚀刻至合适的深度，例如在约200nm到约500nm之间。随后，所述沟槽用绝缘材料填充。例如，可热氧化暴露的硅表面以形成薄氧化层。所述沟槽随后可内衬（line）有第一材料（诸如氮化层（例如，Si3N4））。所述沟槽随后可用第二材料（诸如氧化物）填充。例如，可进行高密度等离子体（HDP），其中，所产生的填充材料被称为HDP氧化物。在其他实施方式中，可使用其他的沟槽填充工艺。例如，当沟槽典型被内衬时，该步骤可免去用其他填充材料（我的理解：可采用其他填充材料免去该步骤）。隔离区30的深度可根据被隔离的器件类型而不同，例如，高电压器件可使用比低电压器件更深的隔离。
器件区20可形成于隔离区30之间。器件区20的形成可包括几种工艺，诸如掩膜掩蔽、注入、退火以及其他工艺。有源区25可形成于器件区20内。此外，可形成源区、漏区以及其他晶体管区。
在隔离区30间形成器件区20后，几个金属化层可形成于第一基板10之上。因此，第一区11和第三区13也可包括几个金属化层。例如，有源区25内的半导体器件可通过金属化层互相连接。此外，金属化提供了与有源区25的接触。如图所示，第一金属化层包括可形成于基板10之上的基板接触垫70。在后续工艺期间，可通过覆盖层60保护金属化层。
在各种实施方式中，第一区11可形成第一电路1，第二区12可形成第二电路2，以及第三区13可形成第三电路3（例如，图1A）。在一种或多种实施方式中，第一区11和第三区13可形成功率芯片的一部分。第一区11和第三区13可包括器件区20，该器件区20可包括各种半导体器件，诸如二极管、场效应晶体管、双极型晶体管、晶闸管以及其他器件。该器件区20可包括用于形成这些器件的有源区25。该器件区20可包括在形成半导体器件时的各种掺杂层35。在一种或多种实施方式中，第二区12可不具有器件区。
参照图4B，在一种或多种实施方式中，第一基板10可以是诸如硅晶片的晶片。图4B在一种实施方式中也示出了第一区11、第二区12以及第三区13。
图5示出了根据本发明实施方式的在形成芯片开口后的半导体器件。
如图5所示，在形成第一金属化层后，在第一基板10中形成芯片开口110。第一区11和第三区13可掩盖有硬掩膜层120。继光刻胶层之后，硬掩膜层120可沉积于基板10之上。可通过图案化光刻胶层来图案化硬掩膜层120。在保护第一区11和第三区13时，被图案化的硬掩膜层120暴露出第二区12。可执行沟槽蚀刻工艺以形成芯片开口110。
在后续的沟槽蚀刻工艺期间，硬掩膜层120保护覆盖层60和其下面的器件区20。硬掩膜层120的材料可基于蚀刻工艺的蚀刻化学剂的选择性来选择。例如，在一种实施方式中，带有氟化学剂的高密度等离子体可随后被用来蚀刻芯片开口110，且硬掩膜层120包括SiO2硬掩膜。在各种实施方式中，硬掩膜层120可包括无机电介质层，诸如氧化硅层。可替换地，硬掩膜层120包括氮化硅。在可替换实施方式中，硬掩膜层120可包括酰亚胺层。
在各种实施方式中，硬掩膜层120的厚度可约为100nm至500nm。在一种或多种实施方式中，硬掩膜层120的厚度可约为100nm至300nm。在一种或多种实施方式中，硬掩膜层120的厚度可约为100nm至2000nm。在各种实施方式中，使用沉积技术或涂覆可形成硬掩膜层120。硬掩膜层120的形成可包括烘焙工艺。
可使用蚀刻工艺在基板10中形成芯片开口110。在一种或多种实施方式中，可使用各向异性蚀刻，诸如反应离子蚀刻工艺。
在各种实施方式中，芯片开口110的深度DDO可约为20μm至约100μm。在一种或多种实施方式中，芯片开口110的深度DDO可约为20μm至约200μm。在一种或多种实施方式中，芯片开口110的深度DDO可约为20μm至约80μm。在各种实施方式中，芯片开口110的深度DDO可约为10μm至约40μm。在各种实施方式中，芯片开口110的深度DDO可约为30μm至约50μm。
图6（包括图6A至图6C）示出了根据本发明实施方式的集成电路芯片的形成。
参照图6A，多个半导体芯片100形成于第二基板51内。在一种或多种实施方式中，第二基板51可包括硅晶片。例如，第二基板51可包括具有（100）表面的体硅基板。在各种实施方式中，第二基板51可包括绝缘体上半导体（SOI）材料，诸如氧化物上硅。在一种或多种实施方式中，第二基板51可包括其他半导体材料，诸如SiGe、SiC、石墨烯，包括诸如GaN、GaAs、GaP、GaSb、InP、InSb、SbAs的化合物半导体及其组合物。在一种或多种实施方式中，第二基板51可掺杂有n型或p型掺杂剂以减小电阻，且可包括外延层。
有源区可接近第二基板51的顶面被形成。在各种实施方式中，有源区可包括二极管、晶体管、晶闸管以及其他器件。在一种或多种实施方式中，第二基板51也可包括无源器件，诸如电容器、电感器、电阻器。
在一种或多种实施方式中，多个半导体芯片100可以是带有多个金属化层的高度集成芯片。在各种实施方式中，所述多个半导体芯片100中的每一个可包括逻辑芯片、存储芯片、模拟芯片、混合信号芯片以及其他类型的电路。所述多个半导体芯片100的有源电路可包括有源器件区，且可包括用于形成集成电路的必要的晶体管、电阻器、电容器、电感器以及其他元件。例如，包括晶体管的有源区（例如，CMOS晶体管）可通过隔离区（例如，浅沟槽隔离）而彼此分开。
接下来，金属化层形成于有源器件区之上以电接触并互相连接有源器件。金属化层和有源器件区一起形成完整的功能性集成电路。换句话说，所述多个半导体芯片100中的每一个的电气功能可通过互相连接的有源电路执行。在逻辑器件中，金属化层可包括很多层，例如，九层或更多层的铜或另外的其他金属。在存储器件（诸如DRAM）中，金属层的数量可较少，且可以是铝。在一种或多种实施方式中，多个半导体芯片100可包括至少四个金属层。如图6B的放大横截面视图所示，多个半导体芯片100可包括至少10个金属层。
图6B示出了显示形成在第二基板51上的多个金属层（M1-M10）和多个通孔层（V1-V10）的放大视图。在图6B中，十层金属层被垂直堆叠，并包括金属线层M1、M2、M3、M4、M5、M6、M7、M8、M9和M10，这些金属线层通过通孔层V1、V2、V3、V4、V5、V6、V7、V8、V9和V10连接。在其他实施方式中，可使用数量或多或少的金属和通孔层。在本发明的各种实施方式中，可使用单镶嵌工艺或双镶嵌工艺形成金属层和通孔层。在单镶嵌工艺中，绝缘材料的单层被图案化有导电性特征的图案，诸如导电线、导电通孔。相反，在双镶嵌工艺中，通孔和金属线被图案化为导电特征并在单填充步骤中用导电材料进行填充。
第二基板51的金属化层可包括用于与外电路接触的最顶层金属层。例如，最顶层金属层可包括芯片接触垫65。
如接下来在图6C中所示，单一化第二基板51以形成多个半导体芯片100。虚线示出了划槽或划线，通过该划槽或划线执行划分。在各种实施方式中，在单一化之前，第二基板51可从后侧（与有源区25相对的一侧）变薄。在一种或多种实施方式中，可通过后侧磨削工艺进行变薄。在变薄之后，后侧导体140可沉淀于第二基板51的暴露的后表面上。在一种实施方式中，后侧导体140可包括铝。
在各种实施方式中，在多个半导体芯片100上的金属化层不同于第一基板10上的金属化层。在一种或多种实施方式中，在多个半导体芯片100上的金属化层的数量大于在第一基板10上的金属化层的数量。
图7示出了根据本发明实施方式的在将半导体芯片排列至第一基板的芯片开口内后的半导体器件。
参照图7，所述多个半导体芯片100被放置在第一基板10的芯片开口120之内。在各种实施方式中，所述多个半导体芯片100中的每一个可分别被排列并放置在芯片开口110之内。在各种实施方式中，可使用多个半导体芯片100的横向排列或纵向排列的合适技术。
在各种实施方式中，芯片开口的宽度WDO比半导体芯片的宽度WD至少大10%。在各种实施方式中，芯片开口的宽度WDO比半导体芯片的宽度WD至少大5%。在各种实施方式中，芯片开口的宽度WDO比半导体芯片的宽度WD至少大20%。在各种实施方式中，芯片开口的宽度WDO比半导体芯片的宽度WD大出约5%至20%。此外，芯片开口110的深度DDO与半导体芯片100的厚度TD几乎相同。在各种实施方式中，芯片开口110的深度DDO是半导体芯片100的厚度TD的0.9至约1.1倍。在各种实施方式中，芯片开口110的深度DDO是半导体芯片100的厚度TD的0.95至约1.05倍。
图8示出了根据本发明实施方式的在将半导体芯片附接至第一基板上之后的半导体器件。
例如，接下来参照图8，使用热工艺将多个半导体芯片100附接至第一基板10。在一种或多种实施方式中，在较高温度下多个半导体芯片100被放置在芯片开口110之内。可替换地，可在将所有多个半导体芯片放置在第一基板10的所有芯片开口120之内后执行热处理。热处理可导致多个半导体芯片100与第一基板10之间形成粘结。在一种实施方式中，后侧导体140的原子可与第一基板10的原子混合和/或反应以形成机械稳定粘结。因而，形成导电性粘结层50。
在多个半导体芯片100与第一基板10之间的粘结后，形成具有临界尺寸约为DS的开口45。在各种实施方式中，开口45的临界尺寸DS约为2μm至约10μm。在一种或多种实施方式中，开口45的临界尺寸DS约为4μm至约6μm。
图9示出了根据本发明一种实施方式的在用电介质材料将第一基板与半导体芯片间的空间填充之后的半导体器件。
参照图9，在第一基板10上形成电介质材料210。在一种或多种实施方式中，电介质材料210填充开口45。在一种或多种实施方式中，电介质材料210可使用高的宽高比填充工艺来沉积以填充高宽高比开口45。在一种或多种实施方式中，可使用高密度等离子体化学气相沉积（HDP CVD）工艺来沉积电介质材料210。可替换地，可使用其他工艺（诸如旋涂、化学气相沉积、等离子体气相沉积和其他沉积工艺）来沉积电介质材料210。使用化学和/或机械抛光工艺可平面化电介质材料210。可替换地，例如，使用涂覆工艺可使电介质材料210形成为平面表面。
第一基板10现包括半导体芯片100，该半导体芯片100可与嵌入式晶圆级工艺相似地与第一基板10的其他电路一起被处理。然而，不同于嵌入式晶圆级工艺，第一基板10包括在热膨胀系数上没有差异的均质材料。例如，在传统的嵌入式晶圆级工艺中，芯片被嵌入在塑封材料内。然而，芯片的热膨胀系数与塑料材料的不同，这在处理和/或操作期间可能产生应力相关系数。
图10（包括图10A和图10B）示出了根据本发明一种实施方式的在形成外接触垫后的半导体器件。图10A示出了截面视图，而图10B示出了顶视图。
参照图10，其他的金属层可形成于电介质材料210之上和/或之内。例如，在一种实施方式中，至少一通孔层可形成于电介质材料210之内。可替换地，其他的金属层可形成于在电介质材料210之上形成的层间电介质上。
如图所示，芯片接触通孔310可被用于将芯片接触垫350与半导体芯片100的芯片接触垫65耦接。基板接触通孔320可被用于将芯片接触垫350与基板接触垫70耦接。
可单一化第一基板10以形成一种包括来自第一区11、第二区12以及第三区13的电路的芯片。第二区12包括半导体芯片100。在单一化之前，第一基板10可选地可从后侧变薄。
图11至图13示出了根据本发明可替换实施方式的在制作的不同阶段期间的半导体器件。
不同于先前的实施方式，该实施方式示出了当半导体芯片厚度与芯片开口的深度不匹配时的情况。
这种工艺始于如在图4至图7中所描述。图11示出了根据本发明可替换实施方式的在将之前在另一基板上形成的半导体芯片100附接至第一基板10后的半导体器件。在一种实施方式中，参照图11，多个半导体芯片100比芯片开口110的深度薄。
图12示出了根据本发明可替换实施方式的在用电介质材料210填充半导体芯片100与第一基板10间的空隙或者空间后的半导体器件。正如先前的实施方式，在将多个半导体芯片100附接至第一基板10后，电介质材料210形成于第一基板10之上并如图12中所示来平面化。
图13示出了根据本发明可替换实施方式的在所述第一基板和半导体芯片上形成金属化层之后的半导体器件。多个接触形成在第一基板10之上。可形成基板接触通孔320以耦接至基板接触垫70。此外，可形成芯片接触通孔310以耦接至芯片接触垫65。芯片接触通孔310的长度不同于基板接触通孔320。在各种实施方式中，在镶嵌工艺中可同时形成芯片接触通孔310和基板接触通孔320。可替换地，在一些实施方式中，可连续形成芯片接触通孔310和基板接触通孔320。因而，即便芯片厚度由于工艺变化和/或设计原因有所不同，也可使用本发明的实施方式。
如各种实施方式中所描述，例如，包括金属的材料可以是纯金属、金属合金、金属化合物、金属间化合物以及其他，即，任何包含金属原子的材料。例如，铜可以是纯铜或包含铜的任何材料，诸如但不限于，铜合金、铜化合物、铜金属间化合物、包含铜的绝缘体以及包含铜的半导体。
尽管已参照所示实施方式来描述本发明，但本说明书并不旨在以限定的意义来解释。参照本说明书，对于本领域技术人员而言，示例性实施方式的各种修改和组合以及本发明的其他实施方式将是显而易见的。如图所示，在各种实施方式中，图1至图13中所描述的实施方式可彼此结合。因此，所附权利要求旨在涵盖任何这些修改或实施方式。
尽管已详细描述了本发明及其优势，但应理解，在不偏离所附权利要求所限定的本发明的精神和范围的情况下，可对本发明做出各种变化、替代以及变更。例如，本领域技术人员将很容易理解，在保持在本发明的范围内的情况下，本文所描述的很多特征、功能、工艺以及材料可以不同。
此外，本申请的范围并不意指被限制于在说明书描述的工艺、机器、制造、物质组成、手段、方法以及步骤的特定实施方式。如本领域普通技术人员根据本发明公开将很容易理解，可根据本发明来利用执行大致与本文所描述的对应实施方式相同的功能或者实现大致与之相同的效果的现有或待后续开发的工艺、机器、制造、物质组成、手段、方法、或者步骤。因此，所附权利要求旨在将这样的工艺、机器、制造、物质组成、手段、方法、或者步骤包括在其范围内。

Claims (21)

1.一种形成半导体器件的方法，所述方法包括：
在半导体基板内形成器件区；
在所述半导体基板内形成围绕所述器件区的浅沟槽隔离区；
在所述半导体基板内形成开口；
在所述开口处将半导体芯片附接至所述半导体基板；
形成内衬所述开口的侧壁并且围绕所述半导体芯片的芯片隔离区，所述芯片隔离区比所述浅沟槽隔离区更深；以及
单一化所述半导体基板。
2.根据权利要求1所述的方法，还包括在形成所述开口前，在所述半导体基板上形成金属化层。
3.根据权利要求1所述的方法，还包括在附接所述半导体芯片后，形成金属化层。
4.根据权利要求1所述的方法，其中，所述半导体基板包括硅晶片。
5.根据权利要求1所述的方法，其中，附接所述半导体芯片包括将所述半导体芯片背面上的导体附接至在所述开口内的所述半导体基板的表面上。
6.一种形成半导体器件的方法，所述方法包括：
在半导体基板的第一区中形成器件区；
在所述第一区周围的所述半导体基板内形成浅沟槽隔离区，所述浅沟槽隔离区围绕所述器件区；
在所述半导体基板的第二区中形成开口；
将半导体芯片放置在所述开口内；
形成内衬所述开口的侧壁并且围绕所述半导体芯片的芯片隔离区，所述芯片隔离区比所述浅沟槽隔离区更深；以及
在所述半导体芯片和所述器件区上形成第一金属化层。
7.根据权利要求6所述的方法，还包括在形成所述开口之前，在所述第一金属化层下形成第二金属化层。
8.根据权利要求7所述的方法，其中，所述第二金属化层与所述器件区形成接触。
9.根据权利要求6所述的方法，其中，所述器件区被设置在所述开口的一侧。
10.根据权利要求6所述的方法，其中，所述器件区环绕所述开口。
11.根据权利要求6所述的方法，其中，所述器件区包括用于功率芯片的电路。
12.根据权利要求6所述的方法，其中，所述半导体芯片包括集成电路。
13.根据权利要求6所述的方法，还包括：
在第一晶片内形成所述半导体芯片；以及
对所述第一晶片进行划片，其中，所述半导体基板是不同于所述第一晶片的第二晶片。
14.根据权利要求6所述的方法，还包括在放置所述半导体芯片后，对所述半导体基板进行划片。
15.根据权利要求6所述的方法，其中，所述半导体芯片被放置在所述开口内，使得所述半导体芯片的上表面基本上与所述半导体基板的上表面共面。
16.根据权利要求6所述的方法，还包括用绝缘材料填充所述半导体芯片与所述开口的侧壁之间的间隙。
17.一种半导体器件，包括：
器件区，被设置在半导体基板内；
浅沟槽隔离区，被设置在所述半导体基板内并且围绕所述器件区；
开口，在所述半导体基板内并靠近所述器件区；
半导体芯片，被设置在所述开口中，所述半导体芯片在所述开口处被附接至所述半导体基板；以及
芯片隔离区，内衬所述开口的侧壁并且被设置在所述半导体芯片的周围，所述芯片隔离区比所述浅沟槽隔离区更深。
18.根据权利要求17所述的器件，还包括：
金属化层，将所述器件区耦接至第一外电位节点并将所述半导体芯片耦接至第二外电位节点。
19.根据权利要求18所述的器件，其中，所述金属化层将所述器件区与所述半导体芯片耦接。
20.根据权利要求17所述的器件，还包括被设置在所述半导体芯片与所述器件区之间的芯片隔离区。
21.根据权利要求17所述的器件，还包括被设置在所述半导体芯片周围的芯片隔离区。
CN201310368204.6A 2012-08-21 2013-08-21 半导体器件封装件及其封装方法 Expired - Fee Related CN103633042B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/590,999 2012-08-21
US13/590,999 US8846452B2 (en) 2012-08-21 2012-08-21 Semiconductor device package and methods of packaging thereof

Publications (2)

Publication Number Publication Date
CN103633042A CN103633042A (zh) 2014-03-12
CN103633042B true CN103633042B (zh) 2017-05-17

Family

ID=50148335

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310368204.6A Expired - Fee Related CN103633042B (zh) 2012-08-21 2013-08-21 半导体器件封装件及其封装方法

Country Status (3)

Country Link
US (2) US8846452B2 (zh)
CN (1) CN103633042B (zh)
DE (1) DE102013108987B4 (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3003962B1 (fr) * 2013-03-29 2016-07-22 St Microelectronics Rousset Procede d'elaboration d'un masque de photolitographie destine a la formation de contacts, masque et circuit integre correspondants
KR20150070810A (ko) * 2013-12-17 2015-06-25 삼성전기주식회사 캐패시터 내장 기판 및 그 제조 방법
KR101665794B1 (ko) * 2014-12-22 2016-10-13 현대오트론 주식회사 다이 기반의 차량 제어기 전용 반도체 설계 방법 및 이에 의해 제조되는 차량 제어기 전용 반도체
US9806030B2 (en) * 2015-10-28 2017-10-31 Indiana Integrated Circuits, LLC Prototyping of electronic circuits with edge interconnects
CN108292651B (zh) * 2015-12-22 2022-08-23 英特尔公司 利用集成在管芯间结构上的化合物半导体器件设计的微电子器件
US9812568B2 (en) * 2016-02-04 2017-11-07 Board Of Regents, The University Of Texas System Ionic barristor
US10529641B2 (en) 2016-11-26 2020-01-07 Texas Instruments Incorporated Integrated circuit nanoparticle thermal routing structure over interconnect region
US11676880B2 (en) 2016-11-26 2023-06-13 Texas Instruments Incorporated High thermal conductivity vias by additive processing
US10861763B2 (en) 2016-11-26 2020-12-08 Texas Instruments Incorporated Thermal routing trench by additive processing
US11004680B2 (en) 2016-11-26 2021-05-11 Texas Instruments Incorporated Semiconductor device package thermal conduit
US10811334B2 (en) 2016-11-26 2020-10-20 Texas Instruments Incorporated Integrated circuit nanoparticle thermal routing structure in interconnect region
US10256188B2 (en) 2016-11-26 2019-04-09 Texas Instruments Incorporated Interconnect via with grown graphitic material
CN110770918B (zh) * 2017-04-19 2023-03-10 麦克姆技术解决方案控股有限公司 用于hast改进的器件隔离设计规则
CN109786368A (zh) * 2019-01-24 2019-05-21 中国科学院微电子研究所 一种光电芯片协同封装结构及方法
CN111048503A (zh) * 2019-12-27 2020-04-21 华天科技（昆山）电子有限公司 一种内埋芯片的扇出型封装方法以及封装结构
US11342218B1 (en) * 2020-11-02 2022-05-24 Micron Technology, Inc. Single crystalline silicon stack formation and bonding to a CMOS wafer

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH031580A (ja) 1989-05-29 1991-01-08 Shimadzu Corp 一次元放射線検出器アレイ
JPH0352273A (ja) 1989-07-19 1991-03-06 Shimadzu Corp 放射線検出素子アレイの実装構造
DE4238137A1 (de) 1992-11-12 1994-05-19 Ant Nachrichtentech Verfahren zur Herstellung von Vorrichtungen mit Bauelementen
US6864570B2 (en) * 1993-12-17 2005-03-08 The Regents Of The University Of California Method and apparatus for fabricating self-assembling microstructures
DE19720300B4 (de) 1996-06-03 2006-05-04 CiS Institut für Mikrosensorik gGmbH Elektronisches Hybrid-Bauelement und Verfahren zu seiner Herstellung
KR100890475B1 (ko) * 1999-09-02 2009-03-26 이비덴 가부시키가이샤 프린트배선판 및 그 제조방법
EP1321980A4 (en) * 2000-09-25 2007-04-04 Ibiden Co Ltd SEMICONDUCTOR ELEMENT, METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT, MULTILAYER PRINTED CIRCUIT BOARD, AND METHOD FOR MANUFACTURING MULTILAYER PRINTED CIRCUIT BOARD
FR2817399B1 (fr) * 2000-11-30 2003-10-31 St Microelectronics Sa Puce electronique multifonctions
US6972964B2 (en) * 2002-06-27 2005-12-06 Via Technologies Inc. Module board having embedded chips and components and method of forming the same
US7312101B2 (en) * 2003-04-22 2007-12-25 Micron Technology, Inc. Packaged microelectronic devices and methods for packaging microelectronic devices
TWI246761B (en) * 2003-05-14 2006-01-01 Siliconware Precision Industries Co Ltd Semiconductor package with build-up layers formed on chip and fabrication method of the semiconductor package
KR100552588B1 (ko) * 2004-10-26 2006-02-15 삼성전자주식회사 반도체 장치의 제조 방법
JP4659488B2 (ja) * 2005-03-02 2011-03-30 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
KR100721353B1 (ko) * 2005-07-08 2007-05-25 삼성전자주식회사 칩 삽입형 매개기판의 구조와 제조 방법, 이를 이용한 이종칩의 웨이퍼 레벨 적층 구조 및 패키지 구조
WO2008087578A2 (en) * 2007-01-17 2008-07-24 Nxp B.V. A system-in-package with through substrate via holes
US20090057903A1 (en) * 2007-03-29 2009-03-05 Yoshio Okayama Semiconductor module, method for manufacturing semiconductor modules, semiconductor apparatus, method for manufacturing semiconductor apparatuses, and portable device
JP2009176978A (ja) * 2008-01-25 2009-08-06 Rohm Co Ltd 半導体装置
WO2011036915A1 (ja) * 2009-09-25 2011-03-31 シャープ株式会社 半導体デバイスの製造方法および半導体デバイス
JP5442424B2 (ja) * 2009-12-25 2014-03-12 新光電気工業株式会社 半導体装置
JP5503322B2 (ja) * 2010-02-15 2014-05-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US20110233718A1 (en) * 2010-03-25 2011-09-29 Qualcomm Incorporated Heterogeneous Technology Integration
DE102010042567B3 (de) * 2010-10-18 2012-03-29 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Herstellen eines Chip-Package und Chip-Package
US20120319295A1 (en) * 2011-06-17 2012-12-20 Chi Heejo Integrated circuit packaging system with pads and method of manufacture thereof
US8686543B2 (en) * 2011-10-28 2014-04-01 Maxim Integrated Products, Inc. 3D chip package with shielded structures
CN103107153B (zh) * 2011-11-15 2016-04-06 精材科技股份有限公司 晶片封装体及其形成方法
US8836327B2 (en) * 2011-12-07 2014-09-16 Texas Instruments Incorporated Micro-fabricated atomic magnetometer and method of forming the magnetometer
US8841768B2 (en) * 2012-07-23 2014-09-23 Infineon Technologies Ag Chip package and a method for manufacturing a chip package

Also Published As

Publication number Publication date
DE102013108987B4 (de) 2018-07-05
US20140057393A1 (en) 2014-02-27
CN103633042A (zh) 2014-03-12
US20160064362A1 (en) 2016-03-03
US8846452B2 (en) 2014-09-30
DE102013108987A1 (de) 2014-03-13
US10297583B2 (en) 2019-05-21

Similar Documents

Publication Publication Date Title
CN103633042B (zh) 半导体器件封装件及其封装方法
US10903316B2 (en) Radio frequency switches with air gap structures
US7626257B2 (en) Semiconductor devices and methods of manufacture thereof
EP3203507B1 (en) Semiconductor structure and fabrication method thereof
US8466054B2 (en) Thermal conduction paths for semiconductor structures
CN105280610B (zh) 3dic互连器件及其形成方法
CN103579186B (zh) 连接通孔至器件
TWI538173B (zh) 具背側散熱能力之絕緣體上半導體結構、自絕緣體上半導體元件進行散熱之方法及製造具有絕緣體上半導體晶圓之積體電路之方法
TWI397972B (zh) Semiconductor device manufacturing method
CN108122831A (zh) 形成保护层以防止形成泄漏路径
CN103972213B (zh) 具有多级互连的半导体器件及其形成方法
CN109560038A (zh) 互连结构及方法
TWI646643B (zh) 用於著陸在不同接觸區階層的接觸方案
US20150303108A1 (en) Method for forming semiconductor device
US20150054139A1 (en) Through-silicon via with sidewall air gap
CN106537600A (zh) 具有空隙加速击穿的mos反熔丝
CN104009085A (zh) 穿通孔及其形成方法
US9412736B2 (en) Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias
CN106340582A (zh) 鳍式fet技术的集成热电器件
CN105990228A (zh) 半导体器件结构及其形成方法
CN104851873B (zh) 势垒层结构及方法
CN102856246B (zh) 制造半导体器件的方法和半导体器件
TWI809525B (zh) 在環繞式閘極電晶體之間具有氣隙之半導體元件及其製備方法
CN106158853B (zh) 一种集成电路结构及其制造方法、半导体器件
US20120261790A1 (en) Substrate structure, semiconductor device, and method for manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20170517

CF01 Termination of patent right due to non-payment of annual fee