FR3003962B1 - Procede d'elaboration d'un masque de photolitographie destine a la formation de contacts, masque et circuit integre correspondants - Google Patents

Procede d'elaboration d'un masque de photolitographie destine a la formation de contacts, masque et circuit integre correspondants

Info

Publication number
FR3003962B1
FR3003962B1 FR1352894A FR1352894A FR3003962B1 FR 3003962 B1 FR3003962 B1 FR 3003962B1 FR 1352894 A FR1352894 A FR 1352894A FR 1352894 A FR1352894 A FR 1352894A FR 3003962 B1 FR3003962 B1 FR 3003962B1
Authority
FR
France
Prior art keywords
mask
formation
producing
photolitography
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1352894A
Other languages
English (en)
Other versions
FR3003962A1 (fr
Inventor
Guilhem Bouton
Patrick Regnier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1352894A priority Critical patent/FR3003962B1/fr
Priority to US14/221,401 priority patent/US10115666B2/en
Publication of FR3003962A1 publication Critical patent/FR3003962A1/fr
Priority to US14/956,903 priority patent/US10418322B2/en
Application granted granted Critical
Publication of FR3003962B1 publication Critical patent/FR3003962B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/50—Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

Procédé d'élaboration d'un masque de photolithographie destiné à la formation de plots de contact électriquement conducteurs entre des pistes d'un niveau de métallisation et des zones électriquement actives de circuits intégrés réalisés dans et sur une plaquette semi-conductrice, comprenant une élaboration (10) d'une première région de masque (RM1) comportant des premières zones d'ouvertures (30) destinées à la formation desdits plots de contact et possédant un premier taux d'ouverture inférieur à une valeur seuil, et une élaboration (11) d'une deuxième région de masque (RM2) comportant des zones d'ouvertures supplémentaires, le taux global d'ouverture dudit masque (MQ) étant supérieur ou égal à ladite valeur seuil.
FR1352894A 2013-03-29 2013-03-29 Procede d'elaboration d'un masque de photolitographie destine a la formation de contacts, masque et circuit integre correspondants Expired - Fee Related FR3003962B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1352894A FR3003962B1 (fr) 2013-03-29 2013-03-29 Procede d'elaboration d'un masque de photolitographie destine a la formation de contacts, masque et circuit integre correspondants
US14/221,401 US10115666B2 (en) 2013-03-29 2014-03-21 Method for making a photolithography mask intended for the formation of contacts, mask and integrated circuit corresponding thereto
US14/956,903 US10418322B2 (en) 2013-03-29 2015-12-02 Method for making a photolithography mask intended for the formation of contacts, mask and integrated circuit corresponding thereto

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1352894A FR3003962B1 (fr) 2013-03-29 2013-03-29 Procede d'elaboration d'un masque de photolitographie destine a la formation de contacts, masque et circuit integre correspondants

Publications (2)

Publication Number Publication Date
FR3003962A1 FR3003962A1 (fr) 2014-10-03
FR3003962B1 true FR3003962B1 (fr) 2016-07-22

Family

ID=48656119

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1352894A Expired - Fee Related FR3003962B1 (fr) 2013-03-29 2013-03-29 Procede d'elaboration d'un masque de photolitographie destine a la formation de contacts, masque et circuit integre correspondants

Country Status (2)

Country Link
US (2) US10115666B2 (fr)
FR (1) FR3003962B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160015094A (ko) 2014-07-30 2016-02-12 삼성전자주식회사 오버레이 마크, 오버레이 마크를 형성하는 방법 및 오버레이 마크를 이용하여 반도체 소자를 제조하는 방법
US10002222B2 (en) * 2016-07-14 2018-06-19 Arm Limited System and method for perforating redundant metal in self-aligned multiple patterning
CN111640658B (zh) * 2019-03-01 2023-04-25 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60153148A (ja) * 1984-01-20 1985-08-12 Nec Corp 半導体装置
JP3348322B2 (ja) * 1994-01-06 2002-11-20 ソニー株式会社 半導体装置の製造方法
US5753417A (en) * 1996-06-10 1998-05-19 Sharp Microelectronics Technology, Inc. Multiple exposure masking system for forming multi-level resist profiles
TW396524B (en) 1998-06-26 2000-07-01 United Microelectronics Corp A method for fabricating dual damascene
US6306755B1 (en) 1999-05-14 2001-10-23 Koninklijke Philips Electronics N.V. (Kpenv) Method for endpoint detection during dry etch of submicron features in a semiconductor device
KR100343291B1 (ko) 1999-11-05 2002-07-15 윤종용 반도체 장치의 커패시터 형성 방법
JP3818828B2 (ja) * 2000-06-05 2006-09-06 シャープ株式会社 半導体装置の製造方法
US6703170B1 (en) * 2000-12-13 2004-03-09 Dupont Photomasks, Inc. Method and apparatus for reducing loading effects on a semiconductor manufacturing component during an etch process
US6433878B1 (en) * 2001-01-29 2002-08-13 Timbre Technology, Inc. Method and apparatus for the determination of mask rules using scatterometry
JP2002319619A (ja) * 2001-04-20 2002-10-31 Matsushita Electric Ind Co Ltd 半導体装置およびエッチング方法
JP4536314B2 (ja) 2002-06-18 2010-09-01 ルネサスエレクトロニクス株式会社 半導体記憶装置及び半導体記憶装置の製造方法
JP2005064226A (ja) * 2003-08-12 2005-03-10 Renesas Technology Corp 配線構造
JP4316358B2 (ja) * 2003-11-27 2009-08-19 株式会社東芝 半導体記憶装置及びその製造方法
JP4338614B2 (ja) * 2004-09-29 2009-10-07 シャープ株式会社 半導体装置およびその製造方法
US7547584B2 (en) * 2005-05-27 2009-06-16 United Microelectronics Corp. Method of reducing charging damage to integrated circuits during semiconductor manufacturing
DE102006004428B4 (de) 2006-01-31 2017-12-21 Globalfoundries Inc. Technik zum zerstörungsfreien Überwachen der Metallablösung in Halbleiterbauelementen
US7767570B2 (en) * 2006-03-22 2010-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy vias for damascene process
US7739632B2 (en) * 2006-08-18 2010-06-15 International Business Machines Corporation System and method of automated wire and via layout optimization description
JP5082338B2 (ja) * 2006-08-25 2012-11-28 東京エレクトロン株式会社 エッチング方法及びエッチング装置
US20090087956A1 (en) * 2007-09-27 2009-04-02 Texas Instruments Incorporated Dummy Contact Fill to Improve Post Contact Chemical Mechanical Polish Topography
KR100895375B1 (ko) * 2007-10-31 2009-04-29 주식회사 하이닉스반도체 반도체 소자의 형성 방법
KR20090046627A (ko) * 2007-11-06 2009-05-11 주식회사 동부하이텍 반도체 소자 및 그 제조 방법
KR100934808B1 (ko) * 2008-03-03 2009-12-31 주식회사 하이닉스반도체 반도체 소자의 캐패시터 형성 방법
JP5223571B2 (ja) 2008-09-30 2013-06-26 富士通株式会社 半導体装置、基板設計方法、基板設計装置
US8846452B2 (en) 2012-08-21 2014-09-30 Infineon Technologies Ag Semiconductor device package and methods of packaging thereof
US20140106264A1 (en) * 2012-10-11 2014-04-17 Infineon Technologies Ag Photolithography mask, photolithography mask arrangement, and method for exposing a wafer

Also Published As

Publication number Publication date
FR3003962A1 (fr) 2014-10-03
US10115666B2 (en) 2018-10-30
US20140291858A1 (en) 2014-10-02
US10418322B2 (en) 2019-09-17
US20160086883A1 (en) 2016-03-24

Similar Documents

Publication Publication Date Title
TW490807B (en) Semiconductor device
JP2013093579A5 (fr)
FR3003962B1 (fr) Procede d'elaboration d'un masque de photolitographie destine a la formation de contacts, masque et circuit integre correspondants
TW201614805A (en) Densely packed standard cells for integrated circuit products
JP2014225713A5 (fr)
TW200701398A (en) Interconnect structure for integrated circuits
Rohbani et al. LAXY: A location-based aging-resilient Xy-Yx routing algorithm for network on chip
BR102012018610B8 (pt) método para formar um transistor de efeito de campo metal-óxido-semicondutor (mosfet) vertical de carboneto de silício (sic)
TW200739750A (en) Lateral power devices with self-biasing electrodes
WO2012087580A3 (fr) Couche riche en pièges pour dispositifs à semi-conducteurs
JP2018504778A5 (fr)
JP2016032243A5 (fr)
TW200739381A (en) Integrated configuration, flow and execution system for semiconductor device experimental flows and production flows
TW200723394A (en) Manufacturing method for semiconductor chips, and semiconductor chip
JP2013514632A5 (fr)
WO2005081323A3 (fr) Dispositifs a semi-conducteur a tranchees-grilles et fabrication
TW200731509A (en) Semiconductor device and manufacturing method thereof
TW200802705A (en) Interconnect structure with a barrier-redundancy feature
SG10201803922PA (en) Semiconductor Device
JP2014120758A5 (fr)
SE0700896L (sv) Halvledarkomponent i kiselkarbid
Dasgupta et al. Compact modeling of surface potential, charge, and current in nanoscale transistors under quasi-ballistic regime
TW200636878A (en) Microelectronic assemblies having compliancy
Mavredakis et al. Understanding the bias dependence of low frequency noise in single layer graphene FETs
MX2019009532A (es) Dispositivo semiconductor y metodo de fabricacion del mismo.

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 4

PLFP Fee payment

Year of fee payment: 5

PLFP Fee payment

Year of fee payment: 6

PLFP Fee payment

Year of fee payment: 7

PLFP Fee payment

Year of fee payment: 8

ST Notification of lapse

Effective date: 20211105