FR2817399B1 - Puce electronique multifonctions - Google Patents

Puce electronique multifonctions

Info

Publication number
FR2817399B1
FR2817399B1 FR0015524A FR0015524A FR2817399B1 FR 2817399 B1 FR2817399 B1 FR 2817399B1 FR 0015524 A FR0015524 A FR 0015524A FR 0015524 A FR0015524 A FR 0015524A FR 2817399 B1 FR2817399 B1 FR 2817399B1
Authority
FR
France
Prior art keywords
elementary
chip
electronic chip
multifunctional electronic
elementary chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0015524A
Other languages
English (en)
Other versions
FR2817399A1 (fr
Inventor
Yvon Gris
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0015524A priority Critical patent/FR2817399B1/fr
Priority to US09/999,208 priority patent/US6806536B2/en
Publication of FR2817399A1 publication Critical patent/FR2817399A1/fr
Application granted granted Critical
Publication of FR2817399B1 publication Critical patent/FR2817399B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FR0015524A 2000-11-30 2000-11-30 Puce electronique multifonctions Expired - Fee Related FR2817399B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0015524A FR2817399B1 (fr) 2000-11-30 2000-11-30 Puce electronique multifonctions
US09/999,208 US6806536B2 (en) 2000-11-30 2001-11-30 Multiple-function electronic chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0015524A FR2817399B1 (fr) 2000-11-30 2000-11-30 Puce electronique multifonctions

Publications (2)

Publication Number Publication Date
FR2817399A1 FR2817399A1 (fr) 2002-05-31
FR2817399B1 true FR2817399B1 (fr) 2003-10-31

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FR (1) FR2817399B1 (fr)

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US7098070B2 (en) * 2004-11-16 2006-08-29 International Business Machines Corporation Device and method for fabricating double-sided SOI wafer scale package with through via connections
JP4497165B2 (ja) * 2007-02-05 2010-07-07 株式会社デンソー 半導体装置の製造方法
TWI335059B (en) * 2007-07-31 2010-12-21 Siliconware Precision Industries Co Ltd Multi-chip stack structure having silicon channel and method for fabricating the same
US8846452B2 (en) * 2012-08-21 2014-09-30 Infineon Technologies Ag Semiconductor device package and methods of packaging thereof
US10043787B2 (en) * 2017-01-10 2018-08-07 International Business Machines Corporation Optoelectronic chip embedded organic substrate
US11536800B2 (en) 2017-12-22 2022-12-27 Hrl Laboratories, Llc Method and apparatus to increase radar range
US11527482B2 (en) 2017-12-22 2022-12-13 Hrl Laboratories, Llc Hybrid integrated circuit architecture
WO2019125587A1 (fr) * 2017-12-22 2019-06-27 Hrl Laboratories, Llc Architecture de circuit intégré hybride
US10957537B2 (en) 2018-11-12 2021-03-23 Hrl Laboratories, Llc Methods to design and uniformly co-fabricate small vias and large cavities through a substrate
US11972970B1 (en) 2020-09-01 2024-04-30 Hrl Laboratories, Llc Singulation process for chiplets

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JP3190057B2 (ja) * 1990-07-02 2001-07-16 株式会社東芝 複合集積回路装置
US5824186A (en) * 1993-12-17 1998-10-20 The Regents Of The University Of California Method and apparatus for fabricating self-assembling microstructures
US6362012B1 (en) * 2001-03-05 2002-03-26 Taiwan Semiconductor Manufacturing Company Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications

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US20020110952A1 (en) 2002-08-15
US6806536B2 (en) 2004-10-19

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