CN108511386B - 分段式防护环及芯片边缘密封件 - Google Patents
分段式防护环及芯片边缘密封件 Download PDFInfo
- Publication number
- CN108511386B CN108511386B CN201810150657.4A CN201810150657A CN108511386B CN 108511386 B CN108511386 B CN 108511386B CN 201810150657 A CN201810150657 A CN 201810150657A CN 108511386 B CN108511386 B CN 108511386B
- Authority
- CN
- China
- Prior art keywords
- low
- dielectric
- edge seal
- semiconductor
- guard ring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003989 dielectric material Substances 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 48
- 239000004065 semiconductor Substances 0.000 claims description 41
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 27
- 239000012212 insulator Substances 0.000 claims description 17
- 238000002161 passivation Methods 0.000 claims description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 8
- 229920001721 polyimide Polymers 0.000 claims description 7
- 239000004642 Polyimide Substances 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 4
- 229910000077 silane Inorganic materials 0.000 claims description 4
- 238000007789 sealing Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 62
- 230000008569 process Effects 0.000 description 44
- 238000000151 deposition Methods 0.000 description 14
- 150000004767 nitrides Chemical class 0.000 description 14
- 238000005530 etching Methods 0.000 description 11
- 238000000206 photolithography Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 230000009977 dual effect Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229920006254 polymer film Polymers 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- -1 silicon carbide nitride Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本揭示内容涉及分段式防护环及芯片边缘密封件,其有关于半导体结构,且更特别的是,有关于分段式防护环及芯片边缘密封件和制法。该结构包括:防护环结构,在一低k介电材料中形成;以及边缘密封结构,形成为穿过该低k介电材料至少直到在该低k介电材料下面的衬底。
Description
技术领域
本揭示内容有关于半导体结构,且更特别的是,有关于分段式防护环及芯片边缘密封件和制法。
背景技术
例如分段式防护环的防护环技术被使用于许多不同半导体技术,例如GaAs、SiGe、RFCMOS及RFSOI。例如,射频(RF)电路需要分段式防护环以避免寄生耦合及感应耦合(后一现象可与连续防护环一起发生)。
RF技术在中段(MOL)及后段(BEOL)工艺通常包含非多孔介电材料。为了进一步改善RF技术,例如,改善RF电路效能,在MOL或BEOL加工阶层需要低k介电多孔材料。例如SiCOH或p-SiCOH的低k介电多孔材料广泛使用于例如90纳米及更小世代用于数个BEOL配线阶层(wiring level)的先进CMOS技术。
于低k介电多孔应用中,特别有用的是防止可能导致SiCOH破裂或铜可靠度劣化(例如,电迁移、应力迁移等等)的湿气入侵的防护环。但是,使用分段式防护环可能导致低k介电多孔应用的可靠度失效。因此,已知具有分段式防护环的RFSOI芯片与低K SiCOH或p-SiCOH MOL/BEOL不相容。
发明内容
在本揭示内容的一态样中,一种结构,其包含:防护环结构,在一低k介电材料中形成;以及边缘密封结构,形成为穿过该低k介电材料至少直到在该低k介电材料下面的一衬底。
在本揭示内容的一态样中,一种结构,其包含:一绝缘体上覆硅衬底;一中段及后段介电质低k介电材料,在该绝缘体上覆硅衬底上;配线结构,在该中段及后段介电质低k介电材料中形成直到该绝缘体上覆硅衬底;分段式防护环结构,在该中段及后段介电质低k介电材料中形成;以及边缘密封结构,形成为延伸穿过该中段及后段介电质低k介电材料。
在本揭示内容的一态样中,一种方法,包含:形成在该绝缘体上覆硅衬底上的中段及后段介电质低k介电材料;形成在该中段及后段介电质低k介电材料中形成直到该绝缘体上覆硅衬底的一配线结构;形成在该中段及后段介电质低k介电材料中形成的一分段式防护环结构;以及形成延伸穿过该中段及后段介电质低k介电材料的一边缘密封结构。
附图说明
以下说明详述本揭示内容,其中参考多个附图以不具限定性的方式举例说明本揭示内容的示范具体实施例。
图1A至图1C根据本揭示内容的数个态样图示结构及各个工艺。
图2除其他特征以外根据本揭示内容的数个态样图示边缘密封结构及各个工艺。
图3根据本揭示内容的其他态样图示结构及各个工艺。
图4根据本揭示内容的其他态样图示结构及各个工艺。
图5A至图5D根据本揭示内容的其他态样图示结构及各个工艺。
具体实施方式
本揭示内容有关于半导体结构,且更特别的是,有关于分段式防护环及芯片边缘密封件和制法。具体而言,本揭示内容提供的是在中段(MOL)及/或后段(BEOL)加工时具有低k介电材料的分段式防护环及芯片边缘密封件。有利的是,本揭示内容提供具有包含低KSiCOH或p-SiCOH MOL/BEOL材料的RFSOI芯片的分段式防护环与制造加工的相容性。
在数个具体实施例中,芯片边缘密封结构可设在最终钝化氮化物/聚亚酰胺膜中,这只需要一个掩模。此芯片边缘密封结构可排除前段(FEOL)埋藏绝缘体上覆硅(SOI)接触或边缘密封件,在当前SOI技术中,其填充通过埋藏氧化物(BOX)接触件连接SOI顶部硅与硅处置晶片(silicon handle wafer)的半导体或导体,且可使用于有非分段式防护环设计的先进CMOS技术(例如,14纳米)。
在其他具体实施例中,在金属-绝缘体-金属(MIM)板形成后以及在通孔层间介电质(ILD)沉积之前,可提供芯片边缘密封结构。在此实作中,厚ILD氧化物沉积可用来填充沟槽以形成该芯片边缘密封件。在另一具体实施例中,芯片边缘密封结构可设有气隙。在此实作中,可使用在形成低系数SOI开关(low Coff SOI switch)期间共享的单一气隙掩模。此外,在此实作中,可提供最佳湿气阻隔保护的材料薄层(例如,约5纳米),例如氧化铝(Al2O3)。有利的是,本文所提供的工艺及所得结构可排除使用上述视需要的FEOL埋藏层隔离边缘密封件。此外,边缘密封结构可使用于分段式及非分段式防护环结构两者。
可用使用许多不同工具的许多方法制造本揭示内容的防护环及芯片边缘密封结构。然而,通常该方法及工具用来形成有微米及纳米级尺寸的结构。用来制造本揭示内容的防护环及芯片边缘密封结构的该方法,亦即,技术,选自集成电路(IC)技术。例如,该结构建立于晶片上以及实现于在晶片上面用光刻工艺(photolithographic process)图案化的材料膜中。特别是,防护环及芯片边缘密封结构的制造使用以下3个基本建造区块:(i)沉积数个材料薄膜于衬底上,(ii)用光刻成像法铺设图案化掩模于薄膜上面,以及(iii)对于该掩模选择性地蚀刻薄膜。
图1A至图1C根据本揭示内容的数个态样图示结构及各个工艺。图1A为该结构的横截面图以及图1C为图1A的结构的俯视图。图1B的部分展开图图示形成于低k介电材料中的防护环结构及沟槽。如图2所示,例如,该沟槽填充材料芯片边缘密封件。
特别是,图1A至图1C的结构10包括绝缘体上覆硅(SOI)衬底12。在数个具体实施例中,SOI衬底12包括处置晶片(handle wafer)14与在半导体层18底下的埋藏绝缘体层16。在数个具体实施例中,埋藏绝缘体层16可为二氧化硅或蓝宝石;不过,应了解,绝缘体及处置晶片的选择大体取决于所欲应用。例如,层16的蓝宝石使用于高效能射频(RF)及辐射敏感应用;然而,二氧化硅使用于例如微电子装置的缩减短沟道效应。在数个具体实施例中,处置晶片14可为硅或蓝宝石。半导体层18可由任何适当半导体材料构成,包括但不限于:硅、硅锗(SiGe)、硅锗碳(SiGeC)、硅碳(SiC)、砷化镓(GaAs)、砷化铟(InAs)、磷化铟(InP)等等。SOI衬底12可用任何习知工艺形成,例如晶片接合(wafer bonding)、氧离子植入硅晶隔离(Separation by IMplantation of Oxygen,SiMOX)等等。
仍参考图1A至图1C,低k介电材料20在MOL及/或BEOL工艺形成于半导体层18上面。在数个具体实施例中,低k介电材料20可为使用习知沉积方法沉积的非多孔或多孔聚合物、掺碳氧化物或氧化物或彼等的组合。在更特定的具体实施例中,低k介电材料20可为低KSiCOH或多孔SiCOH材料。低k介电材料20可用化学气相沉积工艺沉积。
在低k介电材料20中形成直到半导体层18的多个传导配线及通孔结构22(此后通称为配线结构)及防护环结构24。在一或更多配线或通孔形成于低k介电质中的情形下,可在低k金属间介电质或者是氧化物金属间介电质中形成该配线或通孔。防护环结构24较佳为由金属通孔及配线层形成位于芯片边缘附近的分段式防护环结构。防护环结构24可加以分段来减少射频耦合。更特别的是,防护环结构24为使用习知镶嵌或双层镶嵌工艺(dualdamascene process)在配线结构22外形成于芯片边缘附近的金属结构。配线结构22也可用习知镶嵌或双层镶嵌工艺形成。
例如,配线结构22与分段式防护环结构24可使用习知沉积、光刻及蚀刻工艺(例如,镶嵌或双层镶嵌工艺)形成。具体言之,在沉积低k介电材料20的各层后,沉积于低k介电层20表面上的抗蚀剂暴露于能量(光线)以形成图案(开口)。用选择性化学物的蚀刻工艺,例如反应性离子蚀刻(RIE),会通过抗蚀剂的开口用来在低k介电材料20中形成一或更多通孔及沟槽。在数个具体实施例中,光刻及蚀刻步骤可为单一或镶嵌工艺。然后,抗蚀剂可用习知氧气灰化法(oxygen ashing process)或其他习知去膜剂(stripant)移除。在移除抗蚀剂后,用例如化学气相沉积(CVD)工艺的习知沉积工艺沉积导电材料于通孔及沟槽中,例如铜、铝、钨等等。低k介电材料20表面上的任何残余金属材料可用习知化学机械研磨(CMP)工艺移除。此工艺继续直到所有配线层(例如,M1阶层、M2阶层等等)形成。
图1A至图1C进一步图示最后金属层或焊垫25形成为至少与配线结构22及防护环结构24电气及直接接触。最后金属层或焊垫25可用任何减去法形成,例如。举例说明,在焊垫的实作中,铝材料可沉积于低k介电材料20的表面上,接着是图案化及蚀刻工艺(例如,光刻及RIE工艺)。形成氧化物及/或氮化物层26于最后金属层或焊垫25与低k介电材料20的任何暴露表面上面。氧化物层26可用电浆增强(PE)CVD工艺沉积到有约0.5微米的厚度;然而本揭示内容也可考虑其他的尺寸。
仍参考图1A至图1C,形成穿过结构10的诸层的沟槽28且较佳为低于低k介电材料20。在更特定的具体实施例中,形成穿过低k介电材料20且延伸到半导体层18的沟槽28,甚至延伸到埋藏绝缘体层16或到埋藏绝缘体层16下面为更佳。沟槽28可具有约2微米的宽度;然而本文也可考虑其他的尺寸。在数个具体实施例中,熟谙此艺者应了解,沟槽28可用习知光刻及蚀刻工艺形成。
如图2所示,沟槽28会用来在芯片相对于配线结构22及防护环结构24的最外面部分处形成边缘密封结构30。更特别的是,边缘密封结构30的形成是通过沉积材料于沟槽28内。例如,边缘密封结构30包括形成于沟槽28侧壁上例如约有0.5微米的薄钝化层32。在数个具体实施例中,钝化层32可为用习知PECVD工艺沉积的氧化物材料或氮化物材料或彼等的组合。该PECVD工艺也会沉积钝化层32于氧化物层26上面。在沉积钝化层32后,沉积聚亚酰胺膜于沟槽28的其余部分内,例如,填充沟槽28。使用于晶片膜34的最终钝化的聚亚酰胺或其他聚合物膜34可为旋涂(spin on)有机材料(或其他材料)。膜32及/或34应不透水以防止水或湿气通过低k材料入侵芯片。
以此方式,本文所提供的工艺及所得结构排除使用视需要的前段(FEOL)埋藏层隔离边缘密封件。此外,边缘密封结构30可使用于分段式及非分段式防护环结构24两者。
图3根据本揭示内容的其他态样图示结构及各个工艺。在图3的结构10'中,在制造金属-绝缘体-金属(MIM)电容器结构38及数层配线结构22及防护环结构24后,例如配线结构22及防护环结构24的M1及M2阶层,由氧化物或氮化物材料36形成边缘密封结构30'。MIM电容器结构38可为任何BEOL被动装置,例如薄膜电阻器或配线。跟前述态样一样,形成直到半导体层18的配线结构22及防护环结构24。
作为图3的具体实施例的更特定实施例,在形成MIM或其他被动结构38后,形成穿过结构10'的诸层且穿过及低于低k介电材料20为较佳的沟槽28'。在更特定的具体实施例中,形成穿过低k介电材料20且延伸到半导体层18且延伸到埋藏绝缘体层16或到埋藏绝缘体层16下面为更佳的沟槽28'。在数个具体实施例中,熟谙此艺者应了解,沟槽28'可用习知光刻及蚀刻工艺形成。跟前述具体实施例一样,沟槽28'可具有约2微米的宽度;然而本文可考虑其他的尺寸。
在形成沟槽28'后,使用习知CVD、物理气相沉积或类似工艺沉积氧化物及/或氮化物材料36于MIM结构38上面以及于沟槽28'内。在数个具体实施例中,氧化物的沉积可能导致材料36在沟槽28'内的夹止(pinch-off)。接着,此夹止会在沟槽28'内形成气隙40。因此,气隙40的尺寸小于被填充的沟槽28'。氧化物材料可经历视需要的CMP工艺,这会产生平坦的表面用于如本文所述的附加加工。以此方式,边缘密封结构30'会位在芯片相对于配线结构22及分段式防护环结构24两者的最外面部分处。
仍参考图3,使用习知光刻、蚀刻及沉积工艺,配线结构22及分段式防护环结构24的上层部分(例如,第三或以上的金属电线/通孔阶层)可形成于经平坦化的氧化物或氮化物材料36上。最后金属层或焊垫25形成为至少与配线结构22及防护环结构24电气及直接接触。如图3的第三金属层所示的最后金属层或焊垫25可用任何减去法形成,如本文所述。介电层26形成于最后金属层或焊垫25与低k介电材料20的任何暴露表面上面。氧化物层26可用PECVD工艺沉积到0.5微米的厚度;然而本揭示内容也可考虑其他的尺寸。例如约0.5微米的薄钝化层32形成于氧化物层26上面以及聚亚酰胺或其他视需要的聚合物膜34沉积于钝化层32上。聚亚酰胺膜34可为旋涂有机材料(或其他材料)。
图4根据本揭示内容的其他态样图示结构及各个工艺。在图4的结构10”中,气隙或衬有氧化物的气隙30”可形成于低k介电材料20中。例如,在使用单一或双层镶嵌工艺在低k介电材料20(例如,SiCOH)中形成配线结构22与分段式防护环结构24的头一个或多个阶层后,在低k介电材料20中形成直到分段式防护环24的分段开口的沟槽。在数个具体实施例中,沟槽使用习知光刻及蚀刻(RIE)工艺形成,如前述。沟槽可填充氧化物材料直到它被夹止,从而产生气隙30”或可完全填充氧化物。例如,PECVD硅烷氧化物可沉积于沟槽内以形成气隙30”。以此方式,可在配线结构22的M1阶层(下阶层)形成气隙30”。图示两个平行气隙30”作为实施例,但是可使用任意多个气隙,例如,一或更多,以及气隙的俯视图布局可为矩形(图示)、圆形、多边形等等。
在气隙30”形成后,可毯覆式沉积(blanket deposit)氧化物材料于气隙30”上方以形成层间介电层20'。在数个具体实施例中,层间介电层20'不是低k介电材料20。可用已描述于本文的方式制造其余配线结构,包括配线结构22(M2阶层及以上)与分段式防护环结构24的上阶层,以及最后金属层或焊垫25等等。例如,利用光刻、蚀刻及沉积步骤,如本文所述,例如M2阶层及以上的上层配线结构可制造于介电层20'中。
在图4的替代具体实施例中,双层镶嵌配线结构22与分段式防护环结构24在MOL形成于低k介电材料20(例如,SiCOH)中,接着沉积例如SiCxNyHz的NBLoK 20'于双层镶嵌配线结构22及分段式防护环结构24上面。在低k介电材料20(及NBLoK 20')中形成直到分段式防护环24的分段开口的沟槽。在数个具体实施例中,沟槽约有0.3微米宽;然而本文可考虑其他的尺寸。在数个具体实施例中,沟槽可能已经向下蚀刻到NFET开关的PC以形成气隙,例如,约0.18微米深的沟槽。然后,沉积PECVD硅烷氧化物以夹止气隙30”。在一附加实作中,在半导体层18及绝缘体层16中可提供材料42(例如,氧化铝)的薄层(例如,约5纳米)用于完美湿气阻隔保护(在芯片的最外面部分)。其余结构10”可用已描述于本文的方式制造,包括配线结构22的上层部分(例如,M2阶层及以上)与低k介电材料20的分段式防护环结构24,以及最后金属层或焊垫25等等。或者,如果低k介电质使用于多个配线阶层,则气隙会延伸穿过该多个配线阶层。
图5A至图5D的不同视图根据本揭示内容的其他态样图示结构及各个工艺。此外,更详细具体言之,图5A为芯片边缘密封件及分段式防护环结构的俯视图。图5B为图5A的结构的展开图,以及图5C与图5D为各自沿着图5B中的直线A-A及B-B绘出的横截面图。
特别是,图5A至图5D的结构10”'包含气隙50,该气隙50较佳为置于衬底98或特征105上方且接触衬底98或特征105,例如,形成于硅衬底上的FET、电阻器、电容器等等,且更特别的是,落在位于衬底98或特征100上面的氮化物膜95'上的FET、电阻器、电容器等等(图5C)。当具体指定气隙接触衬底98或特征100时,则意谓接触到或蚀刻到氮化物层95'中使得气隙下方未留下低k介电质97。氮化物层95’可由任何非低k介电质构成,例如氧化物、碳化硅(SiC)、氮碳化硅(SiCN)等等。在对特征100进行沟槽蚀刻的选项上,在气隙50的工艺所使用的沟槽蚀刻(例如,RIE)可浅些,从而节省时间及制造成本。在数个具体实施例中,气隙50也可落在结构的其他位置或可蚀刻到衬底98中。
如同本揭示内容形成边缘密封结构的其他态样,气隙50设在例如SiCOH的低k介电材料20中(图5A至图5D)。气隙50可衬有氧化物材料110,它也可使用于,例如,在低k介电材料20上面的上配线阶层(例如,M2配线层)(图5C至图5D)。气隙50可部分或完全填充氧化物110。气隙50可宽约180纳米,如熟谙此艺者所习知,其是由夹止工艺形成。例如,通过沉积氮化物材料95于先前形成的第一阶层配线105’上面,该第一阶层配线形成裂纹止挡(crackstop)与芯片上的其他配线两者,接着沉积氧化物材料96用来形成下一个配线阶层的配线及通孔,从而形成气隙50。此氮化物95及氧化物96沉积于在低k介电材料97中形成的配线及裂纹止挡上面。氧化物96与氮化物95可使用例如PECVD工艺沉积。如图5D所示,气隙50部分位在例如分段式防护环结构的配线结构105’的至少一侧上面。以此方式,气隙50在配线结构105的两侧及之间延伸而形成边缘密封结构。在数个具体实施例中,配线结构105可为第一金属层(例如,M1层)的接触。
图5A至图5D图示形成用于第一配线阶层的低k介电质以及在它下面的接触。该低k介电层可使用于具有完全延伸穿过低k介电层的气隙的任一或更多配线、接触或通孔阶层。图5C图示衬有氧化物110的气隙50,其是从氧化物层96延伸到在衬底98上面的氮化物层95'。图5D图示衬有氧化物110的气隙50,其部分落在裂纹止挡第一金属层105'上以及也落在氮化物层95’上。再者,该气隙完全隔离低k介电质97。
上述该(等)方法使用于集成电路芯片的制造。所得集成电路芯片可由制造者以原始晶片形式(raw wafer form)(也就是具有多个未封装芯片的单一晶片)、作为裸晶粒(bare die)或已封装的形式来销售。在后一情形下,芯片装在单芯片封装体中(例如,塑胶载体(plastic carrier),具有固定至主机板或其他更高层载体的引脚(lead)),或多芯片封装体中(例如,具有表面互连件(surface interconnection)或内嵌互连件(buriedinterconnection)任一或两者兼具的陶瓷载体)。然后,在任一情形下,芯片与其他芯片、离散电路元件及/或其他信号处理装置整合成为(a)中间产品(例如,主机板),或(b)最终产品中的任一者的一部分。该最终产品可为包括集成电路芯片的任何产品,从玩具及其他低端应用到有显示器、键盘或其他输入装置及中央处理器的先进计算机产品不等。
为了图解说明已呈现本揭示内容的各种具体实施例的描述,但是并非旨在穷尽或限定于所揭示的具体实施例。本技艺一般技术人员明白仍有许多修改及变体而不脱离所述具体实施例的范畴及精神。使用于本文的术语经选定成可最好地解释具体实施例的原理、实际应用或优于在市上可找到的技术的技术改善,或使得本技艺一般技术人员能够了解揭示于本文的具体实施例。
Claims (16)
1.一种半导体结构,包含:
防护环结构,在低k介电材料中形成;
边缘密封结构,形成为穿过该低k介电材料至少直到在该低k介电材料下面的衬底,其中,该边缘密封结构为填充有氧化物材料的一沟槽,该氧化物材料也正覆盖金属绝缘体金属结构;以及
聚合物材料膜,形成在该防护环结构和该边缘密封结构上,
其中,该衬底包含绝缘层上覆的半导体材料和该绝缘层下方的半导体处置衬底,该边缘密封结构延伸穿过该半导体材料至该绝缘层底下且进入该半导体处置衬底。
2.如权利要求1所述的半导体结构,其中,该低k介电材料为低KSiCOH或p-SiCOH的中段及/或后段介电材料。
3.如权利要求1所述的半导体结构,其中,该防护环结构为分段式防护环结构。
4.如权利要求3所述的半导体结构,其中,该边缘密封结构为衬有钝化层且填充有聚亚酰胺的沟槽。
5.如权利要求4所述的半导体结构,其中,该聚亚酰胺在最后金属层或焊垫上面受到平坦化。
6.如权利要求1所述的半导体结构,其中,填充有该氧化物材料的该沟槽低于最后金属层或焊垫。
7.如权利要求6所述的半导体结构,其中,填充有该氧化物材料的该沟槽包括气隙。
8.一种半导体结构,包含:
防护环结构,在低k介电材料中形成;
边缘密封结构,形成为穿过该低k介电材料至少直到在该低k介电材料下面的衬底,其中,该边缘密封结构为填充有氧化物材料的一沟槽,该氧化物材料也正覆盖金属绝缘体金属结构;以及
聚合物材料膜,形成在该防护环结构和该边缘密封结构上,
其中,该边缘密封结构为一或更多气隙,其形成于用该氧化物材料夹止的该低k介电材料中。
9.如权利要求8所述的半导体结构,其中,该氧化物材料为PECVD硅烷氧化物。
10.一种半导体结构,包含:
绝缘体上覆硅衬底;
中段及后段介电质低k介电材料,在该绝缘体上覆硅衬底上;
配线结构,在该中段及后段介电质低k介电材料中形成直到该绝缘体上覆硅衬底;
分段式防护环结构,在该中段及后段介电质低k介电材料中形成;
边缘密封结构,形成为延伸穿过该中段及后段介电质低k介电材料,其中,该边缘密封结构为填充有氧化物材料的一沟槽,该氧化物材料覆盖金属绝缘体金属结构;以及
聚合物材料膜,形成在该分段式防护环结构和该边缘密封结构上,
其中,该绝缘体上覆硅衬底包含绝缘层上覆的半导体材料和该绝缘层下方的半导体处置衬底,该边缘密封结构延伸穿过该半导体材料至该绝缘层底下且进入该半导体处置衬底。
11.如权利要求10所述的半导体结构,其中,该金属绝缘体金属结构低于最后金属层或焊垫。
12.如权利要求11所述的半导体结构,其中,填充有该氧化物材料的该沟槽包括一气隙。
13.一种半导体结构,包含:
绝缘体上覆硅衬底;
中段及后段介电质低k介电材料,在该绝缘体上覆硅衬底上;
配线结构,在该中段及后段介电质低k介电材料中形成直到该绝缘体上覆硅衬底;
分段式防护环结构,在该中段及后段介电质低k介电材料中形成;
边缘密封结构,形成为延伸穿过该中段及后段介电质低k介电材料,其中,该边缘密封结构为填充有氧化物材料的一沟槽,该氧化物材料也正覆盖金属绝缘体金属结构;以及
聚合物材料膜,形成在该分段式防护环结构和该边缘密封结构上,
其中,该边缘密封结构为一或更多气隙,其形成于用该氧化物材料夹止的该低k介电材料中。
14.如权利要求13所述的半导体结构,其中,该一或更多气隙在该配线结构的一下阶层。
15.如权利要求13所述的半导体结构,其中,该氧化物材料为PECVD硅烷氧化物。
16.一种制造半导体结构的方法,该方法包含:
在绝缘体上覆硅衬底上形成中段及后段介电质低k介电材料;
形成在该中段及后段介电质低k介电材料中形成直到该绝缘体上覆硅衬底的一配线结构;
形成在该中段及后段介电质低k介电材料中形成的一分段式防护环结构;
形成延伸穿过该中段及后段介电质低k介电材料的一边缘密封结构,其中,该边缘密封结构为填充有氧化物材料的一沟槽,该氧化物材料也正覆盖金属绝缘体金属结构;以及
在该分段式防护环结构和该边缘密封结构上形成聚合物材料膜,
其中,该绝缘体上覆硅衬底包含绝缘层上覆的半导体材料和该绝缘层下方的半导体处置衬底,该边缘密封结构延伸穿过该半导体材料至该绝缘层底下且进入该半导体处置衬底。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/443,276 | 2017-02-27 | ||
US15/443,276 US10062748B1 (en) | 2017-02-27 | 2017-02-27 | Segmented guard-ring and chip edge seals |
Publications (2)
Publication Number | Publication Date |
---|---|
CN108511386A CN108511386A (zh) | 2018-09-07 |
CN108511386B true CN108511386B (zh) | 2023-06-16 |
Family
ID=63208306
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201810150657.4A Active CN108511386B (zh) | 2017-02-27 | 2018-02-13 | 分段式防护环及芯片边缘密封件 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10062748B1 (zh) |
CN (1) | CN108511386B (zh) |
TW (1) | TWI696249B (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10930730B2 (en) * | 2017-07-18 | 2021-02-23 | Qualcomm Incorporated | Enhanced active and passive devices for radio frequency (RF) process and design technology |
US11574863B2 (en) * | 2021-02-08 | 2023-02-07 | Globalfoundries U.S. Inc. | Local interconnect layer with device within second dielectric material, and related methods |
US11543606B2 (en) | 2021-03-09 | 2023-01-03 | Globalfoundries U.S. Inc. | Photonics chips with an edge coupler and a continuous crackstop |
US11855005B2 (en) | 2021-06-21 | 2023-12-26 | Globalfoundries U.S. Inc. | Crackstop with embedded passive radio frequency noise suppressor and method |
US11804452B2 (en) * | 2021-07-30 | 2023-10-31 | Globalfoundries U.S. Inc. | Pic structure having barrier surrounding opening for optical element to prevent stress damage |
US11676892B2 (en) | 2021-09-15 | 2023-06-13 | International Business Machines Corporation | Three-dimensional metal-insulator-metal capacitor embedded in seal structure |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7453128B2 (en) * | 2003-11-10 | 2008-11-18 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
US7635650B2 (en) * | 2006-04-14 | 2009-12-22 | Sony Corporation | Prevention of plasma induced damage arising from etching of crack stop trenches in multi-layered low-k semiconductor devices |
US7868455B2 (en) * | 2007-11-01 | 2011-01-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Solving via-misalignment issues in interconnect structures having air-gaps |
JP4825778B2 (ja) * | 2007-11-16 | 2011-11-30 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
US8053902B2 (en) * | 2008-12-02 | 2011-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation structure for protecting dielectric layers from degradation |
US8859390B2 (en) * | 2010-02-05 | 2014-10-14 | International Business Machines Corporation | Structure and method for making crack stop for 3D integrated circuits |
TWI467695B (zh) * | 2011-03-24 | 2015-01-01 | Sony Corp | 半導體裝置及其製造方法 |
US8896102B2 (en) * | 2013-01-22 | 2014-11-25 | Freescale Semiconductor, Inc. | Die edge sealing structures and related fabrication methods |
-
2017
- 2017-02-27 US US15/443,276 patent/US10062748B1/en active Active
- 2017-05-03 TW TW106114621A patent/TWI696249B/zh active
-
2018
- 2018-02-13 CN CN201810150657.4A patent/CN108511386B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US20180248001A1 (en) | 2018-08-30 |
TWI696249B (zh) | 2020-06-11 |
CN108511386A (zh) | 2018-09-07 |
US10062748B1 (en) | 2018-08-28 |
TW201841311A (zh) | 2018-11-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN108511386B (zh) | 分段式防护环及芯片边缘密封件 | |
US11398405B2 (en) | Method and apparatus for back end of line semiconductor device processing | |
KR101476544B1 (ko) | 개선된 비아 랜딩 프로파일을 위한 신규한 패터닝 방법 | |
US8242604B2 (en) | Coaxial through-silicon via | |
US8796852B2 (en) | 3D integrated circuit structure and method for manufacturing the same | |
US8048761B2 (en) | Fabricating method for crack stop structure enhancement of integrated circuit seal ring | |
US7544602B2 (en) | Method and structure for ultra narrow crack stop for multilevel semiconductor device | |
US20170040216A1 (en) | Damascene wires with top via structures | |
KR101645825B1 (ko) | 반도체 디바이스 및 그 제조 방법 | |
EP3651188B1 (en) | A method for contacting a buried interconnect rail from the back side of an ic | |
US10636698B2 (en) | Skip via structures | |
TWI671852B (zh) | 用於共用基板的電路的隔離結構 | |
US5960316A (en) | Method to fabricate unlanded vias with a low dielectric constant material as an intraline dielectric | |
TW201909362A (zh) | 用於著陸在不同接觸區階層的接觸方案 | |
US11581398B2 (en) | Method of fabrication of an integrated spiral inductor having low substrate loss | |
KR20230145955A (ko) | 금속 상에 랜딩되는 배면 또는 전면 기판 관통 비아(tsv) | |
KR100495288B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US10170540B2 (en) | Capacitors | |
CN108122781B (zh) | 半导体结构及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20210316 Address after: California, USA Applicant after: Lattice chip (USA) integrated circuit technology Co.,Ltd. Address before: Greater Cayman Islands, British Cayman Islands Applicant before: GLOBALFOUNDRIES INC. |
|
TA01 | Transfer of patent application right | ||
GR01 | Patent grant | ||
GR01 | Patent grant |