CN103378033A - 衬底通孔及其形成方法 - Google Patents

衬底通孔及其形成方法 Download PDF

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CN103378033A
CN103378033A CN2012105582955A CN201210558295A CN103378033A CN 103378033 A CN103378033 A CN 103378033A CN 2012105582955 A CN2012105582955 A CN 2012105582955A CN 201210558295 A CN201210558295 A CN 201210558295A CN 103378033 A CN103378033 A CN 103378033A
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陈明发
王宇洋
詹森博
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种器件包括半导体衬底和金属氧化物半导体(MOS)晶体管。MOS晶体管包括位于半导体衬底上方的栅电极和位于栅电极旁边的源极/漏极区。源极/漏极接触塞包括下部和位于下部上方的上部，其中源极/漏极接触塞设置在源极/漏极区上方并且与其电连接。栅极接触塞设置在栅电极上方并且与其电连接，其中栅极接触塞的顶面与源极/漏极接触塞的上部的顶面齐平。衬底通孔(TSV)延伸进半导体衬底。TSV的顶面与栅极接触塞和栅电极之间的界面基本上齐平。本发明提供衬底通孔及其形成方法。

Description

衬底通孔及其形成方法
技术领域
本发明涉及衬底通孔及其形成方法。
背景技术
自从集成电路发明以来，由于各种电子元件(例如，晶体管、二极管、电阻器、电容器等)的集成密度不断提高，半导体产业经历了持续快速的发展。大多数情况下，集成密度的提高来源于最小部件尺寸的不断减小，允许更多的元件在给定的芯片面积上集成。
本质上来说，这些集成方面的改进基本上是二维的(2D)，因为被集成元件占用的体积基本上位于半导体晶圆的表面上。尽管光刻方面的明显改进导致了2D集成电路形成方面的显著改进，但二维所能实现的密度还是存在物理限制。限制之一是制造这些元件所需的最小尺寸。而且，当把更多的器件置于单个晶片内时，需要更复杂的设计。
另一个限制是，随着器件数目的增加，所带来的器件之间的互连的数目和长度的大幅增加。当互连的数目和长度增加时，电路RC延迟和能耗都增加。
在解决上述限制的努力中，通常使用三维集成电路(3DIC)和堆叠的管芯。硅通孔(TSV，或有时也被称为衬底通孔)常在3DIC和堆叠的管芯中用于连接管芯。在这种情况下，TSV用于将管芯上的集成电路连接至管芯的背面。此外，TSV还用于提供将集成电路中的地线连接至管芯的背面(其通常被接地铝膜覆盖)的短接地路径。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种器件，包括：半导体衬底；金属氧化物半导体(MOS)晶体管，包括：栅电极，位于所述半导体衬底上方；和源极/漏极区，位于所述栅电极的旁边；源极/漏极接触塞，包括下部和位于所述下部上方的上部，其中，所述源极/漏极接触塞位于所述源极/漏极区上方并与所述源极/漏极区电连接；栅极接触塞，位于所述栅电极上方并与所述栅电极电连接，所述栅极接触塞的顶面与所述源极/漏极接触塞的上部的顶面齐平；以及衬底通孔(TSV)，延伸进所述半导体衬底，所述TSV的顶面与所述栅极接触塞和所述栅电极之间的界面基本上齐平。
在上述器件中，还包括：位于所述半导体衬底上方的层间电介质，其中，所述栅电极和所述源极/漏极接触塞的下部包括位于所述层间电介质中的部分；以及位于所述层间电介质上方并与所述层间电介质接触的蚀刻停止层，其中，所述TSV的顶面与所述蚀刻停止层接触。
在上述器件中，还包括：位于所述半导体衬底上方的层间电介质，其中，所述栅电极和所述源极/漏极接触塞的下部包括位于所述层间电介质中的部分；以及位于所述层间电介质上方并与所述层间电介质接触的蚀刻停止层，其中，所述TSV的顶面与所述蚀刻停止层接触，其中，所述栅极接触塞和所述源极/漏极接触塞的上部穿透所述蚀刻停止层。
在上述器件中，还包括通孔和位于所述通孔上方的金属线，所述通孔和所述金属线形成双镶嵌结构，并且所述通孔的底面与所述栅极接触塞的顶面接触。
在上述器件中，还包括通孔和位于所述通孔上方的金属线，所述通孔和所述金属线形成双镶嵌结构，并且所述通孔的底面与所述栅极接触塞的顶面接触，还包括：位于所述栅电极上方的层间电介质，其中，所述源极/漏极接触塞的上部包括设置在所述层间电介质中的部分；以及位于所述层间电介质上方的蚀刻停止层，其中，所述通孔延伸进所述蚀刻停止层。
在上述器件中，其中，所述源极/漏极接触塞的上部和下部具有明显的界面。
在上述器件中，还包括位于所述TSV上方并与所述TSV接触的TSV接触塞，所述TSV接触塞与所述栅电极接触塞处于同一平面。
在上述器件中，其中，所述TSV包括：与所述半导体衬底接触的绝缘层；位于所述绝缘层上方的扩散阻挡层；以及位于所述扩散阻挡层上方的金属材料，其中，所述绝缘层、所述扩散阻挡层和所述金属材料中的每一个都从所述界面延伸进所述半导体衬底。
根据本发明的另一方面，还提供了一种器件，包括：半导体衬底；金属氧化物半导体(MOS)晶体管，包括：栅电极，位于所述半导体衬底上方；和源极/漏极区，位于所述栅电极的旁边；源极/漏极接触塞，包括下部和位于所述下部上方的上部，所述源极/漏极接触塞位于所述源极/漏极区上方并与所述源极/漏极区电连接；栅极接触塞，位于所述栅电极上方并与所述栅电极电连接，所述栅极接触塞的顶面与所述源极/漏极接触塞的上部的顶面齐平；衬底通孔(TSV)，延伸进所述半导体衬底，所述TSV的顶面与所述源极/漏极接触塞的顶面基本上齐平；第一蚀刻停止层，位于所述TSV上方并与所述TSV接触；以及第一通孔和位于所述第一通孔上方的第一金属线，所述第一通孔和所述第一金属线形成第一双镶嵌结构，其中，所述第一通孔的底面与所述栅极接触塞的顶面接触，并且所述第一通孔延伸进所述第一蚀刻停止层。
在上述器件中，还包括：位于所述半导体衬底上方的层间电介质，其中，所述栅电极和所述源极/漏极接触塞的下部包括位于所述层间电介质内的部分；以及位于所述层间电介质上方并与所述层间电介质接触的第二蚀刻停止层，其中，所述源极/漏极接触塞的上部和下部具有与所述第二蚀刻停止层的底面基本上齐平的界面。
在上述器件中，还包括：位于所述半导体衬底上方的层间电介质，其中，所述栅电极和所述源极/漏极接触塞的下部包括位于所述层间电介质内的部分；以及位于所述层间电介质上方并与所述层间电介质接触的第二蚀刻停止层，其中，所述源极/漏极接触塞的上部和下部具有与所述第二蚀刻停止层的底面基本上齐平的界面，其中，所述栅极接触塞和所述源极/漏极接触塞的上部穿透所述第二蚀刻终止层。
在上述器件中，其中，所述源极/漏极接触塞的上部和下部形成明显的界面。
在上述器件中，还包括第二通孔和位于所述第二通孔上方的第二金属线，所述第二通孔和所述第二金属线形成第二双镶嵌结构，而且所述第二通孔的底面与所述TSV的顶面接触。
在上述器件中，其中，所述TSV包括：与所述半导体衬底接触的绝缘层；位于所述绝缘层上方的扩散阻挡层；以及位于所述扩散阻挡层上方的金属材料，其中，所述绝缘层、所述扩散阻挡层和所述金属材料中的每一个均从所述栅极接触塞的顶面延伸进所述半导体衬底。
根据本发明的又一方面，还提供了一种器件，包括：半导体衬底；金属氧化物半导体(MOS)晶体管，包括：栅电极，位于所述半导体衬底上方；和源极/漏极区，位于所述栅电极的旁边；源极/漏极接触塞，包括下部和位于所述下部上方的上部，所述源极/漏极接触塞位于所述源极/漏极区上方并与所述源极/漏极区电连接；位于所述栅电极上方并与所述栅电极电连接的栅极接触塞，所述栅极接触塞的顶面与所述源极/漏极接触塞的上部的顶面齐平；第一通孔和位于所述第一通孔上方的第一金属线，其中，所述第一通孔和所述第一金属线形成第一双镶嵌结构，所述第一通孔的底面与所述栅极接触塞的顶面接触；以及延伸进所述半导体衬底的衬底通孔(TSV)，所述TSV的顶面与所述第一金属线的顶面基本上齐平。
在上述器件中，还包括：位于所述半导体衬底上方的层间电介质，其中，所述栅电极和所述源极/漏极接触塞的下部包括位于所述层间电介质中的部分；以及位于所述层间电介质上方并与所述层间电介质接触的蚀刻停止层，其中，所述源极/漏极接触塞的上部和下部具有与所述蚀刻停止层的底面基本上齐平的界面。
在上述器件中，还包括：位于所述半导体衬底上方的层间电介质，其中，所述栅电极和所述源极/漏极接触塞的下部包括位于所述层间电介质中的部分；以及位于所述层间电介质上方并与所述层间电介质接触的蚀刻停止层，其中，所述源极/漏极接触塞的上部和下部具有与所述蚀刻停止层的底面基本上齐平的界面，其中，所述源极/漏极接触塞的上部延伸穿透所述蚀刻停止层。
在上述器件中，其中，所述源极/漏极接触塞的上部和下部形成明显的界面。
在上述器件中，其中，所述TSV包括：与所述半导体衬底接触的绝缘层；位于所述绝缘层上方的扩散阻挡层；以及位于所述扩散阻挡层上方的金属材料，其中，所述绝缘层、所述扩散阻挡层和所述金属材料中的每一个均从所述第一金属线的顶面延伸进所述半导体衬底。
在上述器件中，还包括位于所述栅极接触塞和所述源极/漏极接触塞上方的蚀刻停止层，其中，所述蚀刻停止层的底面与所述栅极接触塞和所述源极/漏极接触塞的顶面基本上齐平。
附图说明
为了更全面理解本实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1至图9是根据一些示例性实施例在制造衬底通孔(TSV)的中间阶段的截面图；
图10示出根据一些可选的示例性实施例的TSV和MOS器件的截面图；
图11示出形成图10中示出的结构的中间阶段；以及
图12和图13示出根据又一可选的实施例制造TSV和MOS器件的中间阶段的截面图。
具体实施方式
以下详细描述了本发明的实施例的制造和使用。然而，应该理解，本发明的实施例提供了许多可以在各种具体环境中实现的可应用的构思。所论述的具体实施例仅是示例性的，并不用来限制本发明的范围。
根据各个示例性实施例提供了衬底通孔(TSV)及其形成方法。示出了形成TSV的中间阶段。论述了实施例的变化。在各个视图和示例性实施例中，相同的参考标号用于表示相同的元件。
参考图1，提供了晶圆10。晶圆10包括衬底20，其可以包含硅、硅锗、硅碳、砷化镓、III-V族化合物半导体材料等。衬底20可以是块状衬底或绝缘体上半导体(SOI)衬底。在衬底20中形成绝缘区22，其可以是浅沟槽隔离(STI)区。
在衬底20的顶面形成金属氧化物半导体(MOS)器件(晶体管)24。MOS器件24包括栅极电介质25、栅电极26和位于栅极电介质25和栅电极26的侧壁上的栅极间隔件27。根据相应的MOS器件24的导电类型，源极和漏极区28(在下文中被称为源极/漏极区)可以是衬底20掺杂有p型或n型杂质的部分。源极/漏极区28还可以包括用于对MOS器件24的沟道区施加应力的应力源，其中应力源可以是硅锗应力源或硅碳应力源。尽管未示出，但源极/漏极硅化物可以作为源极/漏极区28的顶部和/或栅电极26的顶部形成。栅电极26可以是由金属或(一种或多种)金属合金形成的金属栅极，然而栅电极26还可以由多晶硅、金属硅化物等形成。栅电极26形成在层间电介质(ILD，在下文中被称为ILD0)30中，其中ILD030可以由诸如磷硅玻璃(PSG)、硼硅玻璃(BSG)、掺硼磷硅玻璃(BPSG)、原硅酸四乙酯(TEOS)氧化物等的氧化物形成。在一些实施例中，采用后栅极方法形成栅电极26，然而可以采用先栅极方法。栅电极26的顶面可以与ILD030的顶面齐平。
接触塞32(有时被称为M0OD 1或MD1)形成在ILD030中，并且与源极/漏极区28重叠且电连接。在一些实施例中，MD132的顶面、栅电极26的顶面和/或ILD030的顶面相互齐平。
参考图2，在ILD0 30、栅电极26和MD1 32上方形成化学机械抛光(CMP)停止层38，CMP停止层38可以包含氮化硅、碳氧化硅等。接下来，在CMP停止层38上方形成光刻胶40，然后使其图案化。MOS器件24受到光刻胶40的剩余部分的保护。然后实施图案化以蚀刻CMP停止层38、ILD0 30和衬底20以形成TSV开口42。在一些实施例中，TSV开口42延伸进STI区22之一(标记为22A)的中心部分，从而STI区22的剩余部分环绕在TSV开口42的周围。在蚀刻过程中，STI区22A可以用作蚀刻停止层。可选地，TSV开口42不穿透任何STI区22。TSV开口42在衬底20的顶面和底面之间的中间位置终止。
参考图3，例如通过灰化步骤去除光刻胶40。接下来，如图4所示，绝缘层44在CMP停止层38的顶面上形成，并延伸进TSV开口42。绝缘层44可以是基本上共形层，其中绝缘层44的横向部分和纵向部分具有基本上相同的厚度。绝缘层44可以包含氧化硅、氮化硅、碳化硅、氮氧化硅、它们的组合或它们的多层。接下来，覆盖形成扩散阻挡层46(还作为粘着层)以覆盖TSV开口42的侧壁和底部。举例来说，扩散阻挡层46可以包含钛、氮化钛、钽、氮化钽以及它们的组合，并且可以采用物理汽相沉积(PVD)形成。接下来，可以在扩散阻挡层46上覆盖形成薄晶种层(未示出)。晶种层可以包含铜或铜合金，并且也可以包含诸如钨、银、金、铝以及它们的组合的金属。在一些实施例中，通过PVD形成晶种层。在其它实施例中，可以使用诸如电镀或无电电镀的其它方法。
然后将金属材料48填充到TSV开口42内，从而在TSV开口42中形成TSV 50。在各个实施例中，金属材料48包含铜或铜合金，然而也可以使用诸如铝、银、金、以及它们的组合的其他金属。举例来说，形成方法可以包括电镀。填充金属材料48直到金属材料48的顶面高于CMP停止层38的顶面。
图5示出CMP步骤用于去除多余的金属材料48。在一些实施例中，采用基本上不侵蚀CMP停止层38的研磨液实施CMP，因此CMP在CMP停止层38上终止。然后实施进一步CMP，例如采用侵蚀CMP停止层38的研磨液。因此，在一些实施例中，暴露出MD132和栅电极26的顶面。在得到的结构中，TSV50的顶面与MD 132、ILD030的顶面齐平，并且可能与栅电极26的顶面齐平。
参考图6，形成接触蚀刻停止层(CESL)52和ILD1 54。在一些实施例中，CESL 52由氮化硅或其他介电材料形成。ILD1 54可以包含碳氧化硅、TEOS氧化物等。
接下来，图7示出栅极接触塞56、源极/漏极接触塞58(由于它们与MD 132重叠且连接，有时被称为M0OD2或MD2)的形成。由于栅极接触塞56与栅电极26重叠且连接，栅极接触塞56可选地被称为M0多晶硅56，其有时包含多晶硅。此外，形成TSV接触塞58’以重叠且连接至TSV 50，而且用作电连接至TSV 50。在ILD 154中形成接触塞56、58和58’，其中接触塞56电连接至(可以物理接触)栅电极26。源极/漏极接触塞58电连接至(可以物理接触)M0 OD1 32。TSV接触塞58’可以穿透CESL 52以接触TSV50。接触塞56、58和58’的形成工艺可以包括在ILD1 54和CESL52中形成开口、用粘附/阻挡层和诸如钨或铜的金属材料填充开口以及实施CMP。
可以看到，每个MD1 32和各自上覆的MD2 58一起形成源极/漏极接触塞。由于MD1 32和MD258在不同的工艺步骤中形成，所以MD1 32和MD2 58之间存在明显的界面。此外，MD132和MD258的边缘不是连续且光滑的。
在随后的工艺中，如图8所示，形成蚀刻停止层60、M0通孔62和金属线64。金属线64都被称为底金属层M1。在介电层66中形成M0通孔62和金属线64，其中介电层66可以由低k介电材料(例如k值小于约3.0或小于约2.5)形成。介电层66可选地被称为金属间介电(IMD)层或IMD 1。
在一些实施例中，M0通孔62和金属线64作为双镶嵌结构形成，因此在M0通孔62和相应上覆的金属线64之间未形成明显的界面。双镶嵌结构可以包括扩散阻挡层63(诸如Ti/TiN/Ta/TaN)和位于扩散阻挡层上方的含铜材料。当M0通孔62和金属线64形成双镶嵌结构时，扩散阻挡层未介入M0通孔62和上覆的金属线64之间。在可选的实施例中，可以采用单镶嵌工艺形成M0通孔62，也可以使用单镶嵌工艺形成金属线64。在又一其他实施例中，未形成M0通孔62，而金属线64与接触塞56和58接触。在随后的工艺中，可以在金属线64上方形成更多的金属层(未示出)。然后可以形成蚀刻停止层68，并可以在更多的介电层中形成进一步的金属线和通孔(未示出，用点表示)以电连接至TSV 50和接触塞56和58。
图9示出连接至TSV 50的背面结构的形成。在一些示例性形成工艺中，从背面(图8和图9中向下的面)研磨衬底20直到暴露出TSV 50。然后形成再分布线/焊盘70以电连接至TSV 50。可以在再分布线/焊盘70上形成电连接件72。电连接件72可以是焊球、铜柱或包括铜柱和焊料盖顶的复合连接件。
图10至图13示出根据可选的实施例的TSV 50的形成。除非另有说明，这些实施例中元件的材料和形成方法基本上与相似的元件(由图1至图9中示出的实施例中的相同参考标号表示)一样。因而可以在图1至图9示出的实施例的论述中得到图10至图13中示出的相同元件的详情。
参考图10，TSV 50的顶面与M0多晶硅56和MD2 58齐平。该形成工艺与形成图8中的TSV 50的工艺类似，除了TSV50的形成在M0多晶硅56和MD2 58形成之后和在蚀刻停止层60形成之前开始。例如，图11示出在形成TSV 50的中间阶段的截面图。在这些示例性实施例中，在ILD 154、M0多晶硅56和MD2 58形成之后，形成CMP停止层38，然后形成TSV开口42。接下来，形成绝缘层、扩散阻挡层和晶种层(未示出)。然后形成金属材料以填充剩余的TSV开口42。可以参考图4中示出的实施例得到形成绝缘层、扩散阻挡层、晶种层和金属材料的工艺步骤和材料。然后实施CMP，从而形成图10中示出的TSV 50。接下来，还如图10所示，形成包括蚀刻停止层60、M0通孔62和金属线64的上覆正面结构。在TSV50上方并与其接触形成一些M0通孔62和金属线64。然后从衬底20的背面实施背面研磨以暴露出TSV 50，接着形成再分布线/焊盘70和电连接件72。
图12和图13示出根据又一可选的实施例形成TSV 50的中间阶段的截面图。在这些实施例中，采用与图2至图5基本上相同的方法，在金属线64形成之后形成TSV 50。然后形成蚀刻停止层68。因此，TSV 50的顶面与金属线64的顶面齐平，其可以与下面的通孔0 62形成双镶嵌结构。可以在图12和图13示出的结构上方形成分别与金属线64、通孔62和介电层66类似的更多的金属线、通孔和介电层。
根据实施例，一种器件包括半导体衬底和MOS晶体管。MOS晶体管包括位于半导体衬底上方的栅电极，和位于栅电极旁边的源极/漏极区。源极/漏极接触塞包括下部和位于下部上方的上部，其中源极/漏极接触塞设置在源极/漏极区上方并且与源极/漏极区电连接。栅极接触塞设置在栅电极上方并且与栅电极电连接，其中栅极接触塞的顶面与源极/漏极接触塞的上部的顶面齐平。TSV延伸进半导体衬底。TSV的顶面与栅极接触塞与栅电极之间的界面基本上齐平。
根据其它实施例，一种器件包括半导体衬底和MOS晶体管。MOS晶体管包括位于半导体衬底上方的栅电极，和位于栅电极旁边的源极/漏极区。源极/漏极接触塞包括下部和位于下部上方的上部，其中源极/漏极接触塞位于源极/漏极区上方并且与源极/漏极区电连接。栅极接触塞设置在栅电极上方并且与栅电极电连接，其中栅极接触塞的顶面与源极/漏极接触塞的上部的顶面齐平。TSV延伸进半导体衬底，其中TSV的顶面与源极/漏极接触塞的顶面基本上齐平。蚀刻停止层设置在TSV上方并且与TSV接触。该器件还包括通孔和位于通孔上方的金属线，其中通孔和金属线形成双镶嵌结构。通孔的底面与栅极接触塞的顶面接触。通孔延伸进蚀刻停止层。
根据又一其他实施例，一种器件包括半导体衬底和MOS晶体管。MOS晶体管包括位于半导体衬底上方的栅电极，和位于栅电极旁边的源极/漏极区。源极/漏极接触塞包括下部和位于下部上方的上部，其中源极/漏极接触塞位于源极/漏极区上方并且与源极/漏极区电连接。栅极接触塞设置在栅电极上方并且与栅电极电连接，其中栅极接触塞的顶面与源极/漏极接触塞的上部的顶面齐平。该器件还包括通孔和位于通孔上方的金属线，其中通孔和金属线形成双镶嵌结构。通孔的底面与栅极接触塞的顶面接触。TSV延伸进半导体衬底，其中TSV的顶面与金属线的顶面基本上齐平。
尽管已详细地描述了本发明的实施例及其优势，但应该理解，可以在不背离所附权利要求所限定的本发明主旨和范围的情况下，做各种不同的改变、替换或更改。而且，本申请的范围并不仅限于本说明书中所描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域的普通技术人员根据本发明的发明内容将很容易理解，根据本发明可以利用现有的或今后开发的用于执行与根据本文所述相应实施例基本上相同的功能或获得基本上相同结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求应该在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (10)

1.一种器件，包括：
半导体衬底；
金属氧化物半导体(MOS)晶体管，包括：
栅电极，位于所述半导体衬底上方；和
源极/漏极区，位于所述栅电极的旁边；
源极/漏极接触塞，包括下部和位于所述下部上方的上部，其中，所述源极/漏极接触塞位于所述源极/漏极区上方并与所述源极/漏极区电连接；
栅极接触塞，位于所述栅电极上方并与所述栅电极电连接，所述栅极接触塞的顶面与所述源极/漏极接触塞的上部的顶面齐平；以及
衬底通孔(TSV)，延伸进所述半导体衬底，所述TSV的顶面与所述栅极接触塞和所述栅电极之间的界面基本上齐平。
2.根据权利要求1所述的器件，还包括：
位于所述半导体衬底上方的层间电介质，其中，所述栅电极和所述源极/漏极接触塞的下部包括位于所述层间电介质中的部分；以及
位于所述层间电介质上方并与所述层间电介质接触的蚀刻停止层，其中，所述TSV的顶面与所述蚀刻停止层接触。
3.根据权利要求2所述的器件，其中，所述栅极接触塞和所述源极/漏极接触塞的上部穿透所述蚀刻停止层。
4.根据权利要求1所述的器件，还包括通孔和位于所述通孔上方的金属线，所述通孔和所述金属线形成双镶嵌结构，并且所述通孔的底面与所述栅极接触塞的顶面接触。
5.一种器件，包括：
半导体衬底；
金属氧化物半导体(MOS)晶体管，包括：
栅电极，位于所述半导体衬底上方；和
源极/漏极区，位于所述栅电极的旁边；
源极/漏极接触塞，包括下部和位于所述下部上方的上部，所述源极/漏极接触塞位于所述源极/漏极区上方并与所述源极/漏极区电连接；
栅极接触塞，位于所述栅电极上方并与所述栅电极电连接，所述栅极接触塞的顶面与所述源极/漏极接触塞的上部的顶面齐平；
衬底通孔(TSV)，延伸进所述半导体衬底，所述TSV的顶面与所述源极/漏极接触塞的顶面基本上齐平；
第一蚀刻停止层，位于所述TSV上方并与所述TSV接触；以及
第一通孔和位于所述第一通孔上方的第一金属线，所述第一通孔和所述第一金属线形成第一双镶嵌结构，其中，所述第一通孔的底面与所述栅极接触塞的顶面接触，并且所述第一通孔延伸进所述第一蚀刻停止层。
6.根据权利要求5所述的器件，还包括：
位于所述半导体衬底上方的层间电介质，其中，所述栅电极和所述源极/漏极接触塞的下部包括位于所述层间电介质内的部分；以及
位于所述层间电介质上方并与所述层间电介质接触的第二蚀刻停止层，其中，所述源极/漏极接触塞的上部和下部具有与所述第二蚀刻停止层的底面基本上齐平的界面。
7.根据权利要求6所述的器件，其中，所述栅极接触塞和所述源极/漏极接触塞的上部穿透所述第二蚀刻终止层。
8.根据权利要求5所述的器件，其中，所述源极/漏极接触塞的上部和下部形成明显的界面。
9.一种器件，包括：
半导体衬底；
金属氧化物半导体(MOS)晶体管，包括：
栅电极，位于所述半导体衬底上方；和
源极/漏极区，位于所述栅电极的旁边；
源极/漏极接触塞，包括下部和位于所述下部上方的上部，所述源极/漏极接触塞位于所述源极/漏极区上方并与所述源极/漏极区电连接；
位于所述栅电极上方并与所述栅电极电连接的栅极接触塞，所述栅极接触塞的顶面与所述源极/漏极接触塞的上部的顶面齐平；
第一通孔和位于所述第一通孔上方的第一金属线，其中，所述第一通孔和所述第一金属线形成第一双镶嵌结构，所述第一通孔的底面与所述栅极接触塞的顶面接触；以及
延伸进所述半导体衬底的衬底通孔(TSV)，所述TSV的顶面与所述第一金属线的顶面基本上齐平。
10.根据权利要求9所述的器件，还包括：
位于所述半导体衬底上方的层间电介质，其中，所述栅电极和所述源极/漏极接触塞的下部包括位于所述层间电介质中的部分；以及
位于所述层间电介质上方并与所述层间电介质接触的蚀刻停止层，其中，所述源极/漏极接触塞的上部和下部具有与所述蚀刻停止层的底面基本上齐平的界面。
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