WO2022000433A1 - 一种用于三维封装的soi有源转接板及其制备方法 - Google Patents

一种用于三维封装的soi有源转接板及其制备方法 Download PDF

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WO2022000433A1
WO2022000433A1 PCT/CN2020/099978 CN2020099978W WO2022000433A1 WO 2022000433 A1 WO2022000433 A1 WO 2022000433A1 CN 2020099978 W CN2020099978 W CN 2020099978W WO 2022000433 A1 WO2022000433 A1 WO 2022000433A1
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soi
insulating medium
layer
copper
nmos transistor
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PCT/CN2020/099978
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English (en)
French (fr)
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朱宝
陈琳
孙清清
张卫
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复旦大学
上海集成电路制造创新中心有限公司
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Priority to US17/052,857 priority Critical patent/US11881442B2/en
Publication of WO2022000433A1 publication Critical patent/WO2022000433A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Definitions

  • the invention belongs to the field of integrated circuit packaging, and in particular relates to an SOI active switching board for three-dimensional packaging and a preparation method thereof.
  • microelectronic packaging technology has gradually become the main factor restricting the development of semiconductor technology.
  • semiconductor technology In order to achieve high density of electronic packaging, obtain better performance and lower overall cost, technicians have developed a series of advanced packaging technologies.
  • the three-dimensional system-in-package technology has good electrical performance and high reliability, and can achieve high packaging density at the same time, and is widely used in various high-speed circuits and miniaturized systems.
  • TSV interposer technology is a new technology for stacking chips in three-dimensional integrated circuits to achieve interconnection. Layer, RDL for short) to realize the electrical interconnection between different chips.
  • TSV adapter board technology is divided into two technologies: active adapter board and passive adapter board. Among them, the active adapter board has active components, and the passive adapter board lacks active components.
  • TSV interposer technology can make the chips stack with the highest density in the three-dimensional direction, the shortest interconnection between chips, the smallest external size, and greatly improve the performance of chip speed and low power consumption. It is the most attractive electronic packaging technology at present. An eye-catching technique.
  • CMOS devices such as CMOS inverters
  • latch-up effects are prone to occur, thereby affecting device performance.
  • an SOI active transition board for three-dimensional packaging comprising: an SOI substrate; a CMOS inverter, including PMOS transistors and NMOS transistors, formed on the SOI substrate; SOI through holes , formed between the PMOS transistor and the NMOS transistor, through the SOI substrate; a first insulating medium, covering the PMOS transistor and the NMOS transistor; a second insulating medium, formed in the SOI through hole sidewalls and the surface of the first insulating medium; source-drain gate through holes, respectively formed on the source, drain and gate of the PMOS transistor and the NMOS transistor, penetrating the first insulating medium and the The second insulating medium; the sidewall of the SOI through hole is formed with a copper diffusion barrier layer and a seed layer, the inside is filled with copper, the top is formed with an adhesive layer/seed laminated layer film and micro-bumps, and the bottom is formed with an adhesive layer layer/seed stack layer film and C4 bump
  • the first insulating medium and the second insulating medium are silicon dioxide, silicon nitride, SiOCH or SiOCFH.
  • the copper diffusion barrier layer is at least one of TaN, TiN, ZrN, and MnSiO 3 .
  • the seed layer is at least one of Cu, Co, and Ru.
  • the invention also discloses a preparation method of an SOI active switch board for three-dimensional packaging, comprising the following steps: providing an SOI substrate, including a silicon substrate, silicon dioxide and a top layer silicon; preparing a CMOS flip-flop on the surface of the SOI substrate a phase device, including a PMOS transistor and an NMOS transistor; forming a first insulating medium to cover the PMOS transistor and the NMOS transistor; performing photolithography and etching on the area between the PMOS transistor and the NMOS transistor , until part of the silicon substrate is etched; a second insulating medium is formed on the above structure; photolithography, etching removes the first on the source, drain and gate of the PMOS transistor and the NMOS transistor The insulating medium and the second insulating medium are used to form source-drain gate through holes; the copper diffusion barrier layer, seed layer and copper are formed, and the copper material, seed layer and copper diffusion barrier layer above the second insulating medium are removed by chemical mechanical polishing process ; Form the top adh
  • the first insulating medium and the second insulating medium are silicon dioxide, silicon nitride, SiOCH or SiOCFH.
  • the copper diffusion barrier layer is at least one of TaN, TiN, ZrN, and MnSiO 3 .
  • the seed layer is at least one of Cu, Co, and Ru.
  • the present invention adopts SOI as the substrate for preparing the active switching board, and prepares the CMOS inverter on the top layer silicon of the SOI, so that the short channel effect and the latch-up effect can be suppressed.
  • a through-hole structure is formed by etching on the SOI substrate between the PMOS and NMOS transistors of the CMOS inverter.
  • the through-hole structure can be used as a conductive channel connecting the chips in the vertical direction on the one hand, and a PMOS transistor on the other hand.
  • the electrical isolation layer between the NMOS transistor and the NMOS transistor acts like a short trench isolation (STI).
  • FIG. 1 is a flow chart of a method for preparing an SOI active interposer for three-dimensional packaging.
  • 2 to 13 are schematic structural diagrams of each step of a method for preparing an SOI active interposer for three-dimensional packaging.
  • FIG. 1 is a flow chart of a method for preparing an SOI active interposer for 3D packaging
  • FIGS. 2 to 13 show structural schematic diagrams of each step of the method for preparing an SOI active interposer for 3D packaging. As shown in Figure 1, the specific preparation steps are:
  • Step S1 fabricating a CMOS inverter on the surface of the SOI substrate.
  • the single crystal silicon substrate 200 and the top layer single crystal silicon 202 are both p-type doped SOI as the base, and the obtained structure is shown in FIG. 2 .
  • the material between the silicon substrate 200 and the top layer silicon 202 is silicon dioxide 201, and the thickness of the top layer silicon 202 ranges from 100 to 400 nm.
  • a CMOS inverter is fabricated on the surface of the top layer silicon 202 by using standard integrated circuit processes such as photolithography, etching, ion implantation, and sputtering, and the obtained structure is shown in FIG. 3 .
  • the device structure enclosed by the dotted line is a PMOS transistor 203 and an NMOS transistor 204, and the PMOS transistor 203 and the NMOS transistor 204 form a CMOS inverter.
  • CMOS inverter In this embodiment, p-type doping is used for both the silicon substrate and the top layer silicon, but the present invention is not limited to this, and n-type doping can also be used.
  • SOI SOI as the substrate for preparing the active interposer, and fabricating a CMOS inverter on the top silicon of the SOI, the short-channel effect and the latch-up effect can be suppressed.
  • Step S2 etching the SOI substrate to form an SOI via structure.
  • a layer of silicon dioxide is grown on the surface of the above structure by chemical vapor deposition process as the first insulating medium 205, which can completely cover the CMOS inverter.
  • the obtained structure is shown in FIG. 4 .
  • the photoresist is spin-coated and the pattern of the SOI via structure is defined by exposure and development processes.
  • a deep plasma etching (DRIE) process is used to etch the SOI region between the PMOS and NMOS transistors until a part of the silicon substrate 200 is etched away.
  • the photoresist is removed by dissolving or ashing in a solvent, and the resulting structure is shown in FIG. 5 .
  • DRIE deep plasma etching
  • the via structure can be used as a conductive channel connecting chips in the vertical direction, and on the other hand, it can be used as an electrical isolation layer between the PMOS transistor and the NMOS transistor, which plays a role similar to short trench isolation (STI).
  • the plasma used to etch the silicon dioxide 202 and the first insulating medium 205 can be selected from CF 4 , CHF 3 , CF 4 /CHF 3 , CF 4 /O 2 or CHF 3 /O 2 , and the top layer silicon 203 is etched.
  • the silicon substrate 200 may select at least one of CF 4 and SF 6 .
  • Step S3 forming a via structure on the source, drain and gate of the CMOS inverter.
  • a layer of silicon dioxide is grown on the surface of the structure by chemical vapor deposition as the second insulating medium 206 with a thickness ranging from 200 to 500 nm, so that the surface of the SOI through hole is covered with a second insulating medium 206 .
  • the layer of the second insulating medium can be used as an isolation layer between PMOS transistors and NMOS transistors, and can also be used as an isolation layer between CMOS inverters, silicon substrates and metal interconnects.
  • the resulting structure is shown in FIG. 6 .
  • the photoresist is spin-coated and the through-hole patterns of the source, drain and gate of the CMOS inverter are defined through exposure and development processes.
  • the DRIE process is used to etch the first insulating medium 205 and the second insulating medium 206 until the source electrode, the drain electrode and the gate electrode are exposed, and the obtained structure is shown in FIG. 7 .
  • silicon dioxide is used as the insulating medium, but the present invention is not limited to this, and silicon dioxide, silicon nitride, low dielectric constant materials (such as SiOCH, SiOCFH) and the like can be selected.
  • Step S4 depositing a copper diffusion barrier layer, a seed crystal layer and electroplating copper.
  • a TaN film and a Cu film are sequentially grown inside the SOI via and the source-drain gate via by physical vapor deposition as the copper diffusion barrier layer 207 and the seed layer 208, respectively.
  • the resulting structure is shown in FIG. 8 .
  • the copper film is used as the seed layer, and the copper material 209 is electroplated thereon by the electroplating process.
  • the copper material 209 completely fills the SOI through hole and the source-drain gate through hole, and the obtained structure is shown in FIG. 9 .
  • a chemical mechanical polishing process is used to remove the copper material 209 , the Cu seed layer 208 and the TaN copper diffusion barrier layer 207 above the second insulating medium 206 , and the resulting structure is shown in FIG. 10 .
  • a Cu seed layer may be selected TaN, TiN, ZrN, MnSiO 3 in at least one of a copper diffusion barrier layer, Cu is selected At least one of , Co and Ru is used as the seed layer; the growth mode of the copper diffusion barrier layer and the seed layer can be selected from at least one of physical vapor deposition, chemical vapor deposition and atomic layer deposition.
  • Step S5 performing metal wiring and making contact bumps.
  • a layered film 210 composed of a Ti film and a Cu film is grown on the surface of the above-mentioned structure by a physical vapor deposition method. Among them, Ti film and Cu film are used as adhesion layer and seed layer, respectively.
  • a laminated metal composed of Cu material and Sn material is electroplated on the surface of the adhesion layer/seed laminated layer thin film 210 by an electroplating method as the micro bumps 211 .
  • the unnecessary adhesion layer/seed laminated layer film 210 is removed by photolithography and etching process to ensure that there is no conduction between adjacent micro-bumps, and the obtained structure is shown in FIG. 11 .
  • the silicon substrate on the backside of the SOI substrate is thinned by a combined process of mechanical grinding and chemical mechanical polishing, so that the bottom of the copper material 209 is exposed, and the resulting structure is shown in FIG. 12 .
  • an adhesion layer/seed laminate film 212 and a C4 bump 213 are sequentially fabricated on the bottom of the copper material 209 by the same process as that used to fabricate the micro-bumps 211, and the resulting structure is shown in FIG. 13 .
  • the SOI active interposer for three-dimensional packaging of the present invention includes: an SOI substrate; a CMOS inverter, including a PMOS transistor 203 and an NMOS transistor 204, formed on the SOI substrate; SOI through holes, It is formed between the PMOS transistor 203 and the NMOS transistor 204 and runs through the SOI substrate; the first insulating medium 205 covers the PMOS transistor 203 and the NMOS transistor 204; the second insulating medium 206 is formed on the sidewall of the SOI through hole and the first The surface of the insulating medium 205; the source-drain gate through holes are formed on the source, drain and gate of the PMOS transistor 203 and the NMOS transistor 204, respectively, through the first insulating medium 205 and the second insulating medium 206; the side of the SOI through hole
  • the wall is formed with a copper diffusion barrier layer 207 and a seed layer 208, the interior is filled with copper 209, the top is formed with an adhesion layer/s
  • the first insulating medium and the second insulating medium are silicon dioxide, silicon nitride, SiOCH, SiOCFH, or the like.
  • the copper diffusion barrier layer is at least one of TaN, TiN, ZrN, and MnSiO 3 .
  • the seed layer is at least one of Cu, Co and Ru.

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Abstract

一种用于三维封装的SOI有源转接板及其制备方法。采用SOI作为基底，在SOI的顶层硅(202)上采用标准集成电路制造工艺制备CMOS反相器，可以抑制短沟道效应以及闩锁效应。在CMOS反相器的PMOS晶体管(203)和NMOS晶体管(204)之间的SOI基底上刻蚀出通孔结构，该通孔结构一方面可以作为连接垂直方向芯片之间的导电通道，另一方面可以作为PMOS晶体管(203)和NMOS晶体管(204)之间的电学隔离层。

Description

一种用于三维封装的SOI有源转接板及其制备方法 技术领域
本发明属于集成电路封装领域，具体涉及一种用于三维封装的SOI有源转接板及其制备方法。
背景技术
随着集成电路工艺技术的高速发展，微电子封装技术逐渐成为制约半导体技术发展的主要因素。为了实现电子封装的高密度化，获得更优越的性能和更低的总体成本，技术人员研究出一系列先进的封装技术。其中三维系统级封装技术具有良好的电学性能以及较高的可靠性，同时能实现较高的封装密度，被广泛应用于各种高速电路以及小型化系统中。
硅通孔(Through Silicon Via，简称TSV)转接板技术是三维集成电路中堆叠芯片实现互连的一种新技术，通过在硅圆片上制作出许多垂直互连通孔以及后续重布线(Redistribution Layer，简称RDL)来实现不同芯片之间的电互连。此外，TSV转接板技术又分为有源转接板和无源转接板两种技术，其中有源转接板带有有源器件，无源转接板缺少有源器件。TSV转接板技术能够使芯片在三维方向堆叠的密度最大、芯片之间的互连线最短、外形尺寸最小，并且大大改善芯片速度和低功耗的性能，是目前电子封装技术中最引人注目的一种技术。然而，在基于硅材料的转接板上制备CMOS器件，比如CMOS反相器，很容易出现短沟道效应、闩锁效应，从而影响器件性能。
发明内容
为了解决上述问题，本发明公开一种用于三维封装的SOI有源转接板，包括：SOI基底；CMOS反相器，包括PMOS晶体管和NMOS晶体管，形成在所述SOI基底上；SOI通孔，形成在所述PMOS晶体管和所述NMOS晶体管之间，贯穿所述SOI基底；第一绝缘介质，包覆所述PMOS晶体管和所述NMOS晶体管；第二绝缘介质，形成在所述SOI通孔侧壁和所述第一绝缘介 质表面；源漏栅通孔，分别形成在所述PMOS晶体管和所述NMOS晶体管的源极、漏极和栅极上，贯穿所述第一绝缘介质和所述第二绝缘介质；所述SOI通孔的侧壁形成有铜扩散阻挡层和籽晶层，内部填充有铜，顶部形成有粘附层/种子层叠层薄膜和微凸点，底部形成有粘附层/种子层叠层薄膜和C4凸点；所述源漏栅通孔底部和侧壁形成有铜扩散阻挡层和籽晶层，内部填充有铜，顶部形成有粘附层/种子层叠层薄膜和微凸点。
本发明的用于三维封装的SOI有源转接板中，优选为，所述第一绝缘介质、所述第二绝缘介质为二氧化硅、氮化硅、SiOCH或SiOCFH。
本发明的用于三维封装的SOI有源转接板中，优选为，所述铜扩散阻挡层为TaN、TiN、ZrN、MnSiO 3中的至少一种。
本发明的用于三维封装的SOI有源转接板中，优选为，所述籽晶层为Cu、Co和Ru中的至少一种。
本发明还公开一种用于三维封装的SOI有源转接板的制备方法，包括以下步骤：提供SOI衬底，包括硅衬底，二氧化硅和顶层硅；在SOI衬底表面制备CMOS反相器，包括PMOS晶体管和NMOS晶体管；形成第一绝缘介质，使其包覆所述PMOS晶体管和所述NMOS晶体管；对所述PMOS晶体管和所述NMOS晶体管之间的区域进行光刻、刻蚀，直到刻蚀掉部分所述硅衬底；在上述结构上形成第二绝缘介质；光刻、刻蚀去除所述PMOS晶体管和所述NMOS晶体管的源极、漏极和栅极上的第一绝缘介质和第二绝缘介质，形成源漏栅通孔；形成铜扩散阻挡层、籽晶层和铜，采用化学机械抛光工艺去除第二绝缘介质上方的铜材料、籽晶层和铜扩散阻挡层；形成顶部的粘附层/种子层叠层薄膜和微凸点；采用机械磨削和化学机械抛光联合工艺对SOI基底背面的硅衬底进行减薄，使得铜的底部暴露出来，形成底部的粘附层/种子层叠层薄膜和C4凸点。
本发明的用于三维封装的SOI有源转接板的制备方法中，优选为，所述 第一绝缘介质、所述第二绝缘介质为二氧化硅、氮化硅、SiOCH或SiOCFH。
本发明的用于三维封装的SOI有源转接板的制备方法中，优选为，所述铜扩散阻挡层为TaN、TiN、ZrN、MnSiO 3中的至少一种。
本发明的用于三维封装的SOI有源转接板的制备方法中，优选为，所述籽晶层为Cu、Co和Ru中的至少一种。
本发明采用SOI作为制备有源转接板的基底，在SOI的顶层硅上制备CMOS反相器，从而可以抑制短沟道效应以及闩锁效应。此外，在CMOS反相器的PMOS和NMOS晶体管之间的SOI基底上刻蚀形成通孔结构，该通孔结构一方面可以作为连接垂直方向芯片之间的导电通道，另一方面可以作为PMOS晶体管和NMOS晶体管之间的电学隔离层，起到类似短沟槽隔离(STI)的作用。
附图说明
图1是用于三维封装的SOI有源转接板制备方法的流程图。
图2～图13是用于三维封装的SOI有源转接板制备方法各步骤的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
在本发明的描述中，需要说明的是，术语“上”、“下”、“垂直”“水平”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。 此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
此外，在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。除非在下文中特别指出，器件中的各个部分可以由本领域的技术人员公知的材料构成，或者可以采用将来开发的具有类似功能的材料。
以下结合附图1～13和实施例对本发明的技术方案做进一步的说明。图1是用于三维封装的SOI有源转接板制备方法的流程图，图2～13示出了用于三维封装的SOI有源转接板制备方法各步骤的结构示意图。如图1所示，具体制备步骤为：
步骤S1：在SOI基底表面制备CMOS反相器。选择单晶硅衬底200和顶层单晶硅202均为p型掺杂的SOI作为基底，所得结构如图2所示。其中，位于硅衬底200和顶层硅202之间的材料为二氧化硅201，顶层硅202的厚度范围为100～400nm。接着，采用光刻、刻蚀、离子注入、溅射等集成电路标准工艺在顶层硅202表面制备CMOS反相器，所得结构如图3所示。其中，虚线围住的器件结构为PMOS晶体管203和NMOS晶体管204，PMOS晶体管203和NMOS晶体管204组成CMOS反相器。在本实施方式中，硅衬底和顶层硅均采用p型掺杂，但是本发明不限定于此，也可以采用n型掺杂。采用SOI作为制备有源转接板的基底，在SOI的顶层硅上制备CMOS反相器，可以抑制短沟道效应以及闩锁效应。
步骤S2：刻蚀SOI基底形成SOI通孔结构。首先，采用化学气相沉积工艺在上述结构表面生长一层二氧化硅作为第一绝缘介质205，并能完全包覆CMOS反相器，所得结构如图4所示。然后，旋涂光刻胶并通过曝光和显影工艺定义出SOI通孔结构的图形。接着，采用深度等离子体刻蚀(DRIE)工艺对PMOS和NMOS晶体管之间的SOI区域进行刻蚀，直到刻蚀掉一部分硅衬底200。最后，在溶剂中溶解或灰化去除光刻胶，所得结构如图5所示。该通孔结构一方面可以作为连接垂直方向芯片之间的导电通道，另一方面可以作为PMOS晶体管和NMOS晶体管之间的电学隔离层，起到类似短沟槽隔离(STI)的作用。其中，刻蚀二氧化硅202和第一绝缘介质205所采用的等离子体可以选择CF 4、CHF 3、 CF 4/CHF 3、CF 4/O 2或者CHF 3/O 2，刻蚀顶层硅203和硅衬底200可以选择CF 4、SF 6中的至少一种。
步骤S3：在CMOS反相器的源极、漏极和栅极上形成通孔结构。首先，采用化学气相沉积工艺在上述结构表面生长一层二氧化硅作为第二绝缘介质206，厚度范围为200～500nm，从而SOI通孔表面会覆盖一层第二绝缘介质206。该层第二绝缘介质可以作为PMOS晶体管和NMOS晶体管之间的隔离层，也可以作为CMOS反相器、硅衬底与金属互连线之间的隔离层，所得结构如图6所示。然后，旋涂光刻胶并通过曝光和显影工艺定义出CMOS反相器的源极、漏极和栅极的通孔图形。接着，采用DRIE工艺刻蚀第一绝缘介质205和第二绝缘介质206，直到源极、漏极和栅极暴露出来，所得结构如图7所示。在本发明中采用二氧化硅作为绝缘介质，但是本发明不限定于此，可以选择二氧化硅、氮化硅、低介电常数材料(如SiOCH、SiOCFH)等。
步骤S4：沉积铜扩散阻挡层、籽晶层以及电镀铜。首先采用物理气相沉积方法在SOI通孔和源漏栅通孔的内部依次生长TaN薄膜和Cu薄膜分别作为铜扩散阻挡层207和籽晶层208，所得结构如图8所示。然后，以铜薄膜为籽晶层，采用电镀工艺在其上电镀铜材料209，铜材料209完全填充SOI通孔和源漏栅通孔，所得结构如图9所示。最后，采用化学机械抛光工艺去除第二绝缘介质206上方的铜材料209、Cu籽晶层208和TaN铜扩散阻挡层207，所得结构如图10所示。在本实施方式中采用TaN作为铜扩散阻挡层，Cu作为籽晶层，但是本发明不限定于此，可以选择TaN、TiN、ZrN、MnSiO 3中的至少一种作为铜扩散阻挡层，选择Cu、Co和Ru中的至少一种作为籽晶层；铜扩散阻挡层和籽晶层的生长方式可以选择物理气相沉积、化学气相沉积和原子层沉积中的至少一种。
步骤S5：进行金属布线和制作接触凸点。首先，在上述结构表面采用物理气相沉积方法生长Ti薄膜和Cu薄膜所构成的叠层薄膜210。其中，Ti薄膜和Cu薄膜分别作为粘附层和种子层。然后，采用电镀方法在粘附层/种子层叠层薄膜210的表面，电镀Cu材料和Sn材料所构成的叠层金属，作为微凸点211。接着，采用光刻和刻蚀工艺去除不需要的粘附层/种子层叠层薄膜210，保证相邻微凸点之间没有导通，所得结构如图11所示。随后，采用机械磨削和化学机械抛光联合工艺对SOI基底背面的硅衬底进行减薄，使得铜材料209的底部暴露出来，所得结构如图12所示。最后，采用与制作微凸点211相同的工艺在铜材料209的 底部依次制作出粘附层/种子层叠层薄膜212和C4凸点213，所得结构如图13所示。
如图13所示，本发明的用于三维封装的SOI有源转接板，包括：SOI基底；CMOS反相器，包括PMOS晶体管203和NMOS晶体管204，形成在SOI基底上；SOI通孔，形成在PMOS晶体管203和NMOS晶体管204之间，贯穿所述SOI基底；第一绝缘介质205，包覆PMOS晶体管203和NMOS晶体管204；第二绝缘介质206，形成在SOI通孔侧壁和第一绝缘介质205表面；源漏栅通孔，分别形成在PMOS晶体管203和NMOS晶体管204的源极、漏极和栅极上，贯穿第一绝缘介质205和第二绝缘介质206；SOI通孔的侧壁形成有铜扩散阻挡层207和籽晶层208，内部填充有铜209，顶部形成有粘附层/种子层叠层薄膜210和微凸点211，底部形成有粘附层/种子层叠层薄膜212和C4凸点213；源漏栅通孔底部和侧壁形成有铜扩散阻挡层207和籽晶层208，内部填充有铜209，顶部形成有粘附层/种子层叠层薄膜210和微凸点211。
优选地，第一绝缘介质、第二绝缘介质为二氧化硅、氮化硅、SiOCH、SiOCFH等。优选地，铜扩散阻挡层为TaN、TiN、ZrN、MnSiO 3中的至少一种。优选地，籽晶层为Cu、Co和Ru中的至少一种。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。

Claims (8)

  1. 一种用于三维封装的SOI有源转接板，其特征在于，
    包括：
    SOI基底；
    CMOS反相器，包括PMOS晶体管(203)和NMOS晶体管(204)，形成在所述SOI基底上；
    SOI通孔，形成在所述PMOS晶体管(203)和所述NMOS晶体管(204)之间，贯穿所述SOI基底；
    第一绝缘介质(205)，包覆所述PMOS晶体管(203)和所述NMOS晶体管(204)；
    第二绝缘介质(206)，形成在所述SOI通孔侧壁和所述第一绝缘介质(205)表面；
    源漏栅通孔，分别形成在所述PMOS晶体管(203)和所述NMOS晶体管(204)的源极、漏极和栅极上，贯穿所述第一绝缘介质(205)和所述第二绝缘介质(206)；
    所述SOI通孔的侧壁形成有铜扩散阻挡层(207)和籽晶层(208)，内部填充有铜(209)，顶部形成有粘附层/种子层叠层薄膜(210)和微凸点(211)，底部形成有粘附层/种子层叠层薄膜(212)和C4凸点(213)；
    所述源漏栅通孔底部和侧壁形成有铜扩散阻挡层(207)和籽晶层(208)，内部填充有铜(209)，顶部形成有粘附层/种子层叠层薄膜(210)和微凸点(211)。
  2. 根据权利要求1所述的用于三维封装的SOI有源转接板，其特征在于，
    所述第一绝缘介质(205)、所述第二绝缘介质(206)为二氧化硅、氮化硅、SiOCH或SiOCFH。
  3. 根据权利要求1所述的用于三维封装的SOI有源转接板，其特征在于，
    所述铜扩散阻挡层(207)为TaN、TiN、ZrN、MnSiO 3中的至少一种。
  4. 根据权利要求1所述的用于三维封装的SOI有源转接板，其特征在于，
    所述籽晶层(208)为Cu、Co和Ru中的至少一种。
  5. 一种用于三维封装的SOI有源转接板的制备方法，其特征在于，
    包括以下步骤：
    提供SOI衬底，包括硅衬底(200)，二氧化硅(201)和顶层硅(202)；
    在所述SOI衬底表面制备CMOS反相器，包括PMOS晶体管(203)和NMOS晶体管(204)；
    形成第一绝缘介质(205)，使其包覆所述PMOS晶体管(203)和所述NMOS晶体管(204)；
    对所述PMOS晶体管(203)和所述NMOS晶体管(204)之间的区域进行光刻、刻蚀，直到刻蚀掉部分所述硅衬底(200)；
    在上述结构上形成第二绝缘介质(206)；
    光刻、刻蚀去除所述PMOS晶体管(203)和所述NMOS晶体管(204)的源极、漏极和栅极上的第一绝缘介质(205)和第二绝缘介质(206)，形成源漏栅通孔；
    形成铜扩散阻挡层(207)、籽晶层(208)和铜(209)，采用化学机械抛光工艺去除第二绝缘介质(206)上方的铜(209)、籽晶层(208)和铜扩散阻挡层(207)；
    形成顶部的粘附层/种子层叠层薄膜(210)和微凸点(211)；
    采用机械磨削和化学机械抛光联合工艺对SOI基底背面的硅衬底(200)进行减薄，使得铜(209)的底部暴露出来，形成底部的粘附层/种子层叠层薄膜(212)和C4凸点(213)。
  6. 根据权利要求5所述的用于三维封装的SOI有源转接板的制备方法，其特征在于，
    所述第一绝缘介质(205)、所述第二绝缘介质(206)为二氧化硅、氮化硅、SiOCH或SiOCFH。
  7. 根据权利要求5所述的用于三维封装的SOI有源转接板的制备方法， 其特征在于，
    所述铜扩散阻挡层(207)为TaN、TiN、ZrN、MnSiO 3中的至少一种。
  8. 根据权利要求5所述的用于三维封装的SOI有源转接板的制备方法，其特征在于，
    所述籽晶层(208)为Cu、Co和Ru中的至少一种。
PCT/CN2020/099978 2020-06-30 2020-07-02 一种用于三维封装的soi有源转接板及其制备方法 WO2022000433A1 (zh)

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