TWI550808B - 3d互連結構、3d封裝體及形成一雙鑲嵌3d互連結構之方法 - Google Patents

3d互連結構、3d封裝體及形成一雙鑲嵌3d互連結構之方法 Download PDF

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TWI550808B
TWI550808B TW101134000A TW101134000A TWI550808B TW I550808 B TWI550808 B TW I550808B TW 101134000 A TW101134000 A TW 101134000A TW 101134000 A TW101134000 A TW 101134000A TW I550808 B TWI550808 B TW I550808B
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opening
tsvs
array
layer
hole
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TW101134000A
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TW201320282A (zh
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凱文Ｊ 李
馬克Ｔ 鮑爾
安卓Ｗ 楊
克里斯多福Ｍ 佩爾托
希頓 科薩里
賽夏Ｖ 賽提拉于
馬恆盛
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英特爾公司
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Description

3D互連結構、3D封裝體及形成一雙鑲嵌3D互連結構之方法 發明領域
本發明係有關於三維(3D)封裝，更特別地，係有關於通-矽孔(TSVs)至3D封裝體的整合。
發明背景
3D封裝是出現作為朝向系統單晶片(SOC)與系統級封裝體(SIP)之微電子發展的解決方案。特別地，具有TSVs的3D覆晶結構具有被廣泛地採用的潛力。TSV 3D封裝體通常包含兩個或更多個垂直地堆疊的晶片，貫穿矽基體的通孔代替邊緣導線來產生在每一晶片上之電路元件之間的電氣連接。
聯合電子設備工程會議(Joint Electron Devices Engineering Council(JEDEC))目前正發展一個供一邏輯-對-記憶體界面用之界定該晶片-對-晶片著陸墊界面(chip-to-chip landing pad interface)的WideIO標準。習知地，TSVs的物理位置是位在該等在一晶片上之著陸墊位置正下面，其佔用大量的不動產(real estate)。這表示所有其他電路是被佈局在該等TSV位置四周。
在TSV加工期間，TSVs陣列被形成貫穿一個薄化裝置晶圓。習知TSV結構在該薄化裝置晶圓的背面使用二氧化矽或聚合物作為絕緣材料。這些材料不是密封的，而且未設置一堅實的鈍化層在該薄化裝置晶圓的背面。
依據本發明之一實施例，係特地提出一種3D互連 結構，包含：一具有一正面與一背面的半導體基體；及一雙鑲嵌通孔及重佈層(RDL)；其中，該通孔在該等正與背面之間延伸貫穿該半導體基體，且該RDL是形成在該背面之上。
100‧‧‧半導體基體
102‧‧‧正面
104‧‧‧背面
108‧‧‧導電墊
112‧‧‧金屬化結構
113‧‧‧鈍化層
114‧‧‧絕緣體層
116‧‧‧半導體層
118‧‧‧塊狀基體
120‧‧‧鈍化層
122‧‧‧介電層
124‧‧‧光阻層
126‧‧‧開孔
128‧‧‧光阻層
130‧‧‧開孔
132‧‧‧通孔開孔
134‧‧‧溝渠開孔
136‧‧‧絕緣襯裡層
138‧‧‧障壁層
140‧‧‧填充物
142‧‧‧雙鑲嵌通孔
144‧‧‧重佈層
146‧‧‧鈍化層
148‧‧‧光阻層
152‧‧‧著陸墊
154‧‧‧導電凸塊
160‧‧‧3D互連結構
170‧‧‧基底基體
180‧‧‧晶片
182‧‧‧著陸墊
200‧‧‧暫時載體晶圓
208‧‧‧黏著劑
300‧‧‧系統
310‧‧‧處理器
320‧‧‧記憶體裝置
330‧‧‧記憶體控制器
340‧‧‧圖像控制器
350‧‧‧輸入與輸出控制器
352‧‧‧顯示器
354‧‧‧鍵盤
356‧‧‧指向裝置
358‧‧‧週邊裝置
360‧‧‧匯流排
400‧‧‧計算裝置
402‧‧‧板
404‧‧‧處理器
406‧‧‧通訊晶片
圖1至21是為本發明之實施例之使用雙鑲嵌式加工製造3D互連結構之方法的橫截面側視圖。
圖22是為本發明之實施例之一3D互連結構的示意頂視圖。
圖23是為本發明之實施例之一實施TSVs之3D封裝體的側視圖。
圖24表示本發明之實施例之一系統。
圖25表示本發明之實施例之一計算裝置。
較佳實施例之詳細說明
在不同的實施例中，一3D互連結構與使用雙鑲嵌式加工製造一3D互連結構的方法是被描述。然而，某些實施例會在沒有這些特定細節中之一者或多者之下被實施，或者會與其他習知方法和材料組合來被實施。在後面的說明中，很多特定細節被陳述，像是特定材料與製程等等般，俾可提供本發明的徹底了解。在其他例子中，眾所周知的封裝製程以及製造技術未特別詳細地作描述俾不會 不必要地模糊本發明。這說明書從頭到尾的參閱”一實施例”或者”一個實施例”表示與該實施例有關的一特定特徵、結構、材料、或特性是被包括在本發明之至少一個實施例內。因此，該片語”在一實施例中”或者”在一個實施例中”在這說明書之不同位置中的出現不是必要地與本發明的同一實施例相關連。再者，在一個或多個實施例中的該等特定特徵、結構、材料、或特性可以以任何適當的形式組合。
於此中所使用的術語”在..之上”、”至”、”在...之間”以及”在...上”可以是指一個層相對於其他層的相對位置。一個層”在另一個層之上”或者被連結”至”另一個層可以是直接地與該另一個層接觸或者可以具有一個或多個中介層。”在層之間”的一個層可以是直接與該等層接觸或者可以具有一個或多個中介層。對比下，”在一第二層上”的一第一層是與該第二層接觸。
在一特徵中，本發明的實施例描述一3D互連結構以及使用雙鑲嵌式製程流程來把通-矽孔(TSVs)與非常微距背面金屬重佈線(RDLs)結合的製程。這特別組合可以允許該等TSVs的物理位置與該等晶片-對-晶片著陸墊位置解耦(decoupled)，因此提供較大的電路佈局彈性。在這形式下複數的RDLs可以在相鄰的著陸墊行或列之間運行。例如，複數個RDLs可以在以10 μm-500 μm之間距分隔之相鄰的著陸墊行或列之間運行。根據本發明的實施例，雙鑲嵌式加工會允許密封地密封3D互連結構與一比電鍍貫穿光 阻方法更能完成的微距RDL架構，並且允許在用於產生鋁RDL線的減法蝕刻製程中無法使用之銅金屬的使用。
在另一特徵中，本發明的實施例描述一把該等背面RDLs從該磨薄裝置晶圓之大批半導體(例如，矽)分開的氮化矽或碳化矽鈍化層。該氮化矽或碳化矽鈍化層可以提供一保護該磨薄裝置晶圓之背面在雙鑲嵌式加工期間免於軌跡金屬與濕氣污染的密封障壁。此外，該背面鈍化層材料在該雙鑲嵌式製程中很有用的是在該等背面RDLs的氧化物溝渠蝕刻期間該鈍化層材料也能夠作用如一蝕刻擋止層，其在雙鑲嵌式加工期間在沒有引起明顯量的鈍化層也被移除之下允許該氧化物溝渠蝕刻併合大量的過蝕刻。
據此，本發明的實施例描述把雙鑲嵌製程整合至TSV製程的方式，在其中，該雙鑲嵌製程會允許非常微距背面RDLs的形成與較大電路佈局彈性，而另一方面也把一能夠提供裝置之加強可靠性性能的密封障壁鈍化層整合至該製程序列。要了解的是，雖然實施例是配合矽裝置晶圓的TSV製程來作說明，該等實施例也可應用到矽晶圓之外的基體，像是化合物III-V晶圓或II-VI晶圓般。
請參閱圖21所示，在一實施例中一3D互連結構160包括一具有一正面102與一背面104的半導體基體100，及一雙鑲嵌通孔142和重佈層(RDL)144。該通孔(例如，TSV)142在該正102與背104背面之間延伸貫穿該半導體基體100，而該RDL 144是形成在該背面104之上。一鈍化層120可以設置在該背面104與該RDL 144之間來防止濕氣與軌跡 金屬污染物進入該半導體基體100。適合的鈍化層材料會是碳化矽和氮化矽。在某些實施例中，該半導體基體100可以是一包括數個所述之3D互連結構的TSV加工裝置晶圓。或者，該TSV加工裝置晶圓是被分割來形成數個會或者不會被進一步加工來形成數個晶片的半導體基體，其然後會被整合成3D封裝結構。因此，在一實施例中該3D互連結構160是為一晶片。
請參閱圖21-22所示，在一實施例中該3D互連結構160包括一以一系列之列與行之形式配合在該背面104之上的著陸墊152陣列。例如，在該陣列中的列和行會具有10 μm至500 μm的間距。一TSVs 142陣列會被佈置在該背面104下面以致於該TSVs 142陣列不是以一個與該著陸墊152陣列相同的圖案來佈置。在一實施例中，該TSVs 142陣列不是在該著陸墊152陣列正下方。在如此的一實施例中，數條RDLs 144會在兩列著陸墊152之間運行，把該兩列中之一者連接到在該TSVs陣列中之對應數目的TSVs 142。例如，該兩列著陸墊可以隔開10 μm至500 μm的間距。這樣，RDLs 144允許在TSVs 142之物理位置與電路佈局方面的彈性。
請參閱圖23所示，在一實施例中一3D封裝體包括一像是一印刷電路板或者一層疊基體般的基底基體170。一晶片堆疊是形成在該基底基體之上，在其中，該晶片堆疊包括一形成有該3D互連結構的晶片160。在一實施例中，該晶片160是為一邏輯晶片，而且一個或者多個記憶體晶片180是在該邏輯晶片之該著陸墊陣列(在一導電凸塊 154陣列下面)與該記憶體晶片180之一對應的著陸墊182陣列耦合之下堆疊到該邏輯晶片160上，儘管實施例未被限制為如此而且可以包括多種晶片-對-晶片結構。
在一實施例中，一種形成一包括一雙鑲嵌通孔與RDL之3D互連結構的方法是被描述，其包括形成一含碳化矽或氮化矽的鈍化層於一裝置晶圓的背面之上，而然後形成一介電層在該鈍化層之上。一溝渠開孔然後是形成在該介電層中於希望有一具備著陸墊的RDL的地方。一通孔開孔(例如，TSV開孔)是形成在該裝置晶圓中於該裝置晶圓的背面與正面之間。大量的通孔和溝渠然後會藉電鍍來以像是銅般的導電金屬來充填，例如。隨後，一導電凸塊是形成在該被充填的溝渠之上，被充填的通孔不是在該著陸墊正下方。在一實施例中，形成該溝渠開孔可以使用一圖案化光阻層作為一光罩以電漿蝕刻該介電層，並在該鈍化層上停止該電漿蝕刻來被執行。這樣，該鈍化層不僅能夠作用來防止濕氣與軌跡金屬污染物進入該裝置晶圓，且也作用為一在沒有致使該鈍化層之也被移除之顯著的量之下允許該電漿蝕刻製程併合大量過蝕刻的蝕刻擋止層。
現在請參閱圖1-22所示，一種製造一3D互連結構的方法是配合該等圖式來作描述。一倒轉的裝置晶圓100是被描繪在第1圖中，其可以包括一正面102和一背面104。該裝置晶圓100可以具有多種形態。例如，該裝置晶圓可以是一塊狀半導體(bulk semiconductor)，包括一疊置在一塊狀半導體之上的磊晶層，或者包括一半導體-在-絕緣體上(SOI) 結構，儘管其他結構是可以被使用。在所描繪的該特定實施例中，該裝置晶圓100包括一包括疊置在絕緣體層114上之半導體層116的(SOI)結構，及塊狀基體118。該裝置晶圓100可以額外地包括摻雜區域或者其他摻雜特徵來形成各種微電子裝置，像是金屬-絕緣體-半導體場效電晶體(MOSFETs)、電容器、電感器、電阻器、二極體、微機電系統(MEMS)、其他適合的主動或被動裝置、以及其之組合般。
一金屬化結構112可以形成在該裝置晶圓100的正面102上。如圖所示，金屬化結構112包括複數個由像是銅、鋁等等般之導電金屬以及像是氧化矽、摻雜碳之氧化物、氮化矽等等般之中間層介電材料形成的互連層。一鈍化層113可以形成在該金屬化結構112的上部份之上來提供物理與化學保護。一個或多個導電墊108(例如，銅、鋁等等)可以設置在該等位於鈍化層113中的開孔之上。
現在請參閱圖2-4所示，該裝置晶圓100是利用商業上可得到的暫時黏著劑208以及設備來黏接到一暫時載體晶圓200。該裝置晶圓100然後可以藉研磨、化學機械研磨(CMP)、電漿蝕刻及/或濕蝕刻該背面104來使背面變薄。例如，在一實施例中該裝置晶圓100可以使背面變薄成大約50-100 μm。
在使該裝置晶圓100變薄之後，一鈍化層120可以形成在該背面104之上來提供一密封障壁，一像是二氧化矽般之供非常微距金屬RDL用的介電層122是接著在該鈍化 層120後面。在一實施例中，鈍化層120的合適材料包括碳化矽和氮化矽，因為這些材料可以提供一密封障壁，其保護該磨薄之裝置晶圓100的背面104免於軌跡金屬和濕氣污染。鈍化層120與介電層122能夠以像是化學蒸氣沉積(CVD)般之合適的方法來沉積。
現在請參閱圖5-7所示，一光阻層是塗佈到該磨薄的裝置晶圓上、曝光和顯影。在顯影之後，於該圖案化光阻層124中在那些希望有包括著陸墊之微距金屬RDLs的位置處是有開孔126。使用一像是電漿蝕刻般的合適方法，溝渠然後利用該圖案化光阻層124作為光罩來被蝕刻貫穿該介電層122的整個深度，停在鈍化層120上。根據該雙鑲嵌製程流程的一些實施例，碳化矽或氮化矽鈍化層120材料在形成RDLs的溝渠蝕刻製程期間可以作為一蝕刻擋止層，在沒有致使顯著鈍化層120的量也被移除之下允許該溝渠蝕刻製程體現大量的過蝕刻。在該蝕刻製程後面，該圖案化光阻層124被移除而任何餘下的蝕刻聚合物或殘餘物會被清除。
一第二光阻層然後是塗佈到該磨薄的裝置晶圓上、曝光和顯影。如在圖8中所示，在該圖案化光阻層128中於那些希望有通孔(例如，TSVs)的位置處是有開孔130。請參閱圖9-10所示，通孔開孔然後被電漿蝕刻貫穿該鈍化層120，以及貫穿在背面104與正面102之間的裝置晶圓100，停止於在金屬結構112之內的銅著陸墊上。該圖案化光阻層128然後被移除而任何餘下的蝕刻聚合物或殘餘物 會被清除以得到通孔開孔132(例如，TSV開孔)與溝渠開孔134(例如，RDL開孔)。
如在圖11中所示，一絕緣襯裡層136然後被沉積，襯塗該等通孔開孔132與溝渠開孔134的底部和側壁，以及在介電層122之通孔開孔之間的區域。絕緣襯裡層136之合適的材料包括，但不限於，二氧化矽、氮化矽、碳化矽、及各種聚合物。這些材料可以藉CVD、原子層沉積(ALD)、與旋塗法來沉積，例如。如在圖12中所示，一各向異性電漿蝕刻製程然後可以被使用來把絕緣襯裡層136從該等通孔開孔132與溝渠開孔134的底部表面，以及從在介電層122之上之通孔開孔之間的區域移除，而同時保持在該等通孔開孔132之側表面上之絕緣襯裡層136的實質厚度。在如此的一實施例中，該絕緣襯裡層136可以直接形成在該等由該塊狀矽基體118所界定的通孔開孔132側壁上。因此，該絕緣襯裡層136在該最終3D互連結構中是作用來使該TSV與該周圍矽基體材料隔離。該絕緣襯裡層136的實質厚度也可以維持在溝渠開孔134的側表面上。
請參閱圖13-15所示，一障壁層138與種子層然後可以被沉積到該裝置晶圓表面上。例如，該障壁層138可以包括鉭、鈦、或鈷。該種子層可以是銅，例如。一銅圍包層140然後被電鍍到該裝置晶圓表面上，完全以銅填充該等TSV開孔132與RDL開孔134。過多的銅和該障壁層然後是藉CMP來從介電層122之上移除，如在圖15中所示。該最終結構包括雙鑲嵌TSVs 142與RDLs 144，在其中，TSVs 142 延伸貫穿該裝置晶圓100在該正面102與背面104之間而RDLs 144是形成在該背面104之上。在如此的雙鑲嵌結構中一單一金屬填充物140充任大量的TSVs 142和RDLs 144，其可以襯塗障壁層138與種子層(例如，用於電鍍)以及絕緣襯裡層136。
現在請參閱圖16-19所示，著陸墊開孔是形成在該等RDLs 144之上。一鈍化層146是沉積在該平坦化表面之上。合適的材料包括，但不限定為，氮化矽，其可以提供一個對抗軌跡金屬與濕氣污染，以及保護該等RDLs 144免於氧化的密封障壁。一光阻材料然後是塗佈於該鈍化層146之上、曝光以及顯影來形成一圖案化光阻層148。在顯影之後，於該光阻層148中是有開孔150位在RDLs 144要終止在希望有晶片-對-晶片連接之著陸墊的位置處。開孔然後使用該圖案化光阻層148作為光罩利用像是電漿蝕刻般之合適的技術來被蝕刻貫穿該鈍化層146，停止在該底層RDL 144著陸墊152上。該光阻層148然後被移除而任何餘下的蝕刻聚合物或殘留物會被清除。
現在請參閱圖20所示，一導電凸塊154是形成在該等露出之RDL 144著陸墊152中之每一者上。任何合適的技術是可以被實施來形成導電凸塊154，像是，但不限定為，焊錫凸塊、使用圖案化製程的電鍍、以及無電電鍍般。在圖20中所描繪的特定實施例中，露出的RDL 144著陸墊152是塗佈有一焊料可相容表面層(solder-compatible surface finish)。導電凸塊154用的範例表面層包括無電CoP/ 浸沒Au、無電CoWP/浸沒Au、無電Ni/P浸沒Au、無電NiP/無電Pd/浸沒Au、無電Sn、無電NiP/無電Sn、無電CoP/無電Sn、無電CoWP/無電Sn、CoWP/無電Sn、無電Cu/無電CoP/浸沒Au、無電Cu/無電CoWP/浸沒Au、無電Cu/無電NiP/浸沒Au、無電Cu/無電NiP/無電Pd/浸沒Au、無電Cu/無電Sn、無電Cu/無電NiP/無電Sn、無電Cu/無電CoP/浸沒Au、無電Cu/無電CoWP/無電Sn。端視該(等)晶片-對-晶片焊接材料及/或使用的晶片-對-晶片連接方法而定，其他的表面層也可以是合適的。在另一實施例中，導電凸塊154可以是由像是PbSn、Sn、SnAg、Cu、In、SnAgCu、SnCu、Au等等般之材料形成的一C4或覆晶凸塊。
該載體晶圓200與黏著劑208然後是利用商業上可得到的晶圓解除-連接(de-bonding)設備與製程來從該裝置晶圓100移除，如在圖21中所示。在該載體晶圓200與黏著劑208的移除之時，在圖21中所示之該最終數個3D互連結構160會被切割，而然後會或不會被進一步處理來形成然後可以被整合成3D封裝結構的晶片。
請參閱圖22所示，一範例標準化晶片-對-晶片著陸墊界面是被描繪用於把一第二晶片連接到本發明之實施例的3D互連結構。如更詳細地在該放大圖中所示，一著陸墊152陣列是以連串之列與行的形式佈置在該背面104(見圖21)之上。一TSVs 142陣列是佈置在該背面104下面以致於該TSVs陣列不是在該著陸墊152陣列正下面。數個RDLs 144是在該等著陸墊152列中之二者之間運行把該兩著陸墊 152列中之一者連接到在該TSVs陣列中之對應數目的TSVs 142。這樣，連接背面著陸墊152到正面電路(金屬結構112)的TSVs可以位在該晶片上的任何地方。雖然本發明的實施例業已描述該TSVs陣列不是在該著陸墊及/或導電凸塊陣列正下方，要察知的是一些TSVs會是在該著陸墊及/或導電凸塊陣列正下方。本發明的實施例藉著雙鑲嵌製程的整合來提供TSVs之位置的彈性。結果，是不需要TSVs陣列的位置在連接該等TSVs之對應之著陸墊及/或導電凸塊陣列正下方。
為了進一步描繪本發明之實施例允許電路設計彈性的能力，在一個範例中，於圖22中所示之著陸墊152陣列會具有50 μm的垂直間距和40 μm的水平間距，而且該等著陸墊152具有20 μm的直徑。在該特定範例中這留有30 μm讓該六個RDLs 144在兩列著陸墊152之間運行。假設該六條RDL線的寬度與相鄰於和在該等RDLs 144之間的七個空間是相同，每一RDL 144會具有一個2.3 μm的線寬度。本發明之實施例的雙鑲嵌式製程會特別適合於實現如此之範例微距RDL架構，雖然實施例未如此限制而且也可以被用於任何間距的RDL架構。
圖23是為一實現本發明之實施例之3D互連結構之某些特徵之3D封裝體的說明範例。如圖所示，數個晶片是堆疊在一像是印刷電路板或積層基體般的基體170之上。例如，一晶片堆疊可以包括一包括一如於此中所述之3D互連結構的晶片160和一個或多個堆疊在晶片160之上的 晶片180。在一個實施例中，晶片160是為一包括一如於此中所述之3D互連結構的邏輯晶片而晶片180是為記憶體晶片。一3D封裝體或者可包括一堆疊於至少一個記憶體晶片180之上的邏輯晶片180。如圖所示，導電凸塊154陣列，而因此在該等導電凸塊154下面的著陸墊152(圖中未示)是與記憶體晶片180之對應的著陸墊182陣列對準，而導電墊108是與基體170連接。要察覺到的是，雖然圖23是為邏輯晶片160與記憶體晶片180之範例堆疊的說明，本發明的實施例不受限為如此而且像是記憶體(例如，DRAM、eFLASH、eRAM等等)、中介物、RF、MEMS等等般之合適之晶片的各種晶片-對-晶片結構是想像得到的。
圖24顯示本發明之實施例的一電腦系統。系統300包括一處理器310、一記憶體裝置320、一記憶體控制器330、一圖像控制器340、一輸入與輸出(I/O)控制器350、一顯示器352、一鍵盤354、一指向裝置356、及一週邊裝置358，在某些實施例中，它們全部會是透過一匯流排360來彼此通訊地耦合。處理器310可以是一般用途處理器或者一應用指定積體電路(ASIC)。I/O控制器350可以包括一供有線或無線通訊用的通訊模組。記憶體裝置320可以是一動態隨機存取記憶體(DRAM)裝置、一靜態隨機存取記憶體(SRAM)裝置、一快閃記憶體裝置、或者這些記憶體裝置的組合。因此，在一些實施例中，在系統300中的記憶體裝置320不必包括一DRAM裝置。
顯示在系統300內之該等組件中之一者或多者可 以被包括在一個或多個積體電路封裝體內/及或可以包括一個或多個積體電路封裝體，像是圖23的3D封裝體或晶片160般，例如。例如，處理器310，或記憶體裝置320，或I/O控制器350的至少一部份，或這些組件的組合是可以被包括在一包括在該等各種實施例中所述之結構之至少一實施例的積體電路封裝體內。
這些元件執行它們眾所周知的習知功能。特別地，在藉著處理器310的執行期間記憶體裝置320在一些情況中是可以被使用來提供本發明之實施例之用於形成封裝結構之方法之可執行指令的長期儲存，而在其他實施例中可被用來依較短期基準儲存本發明之實施例之用於形成封裝結構之方法之可執行指令。此外，該等指令可以被儲存，或者是與通訊地與該系統連結的機器可存取媒體結合在一起，像是光碟唯讀記憶體(CD-ROMs)、多功能數位碟片(DVDs)、及軟碟、載波、及/或其他傳播訊號般，例如。在一個實施例中，記憶體裝置320可以供應該處理器310該等可執行指令以供執行。
系統300可以包括電腦(例如，桌上型、膝上型、手持式、何服器、網絡設備(Web appliances)、路由器等等)、無線通訊裝置(例如，細胞電話、無線電話、傳呼器、個人數位助理等等)、電腦-相關週邊設備(例如，印表機、掃描器、監視器等等)、娛樂裝置(例如，電視機、收音機、立體音響裝置、錄音帶與光碟播放器、卡式錄放影機、攝錄像機、數位攝影機、MP3(MPEG第三代聲音文件壓縮格式) 播放器、電動遊戲、手錶等等)、及其類似。
圖25描繪本發明之一實施例的計算裝置400。該計算裝置400容納一板402。該板402可以包括若干組件，包括但不限於一處理器404和至少一個通訊晶片406。該處理器404是物理地與電氣地連結至該板402。在一些實施中，該至少一個通訊晶片406也是物理地與電氣地連結到該板402。在另外的實現中，該通訊晶片406是該處理器404的一部份。
端視其之應用而定，計算裝置400可以包括會或不會是物理地和電氣地連結至該板402的其他組件。這些其他組件包括，但不限於，揮發性記憶體(例如，DRAM)、非揮發性記憶體(例如，ROM)、快閃記憶體、圖像處理器、數位訊號處理器、密碼處理器(crypto processor)、晶片組、天線、顯示器、觸摸式顯示器、觸摸式控制器、電池、音頻編解碼器(audio codec)、視頻編解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、加速度計、迴轉儀、揚聲器、攝影機、及大量儲存裝置(像是硬碟機、光碟(CD)、多功能數位碟片(DVD)等等般)。
該通訊晶片406致使資料至該計算裝置400之傳輸與來自該計算裝置400之資料之傳輸用的無線通訊。該詞”無線”及其之衍生物是可以用來描述透過經由非固體媒體之調制電磁輻射(modulated electromagnetic radiation)之使用能夠傳遞資料的電路、裝置、系統、方法、技術、通訊通道等等。該詞不暗示相關裝置不包含任何導線，雖然 在一些實施例中它們會是不包含任何導線。該通訊晶片406可以實現若干無線標準或協定中之任一者，包括但不限於Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、其之衍生物、以及任何其他被定名為3G、4G、5G、與更往後之無線協定。該計算裝置400可以包括數個通訊晶片406。例如，一第一通訊晶片406可以是獻給較短範圍的無線通訊，像是Wi-Fi與藍芽般而一第二通訊晶片406是可以獻給較長範圍的無線通訊，像是GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等等般。
該計算裝置400的處理器404包括一封裝在該處理器404之內的積體電路晶元。在本發明的一些實施中，該處理器的積體電路晶元可以被包括在一個或多個積體電路封裝體內或者可以包括一個或多個積體電路封裝體，像是圖23的3D封裝體或晶片160般，例如。該詞”處理器”可以是指處理來自暫存器及/或記憶體之電子資料俾可把該電子資料轉變成其他可以儲存於暫存器及/或記憶體內之電子資料的任何裝置或者一裝置的部份。
該通訊晶片406也包括一被封裝在該通訊晶片406之內的積體電路晶元。根據本發明的另一實施，該通訊晶片的積體電路晶元可以被包括在一個或多個積體電路封裝體內或者可以包括一個或多個積體電路封裝體，像是圖23的3D封裝體或晶片160般，例如。
在另外的實施中，容納在該計算裝置400之內的另一組件可以包含一積體電路封裝體，像是圖23的3D封裝體或晶片160般，例如。此外，該處理器404、通訊晶片406及被容納於該計算裝置400之內的其他組件是能夠以圖23的3D封裝體形式堆疊，例如。
在各種實施中，該計算裝置400可以是一膝上型電腦、小筆電、筆記本型電腦、超極緻筆電(ultrabook)、智慧型電話、平板電腦、個人數位助理(PDA)、超級移動電腦(ultra mobile PC)、行動電腦、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位攝影機、可攜帶型音樂播放器、或者數位錄影機。在另外的實施中，該計算裝置400可以是任何其他處理資料的電子裝置。
雖然本發明以結構特徵及/或方法動作之特定語言被描述，但是需明白的是，在後附的申請專利範圍中定義的發明並不需要限於以上所述的特定特徵或動作。所揭露的特定特徵及動作要被理解是作為要求保護之發明之用於說明本發明的特定實施。
100‧‧‧半導體基體
102‧‧‧正面
104‧‧‧背面
108‧‧‧導電墊
112‧‧‧金屬結構
113‧‧‧鈍化層
114‧‧‧絕緣體層
116‧‧‧半導體層
118‧‧‧塊狀基體
120‧‧‧鈍化層
122‧‧‧介電層
136‧‧‧絕緣襯裡層
138‧‧‧障壁層
142‧‧‧雙鑲嵌通孔
144‧‧‧重佈層
146‧‧‧鈍化層
154‧‧‧導電凸塊
160‧‧‧3D互連結構

Claims (19)

  1. 一種3D互連結構，包含：一具有一正面與一背面的半導體基體；一雙鑲嵌通孔及重佈層(RDL)；其中，該雙鑲嵌通孔在該等正與背面之間延伸貫穿該半導體基體，且該RDL是形成在該背面之上於一溝渠開孔中；及一形成在該雙鑲嵌通孔與該溝渠開孔之側表面上，且不形成在該雙鑲嵌通孔與該溝渠開孔之底表面上的絕緣襯裡層。
  2. 如申請專利範圍第1項所述之3D互連結構，更包含一設置在該背面與該RDL之間的鈍化層。
  3. 如申請專利範圍第2項所述之3D互連結構，其中，該鈍化層包含碳化矽或氮化矽。
  4. 如申請專利範圍第1項所述之3D互連結構，其中，該雙鑲嵌通孔與RDL更包含一形成於該雙鑲嵌通孔與該溝渠開孔之底表面上，以及在該形成於該雙鑲嵌通孔與該溝渠開孔之側表面上之絕緣襯裡層上的連續障壁層。
  5. 如申請專利範圍第3項所述之3D互連結構，更包含：一以一系列之列與行的方式配置在該背面之上的著陸墊陣列；一通矽孔(TSVs)陣列，該通矽孔(TSVs)陣列是配置在該背面下面以致於該TSVs陣列不是在該著陸墊陣列正下方；及數條在兩列著陸墊之間運行之把該兩列著陸墊中之 一者連接到在該TSVs陣列中之對應數目之TSVs的RDLs。
  6. 如申請專利範圍第5項所述之3D互連結構，其中，該兩列著陸墊是以10μm至500μm的間距隔開。
  7. 一種3D封裝體，包含：一基底基體；一形成在該基底基體之上的晶片堆疊；其中，該晶片堆疊包括一晶片，包含：一具有一正面與一背面的半導體基體；一雙鑲嵌通孔與重佈層(RDL)；其中，該雙鑲嵌通孔在該半導體基體的該等正與背面之間延伸，且該RDL是形成在該背面之上於一溝渠開孔中；及一形成在該雙鑲嵌通孔與該溝渠開孔之側表面上，且不形成在該雙鑲嵌通孔與該溝渠開孔之底表面上的絕緣襯裡層。
  8. 如申請專利範圍第7項所述之3D封裝體，其中，該晶片是為一邏輯晶片。
  9. 如申請專利範圍第8項所述之3D封裝體，更包含一系統，該系統包含一通訊地耦合至該3D封裝體的匯流排。
  10. 如申請專利範圍第8項所述之3D封裝體，其中，該邏輯晶片更包含：一以一系列之列與行的方式配置在該背面之上的著陸墊陣列；一通矽孔(TSVs)陣列，該通矽孔(TSVs)陣列是配置在 該背面下面以致於該TSVs陣列不是在該著陸墊陣列正下方；及數條在兩列著陸墊之間運行之把該兩列著陸墊中之一者連接到在該TSVs陣列中之對應數目之TSVs的RDLs。
  11. 如申請專利範圍第10項所述之3D封裝體，其中，該著陸墊陣列是與一記憶體晶片之一對應的著陸墊陣列耦合。
  12. 一種形成一雙鑲嵌3D互連結構之方法，包含：形成一鈍化層在一裝置晶圓的一背面之上，其中，該鈍化層包含碳化矽或氮化矽；形成一介電層在該鈍化層之上；形成一溝渠開孔在該介電層中；形成一通孔開孔在該裝置晶圓中於該裝置晶圓的該背面與一正面之間；形成一絕緣襯裡層在該通孔開孔與該該溝渠開孔之側表面上，但不在該通孔開孔與該溝渠開孔之底表面上；以導電金屬填充大量的該通孔開孔和該溝渠開孔俾可形成一通孔與包括一著陸墊的重佈層(RDL)，其中，該通孔不是在該著陸墊正下方；及形成一導電凸塊於該著陸墊之上。
  13. 如申請專利範圍第12項所述之方法，其中，形成溝渠開孔包含電漿蝕刻該介電層。
  14. 如申請專利範圍第13項所述之方法，其中，該電漿蝕刻 包含利用一圖案化光阻層作為一光罩，及在該鈍化層上停止該電漿蝕刻。
  15. 如申請專利範圍第12項所述之方法，其中形成該絕緣襯裡層包含首先沉積一絕緣襯裡材料在該通孔開孔與該溝渠開孔的側和底表面上。
  16. 如申請專利範圍第15項所述之方法，其中形成該絕緣襯裡層更包含在保持一絕緣襯裡材料之一實質厚度在該通孔開孔與該溝渠開孔的側表面上時從該通孔開孔與該溝渠開孔的底表面開始各向異性地蝕刻該絕緣襯裡材料。
  17. 如申請專利範圍第12項所述之方法，其中，以導電金屬填充該大量的該通孔開孔與該溝渠開孔包含電鍍銅。
  18. 如申請專利範圍第12項所述之方法，更包含：以一系列之列與行的方式形成一著陸墊陣列在該背面之上；形成一通矽孔(TSVs)陣列在該背面下面以致於該TSVs陣列不是在該著陸墊陣列正下方；及形成數條在兩列著陸墊之間運行之把該兩列著陸墊中之一者連接到在該TSVs陣列中之對應數目之TSVs的RDLs。
  19. 如申請專利範圍第18項所述之方法，其中，該兩列著陸墊是以10μm至500μm的間距隔開。
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