CN103890940A - 包括结合使用双镶嵌型方案制造的微细间距背侧金属再分布线的穿硅过孔的3d互连结构 - Google Patents

包括结合使用双镶嵌型方案制造的微细间距背侧金属再分布线的穿硅过孔的3d互连结构 Download PDF

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CN103890940A
CN103890940A CN201180074420.9A CN201180074420A CN103890940A CN 103890940 A CN103890940 A CN 103890940A CN 201180074420 A CN201180074420 A CN 201180074420A CN 103890940 A CN103890940 A CN 103890940A
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array
bond pad
tsv
rdl
layer
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CN103890940B (zh
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K·J·李
M·T·博尔
A·W·杨
C·M·佩尔托
H·科塔里
S·V·萨蒂拉朱
H-S·马
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Intel Corp
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Abstract

本发明说明了一种3D互连结构和制造方法，其中，使用双镶嵌型工艺流程形成穿硅过孔(TSV)和金属再分布层(RDL)。可以在减薄的器件晶片背侧和RDL之间提供氮化硅或碳化硅钝化层，以在工艺流程过程中提供密封屏障和蚀刻停止层。

Description

包括结合使用双镶嵌型方案制造的微细间距背侧金属再分布线的穿硅过孔的3D互连结构
技术领域
本发明涉及三维(3D)封装，更具体来说，涉及穿硅过孔(TSV)在3D封装中的集成。
背景技术
3D封装作为用于向片上系统(SOC)和系统级封装(SIP)的微电子发展的解决方案脱颖而出。尤其是具有TSV的3D倒装芯片结构具有被广泛采用的潜力。TSV3D封装通常包含垂直叠置的两个或更多个芯片，具有代替边缘布线的穿过硅衬底的过孔，以在每一个芯片上的电路元件之间产生电连接。
电子元件工业联合会(JEDEC)当前开发了一种WideIO标准，其规定了逻辑到存储器接口的芯片对芯片接合焊盘接口(landing pad interface)。传统上，TSV的物理位置位于芯片上的接合焊盘位置的正下方，其占用了大量面积。这意味着所有其他电路都布置在TSV位置的周围。
在TSV处理过程中，通过减薄的器件晶片形成TSV的阵列。传统TSV结构使用二氧化硅或聚合物作为减薄的器件晶片的背侧上的绝缘体材料。这些材料不是密封的(hermetic)，在减薄的器件晶片背侧上没有提供鲁棒的钝化层。
附图说明
图1－21是根据本发明实施例的使用双镶嵌处理的制造3D互连结构的方法的截面侧视图。
图22是根据本发明实施例的3D互连结构的示意性顶视图。
图23是根据本发明实施例的实施TSV的3D封装的侧视图。
图24表示根据本发明实施例的系统。
图25表示根据本发明实施例的计算设备。
具体实施方式
在多个实施例中，说明了3D互连结构和利用双镶嵌处理制造3D互连结构的方法。但某些实施例的实践可以无需这些特定细节中的一个或多个，或者结合了其他已知的方法和材料。在以下说明中，阐述了多个特定细节，例如特定材料和工艺等，以便提供对本发明透彻的理解。在其他实例中，没有特别详细说明公知的封装工艺和制造技术，以避免不必要地使得本发明难以理解。在本说明书通篇中对“实施例”或“一个实施例”的提及表示结合该实施例说明的特定特征、结构、材料或特性包括在本发明的至少一个实施例中。因而，短语“在实施例中”或“在一个实施例中”在本说明书通篇的多个位置的出现不一定全都指代本发明相同的实施例。而且，特定特征、结构、材料或特性可以以任意适合的方式组合到一个或多个实施例中。
本文使用的术语“在……之上”、“到”、“之间”和“在……上”可以指代一层相对于其他层的相对位置。“在另一层之上”或接合“到”另一层的一层可以与另一层直接接触，或者可以具有一个或多个居间层。在多层“之间”的一层可以与所述多层直接接触，或者可以具有一个或多个居间层。相反，“在第二层上”的第一层与该第二层接触。
在一个方案中，本发明的实施例说明了一种3D互连结构和工艺，其使用双镶嵌型工艺流程，将穿硅过孔(TSV)与极微细间距背侧金属再分布层(RDL)相组合。这个特定组合可以允许TSV的物理位置与芯片对芯片接合焊盘位置分离，从而提供更大的电路布局灵活性。以此方式，能够在相邻接合焊盘行或列之间延伸多个RDL。例如，可以在以10μm-500μm间距分隔开的相邻接合焊盘行或列之间延伸多个RDL。根据本发明的实施例，双镶嵌型处理可以实现密封地封闭的3D互连结构和间距比利用镀通抗蚀剂法(plate through resist method)所能够实现的间距更微细的RDL架构，并允许使用铜金属，其对于用来生产铝RDL线的减成蚀刻工艺是不可能的。
在另一个方案中，本发明的实施例说明了一种氮化硅或碳化硅钝化层，其将背侧RDL与减薄器件晶片的块状半导体(例如硅)分离。氮化硅或碳化硅钝化层可以提供密封屏障(barrier)，其在双镶嵌处理过程中保护减薄器件晶片的背侧使其免于痕量金属和湿气污染。另外，背侧钝化层材料在双镶嵌工艺中是有用的，因为钝化层材料在用于背侧RDL的氧化物沟槽蚀刻过程中还可以充当蚀刻停止层，这允许氧化物沟槽蚀刻包含大量的过蚀刻，而不会导致相当大量的钝化层在双镶嵌处理过程中也被去除。
因此，本发明的实施例说明了一种将双镶嵌处理合并到TSV处理中的方式，其中，双镶嵌处理可以允许极微细间距背侧RDL的形成以及更大的电路布局灵活性，同时还将密封屏障钝化层合并到处理序列中，其可以提供器件的增强的可靠性性能。会理解，尽管参考硅器件晶片的TSV处理说明了实施例，但实施例也可以应用于除了硅晶片以外的衬底，例如化合物III-V族晶片或II-VI族晶片。
参考图21，在一个实施例中，3D互连结构160包括：具有正表面102和背表面104的半导体衬底100、以及双镶嵌过孔142和再分布层(RDL)144。过孔(例如TSV)142穿过半导体衬底100、在正表面102与背表面104之间延伸，RDL144形成于背表面104之上。钝化层120可以布置在背表面104与RDL144之间，以避免湿气和痕量金属污染进入半导体衬底100。适合的钝化层材料可以是碳化硅和氮化硅。在一些实施例中，半导体衬底100可以是TSV处理的器件晶片，包括多个所述3D互连结构。可替换地，将TSV处理的器件晶片单个化，以形成多个半导体衬底，可以进一步处理或不处理所述多个半导体衬底，以形成多个芯片，芯片随后可以集成到3D封装结构中。这样，在实施例中，3D互连结构160是芯片。
参考图21－22，在一个实施例中，3D互连结构160包括以一系列行和列排列在背表面104之上的接合焊盘152的阵列。例如，阵列中的行和列可以具有10μm到500μm的间距。TSV142的阵列可以布置在背表面104之下，以使得TSV142的阵列没有以与接合焊盘152的阵列相同的图案排列。在一个实施例中，TSV142的阵列不在接合焊盘152的阵列的正下方。在这个实施例中，多个RDL144可以在接合焊盘152的两行之间延伸，将两行中的一行连接到TSV阵列中相应数量的TSV142。例如，接合焊盘的两行可以以10μm到500μm的间距分隔开。以此方式，RDL144允许TSV142的物理位置和电路布局的灵活性。
参考图23，在一个实施例中，3D封装包括基底衬底170，例如印刷电路板或层合衬底。芯片叠置体形成于基底衬底之上，其中，芯片叠置体包括以3D互连结构形成的芯片160。在一个实施例中，芯片160是逻辑芯片，一个或多个存储器芯片180叠置在逻辑芯片160上，逻辑芯片的接合焊盘的阵列(在导电凸块154的阵列下面)与存储器芯片180的接合焊盘182的相应阵列耦合，尽管实施例不限于此，而是可以包括各种芯片对芯片结构。
在一个实施例中，说明了形成包括双镶嵌过孔和RDL的3D互连结构的方法，其包括在器件晶片的背表面之上形成包含钝化层的碳化硅或氮化硅，随后在钝化层上形成电介质层。随后在电介质层中期望存在具有接合焊盘的RDL的位置形成沟槽开口。在器件晶片中的器件晶片的背表面与正表面之间形成过孔开口(例如，TSV开口)。例如，随后借助电镀以诸如铜的导电金属填充过孔和沟槽的总体积。随后，在填充的沟槽上形成导电凸块，其中填充的过孔不在接合焊盘的正下方。在一个实施例中，可以通过使用经构图的光致抗蚀剂作为掩模来等离子体蚀刻电介质层，并在钝化层上停止等离子体蚀刻来执行形成沟槽开口的步骤。以此方式，钝化层不仅可以用以避免湿气和痕量金属污染进入器件晶片，而且还起到蚀刻停止层的作用，在不导致相当大量的钝化层也被去除的情况下，允许等离子体蚀刻过程包含大量的过蚀刻。
现在参考图1-22，参考附图说明了制造3D互连结构的方法。图1中示出了倒置的器件晶片100，其可以包括正表面102和背表面104。器件晶片100可以具有各种形式。例如，器件晶片可以是块状半导体，包括覆盖块状半导体的外延层，或者包括绝缘体上半导体(SOI)结构，尽管可以使用其他结构。在所示的具体实施例中，器件晶片100包括(SOI)结构，其包括覆盖绝缘体层114的半导体层116，以及块状衬底118。器件晶片100可以另外包括掺杂区或者其他掺杂部件，用以形成多个微电子器件，例如，金属绝缘体半导体场效应晶体管(MOSFET)、电容器、电感器、电阻器、二极管、微机电系统(MEMS)、其他适合的有源或无源器件及其组合。
可以在器件晶片100的正表面102上形成金属化结构112。如图所示，金属化结构112包括多个互连层，由诸如铜、铝等的导电金属和诸如氧化硅、碳掺杂氧化物、氮化硅等的中间层电介质材料形成。可以在金属化结构112的上部之上形成钝化层113，以提供物理和化学保护。可以在钝化层113中的开口之上提供一个或多个导电焊盘108(例如，铜、铝等)。
现在参考图2-4，使用市售暂时接合粘合剂208和设备将器件晶片100接合到暂时载体晶片200。随后可以通过对背表面104进行研磨、化学机械抛光(CMP)、等离子体蚀刻和/或湿法蚀刻来对器件晶片100进行减薄。例如，在一个实施例中，可以将器件晶片100减薄到约50-100μm。
在对器件晶片100进行减薄后，可以在背表面104之上形成钝化层120，以提供密封屏障，之后是例如氧化硅的电介质层122，用于极微细间距金属RDL。在一个实施例中，用于钝化层120的适合材料包括碳化硅和氮化硅，因为这些材料可以提供密封屏障，其保护减薄的器件晶片100的背侧104使其免于痕量金属和湿气污染。可以借助诸如化学气相沉积(CVD)之类的适合方法来沉积钝化层120和电介质层122。
现在参加图5-7，将光致抗蚀剂层涂覆在减薄的器件晶片上，对其进行曝光和显影。在显影后，在经构图的光致抗蚀剂层124中，在期望存在包括接合焊盘的微细间距金属RDL的位置处存在开口126。随后使用诸如等离子体蚀刻之类的适合方法来蚀刻沟槽，其中使用经构图的光致抗蚀剂层124作为掩模蚀刻穿过电介质层122的整个深度，在钝化层120上停止。根据双镶嵌工艺流程的一些实施例，在形成RDL的沟槽蚀刻过程期间，碳化硅或氮化硅钝化层120材料可以充当蚀刻停止层，在不导致相当大量的钝化层120也被去除的情况下，允许沟槽蚀刻过程包含大量的过蚀刻。在蚀刻过程后，去除经构图的光致抗蚀剂层124，以清除掉任何剩余的蚀刻聚合物或残留物。
随后将第二光致抗蚀剂层涂覆在减薄的器件晶片上，对其进行曝光和显影。如图8所示，在经构图的光致抗蚀剂层128中，在期望存在过孔(例如，TSV)之处存在开口130。参考图9-10，随后等离子体蚀刻过孔开口，以穿过钝化层120，并穿过在背表面104与正表面102之间的器件晶片100，在金属化结构112内的铜接合焊盘上停止。随后去除经构图的光致抗蚀剂层128，并且可以清除掉任何剩余的蚀刻聚合物或残留物，得到过孔开口132(例如TSV开口)和沟槽开口134(例如RDL开口)。
如图11所示，随后沉积绝缘衬垫层(liner layer)136，以衬垫(lining)过孔开口132和沟槽开口134的底部和侧壁，以及在电介质层122之上的过孔开口之间的区域。用于绝缘衬垫层136的适合材料包括但不限于：二氧化硅、氮化硅、碳化硅和多种聚合物。例如，可以借助CVD、原子层沉积(ALD)和旋涂法来沉积这些材料。如图12所示，随后可以将各向异性等离子体蚀刻过程用于从过孔开口132和沟槽开口134的底表面以及在电介质层122之上的过孔开口之间的区域去除绝缘衬垫层136，同时保持绝缘衬垫层136在过孔开口132的侧表面上的实质厚度。在这个实施例中，可以在由块状硅衬底118限定的过孔开口132侧壁上直接形成绝缘衬垫层136。因而，绝缘衬垫层136在最终的3D互连结构中起作用以使TSV与周围的硅衬底材料绝缘。绝缘衬垫层136的实质厚度在沟槽开口134的侧表面上也可以保持。
参考图13-15，随后可以在器件晶片表面上沉积阻挡层138和晶种层。例如，阻挡层138可以包括钽、钛或钴。例如晶种层可以是铜。随后将铜的均厚层140电镀到器件晶片表面上，以铜完全填充TSV开口132和RDL开口134。如图15所示，随后借助CMP从电介质层122之上去除铜覆盖层和阻挡层。得到的结构包括双镶嵌TSV142和RDL144，其中，TSV142在正表面102与背表面104之间延伸穿过器件晶片100，并且RDL144在背表面104之上形成。在这个双镶嵌结构中，单一金属填料140占据了TSV142和RDL144的总体积，它可以借助阻挡层138和晶种层(例如用于电镀)及绝缘衬垫层136来衬垫。
现在参考图16-19，在RDL144之上形成接合焊盘开口。将钝化层146沉积在该平坦化的表面之上。适合的材料包括但不限于氮化硅，其可以提供针对痕量金属和湿气污染的保护的密封屏障，并且保护RDL144使其免于氧化。随后将光致抗蚀剂材料涂覆在钝化层146之上，并对其进行曝光和显影，以形成经构图的光致抗蚀剂层148。在显影后，在光致抗蚀剂层148中，在RDL144要在期望芯片对芯片连接所至的接合焊盘处终止的那些位置存在开口150。随后使用经构图的光致抗蚀剂层148作为掩模，使用诸如等离子体蚀刻之类的适合技术蚀刻开口，以穿过钝化层146，在底层RDL144接合焊盘152上停止。随后去除光致抗蚀剂层148，并可以清除掉任何剩余的蚀刻聚合物或残留物。
现在参考图20，在每一个露出的RDL144接合焊盘152之上形成导电凸块154。可以实施任何适合的技术以形成导电凸块154，所述技术例如但不限于：焊料凸块形成、使用图案化工艺的电镀、和无电镀覆。在图20所示的特定实施例中，以与焊料相适应的表面终饰层涂覆露出的RDL144接合焊盘152。用于导电凸块154的示例性表面终饰层包括无电镀覆CoP/浸润Au、无电镀覆CoWP/浸润Au、无电镀覆NiP/浸润Au、无电镀覆NiP/无电镀覆Pd/浸润Au、无电镀覆Sn、无电镀覆NiP/无电镀覆Sn、无电镀覆CoP/无电镀覆Sn、无电镀覆CoWP/无电镀覆Sn、无电镀覆Cu/无电镀覆CoP/浸润Au、无电镀覆Cu/无电镀覆CoWP/浸润Au、无电镀覆Cu/无电镀覆NiP/浸润Au、无电镀覆Cu/无电镀覆NiP/无电镀覆Pd/浸润Au、无电镀覆Cu/无电镀覆Sn、无电镀覆Cu/无电镀覆NiP/无电镀覆Sn、无电镀覆Cu/无电镀覆CoP/浸润Au、无电镀覆Cu/无电镀覆CoWP/无电镀覆Sn。取决于所用的芯片对芯片焊料材料和/或芯片对芯片附接方法，其他表面终饰层也可以是适合的。在另一个实施例中，导电凸块154可以是由诸如PbSn、Sn、SnAg、Cu、In、SnAgCu、SnCu、Au等的材料形成的C4或倒装芯片凸块。
随后可以使用市售晶片剥离设备和处理，从器件晶片100去除载体晶片200和粘合剂208，如图21所示的。在去除了载体晶片200和粘合剂208时，可以单个化图21中所示的所得到的多个3D互连结构160，随后可以进一步处理或不处理以形成芯片，芯片可以随后集成到3D封装结构中。
参考图22，示出了根据本发明实施例的示例性标准化芯片对芯片接合焊盘接口，用于将第二芯片连接到3D互连结构。如在放大视图中更详细示出的，将接合焊盘152的阵列以一系列行和列的形式布置在背表面104(参见图21)之上。将TSV142的阵列布置在背表面104之下，以使得TSV的阵列不在接合焊盘152的阵列的正下方。多个RDL144在接合焊盘152的两行之间延伸，将接合焊盘152的两行中的一行连接到TSV阵列中相应数量的TSV142。以此方式，将背侧接合焊盘152连接到正侧电路(金属化结构112)的TSV可以位于芯片上的任何位置。尽管将本发明的实施例描述为TSV的阵列不在接合焊盘的阵列和/或导电凸块的正下方，但会意识到，一些TSV可以在接合焊盘的阵列和/或导电凸块的正下方。本发明的实施例通过结合双镶嵌处理，为TSV的定位提供了灵活性。结果，不需要TSV的阵列的位置在TSV所连接到的相应的接合焊盘的阵列和/或导电凸块的正下方。
为了进一步示出本发明的实施例允许电路设计灵活性的能力，在一个实例中，图22中所示的接合焊盘152的阵列可以具有50μm的垂直间距，和40μm的水平间距，接合焊盘152具有20μm的直径。在这个特定实例中，这留下了30μm，以便在接合焊盘152的两行之间布置六个RDL144。假定这六个RDL线宽和相邻的、RDL144之间的七个间隔相同，每一个RDL144都可以具有2.3μm的线宽。根据本发明实施例的双镶嵌型处理会尤其适合于完成此类示例性微细间距RDL架构，尽管实施例不限于此，且也可以用于任何间距的RDL架构。
图23示出了根据本发明实施例的实施3D互连结构的某些方案的3D封装的说明性实例。如图所示，将多个芯片叠置在诸如印刷电路板或层合衬底的衬底170之上。例如，芯片叠置体可以包括芯片160，其包括如本文所述的3D互连结构，以及叠置在芯片160之上的一个或多个芯片180。在一个实施例中，芯片160是逻辑芯片，包括如本文所述的3D互连结构，芯片180是存储器芯片。3D封装可替换地可以包括叠置在至少一个存储器芯片180之上的逻辑芯片160。如图所示，导电凸块154的阵列以及因此的在导电凸块154之下的接合焊盘152(未示出)与存储器芯片180的接合焊盘182的相应阵列对齐，导电焊盘108与衬底170相连接。会意识到，尽管图23用于例示逻辑芯片160与存储器芯片180的示例性叠置，但本发明的实施例不限于此，可以借助诸如存储器(例如，DRAM、eFLASH、eRAM等)、内插器、RF、MEMS等的适合芯片设想各种芯片对芯片结构。
图24示出了根据本发明实施例的计算机系统。在一些实施例中，系统300包括处理器310、存储器设备320、存储器控制器330、图像控制器340、输入和输出(I/O)控制器350、显示器352、键盘354、指点设备356、和外围设备358，其全部都可以通过总线360可通信地彼此耦合。处理器310可以是通用处理器或专用集成电路(ASIC)。I/O控制器350可以包括通信模块，用于有线或无线通信。存储器设备320可以是动态随机存取存储器(DRAM)设备、静态随机存取存储器(SRAM)设备、闪速存储器设备、或者这些存储器设备的组合。因此，在一些实施例中，系统300中的存储器设备320不必包括DRAM设备。
系统300中所示的一个或多个组件可以包含于和/或可以包括一个或多个集成电路封装，例如图23的芯片160或3D封装。例如，处理器310、或存储器设备320、或至少一部分I/O控制器350、或这些部件的组合可以包含于集成电路封装中，其包括多个实施例中所述的结构的至少一个实施例。
这些元件执行本领域中公知的它们的常规功能。具体地，存储器设备320可以在一些情况下用于为方法的可执行指令提供长期存储，其中所述方法用于形成根据本发明实施例的封装结构；在其他实施例中，存储器设备320可以用于在短期基础上存储方法的可执行指令，其中所述方法用于在处理器310的执行过程中形成根据本发明实施例的封装结构。另外，可以存储指令，或者使指令与机器可存取介质相关联，机器可存取介质与系统可通信地耦合，其例如是紧致盘只读存储器(CD-ROM)、数字多用途盘(DVD)和软盘、载波和/或其他传播信号。在一个实施例中，存储器设备320可以为处理器310提供用于执行的可执行指令。
系统300可以包括计算机(例如台式、膝上型、手持式、服务器、网络设备、路由器等)、无线通信设备(例如，蜂窝电话、无绳电话、寻呼机、个人数字助理等)、与计算机相关的外围设备(例如，打印机、扫描器、监视器等)、娱乐设备(例如，电视机、收音机、立体声系统、磁带和紧致盘播放器、盒式录像机、便携式摄像机、数码相机、MP3(运动图像专家组，音频层3)播放器、视频游戏、手表等)等。
图25示出了根据本发明一个实施例的计算设备400。计算设备400容纳板402。板402可以包括多个部件，包括但不限于：处理器404和至少一个通信芯片406。处理器404物理且电耦合到板402。在一些实现方式中，至少一个通信芯片406也物理且电耦合到板402。在进一步的实现方式中，通信芯片406是处理器404的一部分。
取决于其应用，计算设备400可以包括会或不会物理且电耦合到板402其他部件。这些其他部件包括但不限于：易失性存储器(例如，DRAM)、非易失性存储器(例如ROM)、闪速存储器、图形处理器、数字信号处理器、加密处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)设备、指南针、加速度计、陀螺仪、扬声器、相机和大容量储存设备(例如，硬盘驱动器、紧致盘(CD)、数字多用途盘(DVD)等等)。
通信芯片406实现了无线通信，用于向和从计算设备400传送数据。术语“无线”及其派生词可以用于描述可以通过非固态介质、借助使用调制电磁辐射来传送数据的电路、设备、系统、方法、技术、通信信道等。该术语并非暗示相关设备不包含任何导线，尽管在一些实施例中它们可以不包含。通信芯片406可以实施多个无线标准或协议中的任意一个，包括但不限于，Wi-Fi(IEEE802.11族)、WiMAX(IEEE802.16族)、IEEE802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其衍生物，以及被指定为3G、4G、5G及之后的任何其他无线协议。计算设备400可以包括多个通信芯片406。例如，第一通信芯片406可以专用于近距离无线通信，例如Wi-Fi和蓝牙，第二通信芯片406可以专用于远距离无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他的。
技术设备400的处理器404包括封装在处理器404内的集成电路管芯。在本发明的一些实现方式中，处理器的集成电路管芯可以包含于或可以包括一个或多个集成电路封装，例如图23的芯片160或3D封装。术语“处理器”可以指代任何设备或设备的部分，其处理来自寄存器和/或存储器的电子数据，以将所述电子数据转变为可以存储在寄存器和/或存储器中的其他电子数据。
通信芯片406也包括封装在通信芯片406内的集成电路管芯。根据本发明的另一个实现方式，通信芯片的集成电路管芯可以包含于或可以包括一个或多个集成电路封装，例如图23的芯片160或3D封装。
在进一步的实现方式中，容纳在计算设备400中的另一个部件可以包含集成电路封装，例如图23的芯片160或3D封装。另外，例如，容纳在计算设备400内的处理器404、通信芯片406和其他部件可以叠置在图23的3D封装中。
在多个实现方式中，计算设备400可以是膝上型电脑、上网本、笔记本电脑、超级本电脑、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描器、监视器、机顶盒、娱乐控制单元、数码相机、便携式音乐播放器、或数码摄像机。在进一步的实现方式中，计算设备400可以是处理数据的任何其他电子设备。
尽管以专用于结构特征和/或方法操作的语言说明了本发明，但会理解，在所附权利要求书中限定的本发明不必局限于所述的特定特征或操作。相反，将公开的特定特征和操作理解为对于说明本发明有用的所要求保护的发明的尤其得体的实现方式。

Claims (20)

1.一种3D互连结构，包括：
半导体衬底，所述半导体衬底具有正表面和背表面；以及
双镶嵌过孔和再分布层(RDL)；
其中，所述过孔在所述正表面与所述背表面之间延伸穿过所述半导体衬底，并且所述RDL形成于所述背表面之上。
2.根据权利要求1所述的3D互连结构，进一步包括钝化层，所述钝化层布置在所述背表面与所述RDL之间。
3.根据权利要求2所述的3D互连结构，其中，所述钝化层包括碳化硅或氮化硅。
4.根据权利要求3所述的3D互连结构，其中，所述双镶嵌过孔和所述RDL进一步包括绝缘衬垫层，所述绝缘衬垫层形成于双镶嵌过孔和沟槽开口的侧表面上，但没有形成于所述双镶嵌过孔和所述沟槽开口的底表面上。
5.根据权利要求4所述的3D互连结构，其中，所述双镶嵌过孔和所述RDL进一步包括连续阻挡层，所述连续阻挡层形成于所述双镶嵌过孔和所述沟槽开口的底表面上，并且形成于所述绝缘衬垫层上，其中所述绝缘衬垫层形成于所述双镶嵌过孔和沟槽开口的所述侧表面上。
6.根据权利要求3所述的3D互连结构，进一步包括：
接合焊盘的阵列，所述接合焊盘的阵列以一系列行和列的形式布置在所述背表面之上；
穿硅过孔(TSV)的阵列，所述穿硅过孔的阵列布置在所述背表面之下，以使得TSV的阵列不在所述接合焊盘的阵列的正下方；以及
多个RDL，所述多个RDL在所述接合焊盘的两行之间延伸，将所述两行中的一行连接到所述TSV的阵列中的相应数量的TSV。
7.根据权利要求6所述的3D互连结构，其中，所述接合焊盘的所述两行以10μm到500μm的间距分隔开。
8.一种3D封装，包括：
基底衬底；
芯片堆叠体，所述芯片堆叠体形成于所述基底衬底之上；
其中，所述芯片堆叠体包括芯片，所述芯片包括：
半导体衬底，所述半导体衬底具有正表面和背表面；以及双镶嵌过孔和再分布层(RDL)；
其中，所述过孔在所述半导体衬底的所述正表面与所述背表面之间延伸，并且所述RDL形成于所述背表面之上。
9.根据权利要求8所述的3D封装，其中，所述芯片是逻辑芯片。
10.根据权利要求9所述的3D封装，进一步包括系统，所述系统包括总线，所述总线可通信地耦合到所述3D封装。
11.根据权利要求9所述的3D封装，其中，所述逻辑芯片进一步包括：
接合焊盘的阵列，所述接合焊盘的阵列以一系列行和列的形式布置在所述背表面之上；
穿硅过孔(TSV)的阵列，所述穿硅过孔的阵列布置在所述背表面之下，以使得TSV的阵列不在所述接合焊盘的阵列的正下方；以及
多个RDL，所述多个RDL在所述接合焊盘的两行之间延伸，将所述两行中的一行连接到所述TSV的阵列中的相应数量的TSV。
12.根据权利要求11所述的3D封装，其中，所述接合焊盘的阵列与存储器芯片的相应的接合焊盘的阵列耦合。
13.一种形成双镶嵌3D互连结构的方法，包括：
在器件晶片的背表面之上形成钝化层，其中，所述钝化层包括碳化硅或氮化硅；
在所述钝化层之上形成电介质层；
在所述电介质层中形成沟槽开口；
在所述器件晶片中、在所述器件晶片的所述背表面与所述正表面之间形成过孔开口；
利用导电金属填充所述过孔和沟槽开口的总体积，以形成过孔和包括接合焊盘的再分布层(RDL)，其中，所述过孔不在所述接合焊盘的正下方；以及
在所述接合焊盘之上形成导电凸块。
14.根据权利要求13所述的方法，其中，形成所述沟槽开口包括对所述电介质层进行等离子体蚀刻。
15.根据权利要求14所述的方法，其中，所述等离子体蚀刻包括使用经构图的光致抗蚀剂层作为掩模，以及在所述钝化层上停止所述等离子体蚀刻。
16.根据权利要求13所述的方法，进一步包括将绝缘衬垫层沉积在所述过孔和沟槽开口的侧表面和底表面上。
17.根据权利要求16所述的方法，进一步包括从所述过孔和沟槽开口的所述底表面各向异性地蚀刻所述绝缘衬垫层，同时保持所述过孔开口的所述侧表面上的实质厚度。
18.根据权利要求17所述的方法，其中，利用导电金属填充所述过孔和沟槽开口的总体积包括电镀铜。
19.根据权利要求13所述的方法，进一步包括：
以一系列行和列的形式在所述背表面之上形成接合焊盘的阵列；
在所述背表面之下形成穿硅过孔(TSV)的阵列，以使得TSV的阵列不在所述接合焊盘的阵列的正下方；以及
形成多个RDL，所述多个RDL在所述接合焊盘的两行之间延伸，将所述两行中的一行连接到所述TSV的阵列中的相应数量的TSV。
20.根据权利要求19所述的方法，其中，所述接合焊盘的所述两行以10μm到500μm的间距分隔开。
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