WO2022000438A1 - 一种dram芯片三维集成系统及其制备方法 - Google Patents

一种dram芯片三维集成系统及其制备方法 Download PDF

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WO2022000438A1
WO2022000438A1 PCT/CN2020/099997 CN2020099997W WO2022000438A1 WO 2022000438 A1 WO2022000438 A1 WO 2022000438A1 CN 2020099997 W CN2020099997 W CN 2020099997W WO 2022000438 A1 WO2022000438 A1 WO 2022000438A1
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copper
diffusion barrier
barrier layer
trench
insulating medium
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PCT/CN2020/099997
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English (en)
French (fr)
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朱宝
陈琳
孙清清
张卫
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复旦大学
上海集成电路制造创新中心有限公司
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Priority to US17/052,861 priority Critical patent/US11854939B2/en
Publication of WO2022000438A1 publication Critical patent/WO2022000438A1/zh

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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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Definitions

  • the invention belongs to the field of integrated circuit packaging, and in particular relates to a DRAM chip three-dimensional integrated system and a preparation method thereof.
  • microelectronic packaging technology has gradually become the main factor restricting the development of semiconductor technology.
  • semiconductor technology In order to achieve high density of electronic packaging, obtain better performance and lower overall cost, technicians have developed a series of advanced packaging technologies.
  • the three-dimensional system-in-package technology has good electrical performance and high reliability, and can achieve high packaging density at the same time, and is applied to dynamic random access memory (DRAM) chip systems.
  • DRAM dynamic random access memory
  • TSV interposer technology is a new technology for stacking chips in three-dimensional integrated circuits to achieve interconnection. Layer, RDL for short) to realize the electrical interconnection between different chips.
  • TSV interposer technology can make DRAM chips have the highest stacking density in three-dimensional direction, the shortest interconnection between chips, and the smallest external size, and greatly improve the performance of chip storage density, speed and low power consumption. It is the current electronic packaging technology. one of the most striking technologies.
  • the silicon wafer is usually thinned first, then the TSV structure is fabricated, and finally the chips are stacked vertically. The thinning of silicon wafers will undoubtedly increase the complexity of the process, cause waste of silicon materials, and be prone to warping and deformation problems.
  • the present invention discloses a three-dimensional integrated system of DRAM chips, comprising: a top trench, a bottom trench and a TSV through a silicon substrate, wherein the TSV is connected to the top trench and the TSV. the bottom groove;
  • first insulating medium a first insulating medium, a first copper diffusion barrier layer and a copper seed layer
  • the first insulating medium covers the bottom trench and is discontinuous at the bottom of the TSV
  • the first copper diffusion A barrier layer is formed on the first insulating medium
  • the copper seed layer covers the first copper diffusion barrier layer and presents a continuous film state
  • the first copper diffusion barrier layer and the copper seed layer Disconnect at the area adjacent to the bottom trench for insulation
  • a second insulating medium, a second copper diffusion barrier layer, a copper thin film, and a conductive copper pillar wherein the second insulating medium covers the top trench and the sidewalls of the TSV, and is located in the TSV
  • the top and bottom are in discontinuous state
  • the second copper diffusion barrier layer is formed on the second insulating medium
  • the copper film covers the second copper diffusion barrier layer in the top trench and presents Continuous film state
  • the conductive copper pillars cover the second copper diffusion barrier on the sidewalls of the TSVs and completely fill the TSVs, the tops of which are in contact with the copper film and the bottoms are in contact with the copper the seed layer is in contact
  • the second copper diffusion barrier layer and the copper film are disconnected at the adjacent area of the top trench to achieve insulation
  • the DRAM chip is respectively bonded with the copper seed layer and the copper thin film through the contact bump; the filler fills the DRAM the gap between the chip, the copper seed layer and the copper thin film; the redistribution layer covers the top and bottom of the three-dimensional integrated system.
  • the first insulating medium and the second insulating medium are at least one of SiO 2 , Si 3 N 4 , SiOCH, and SiOCFH.
  • the first copper diffusion barrier layer and the second copper diffusion barrier layer are at least one of TaN, TiN, ZrN, and MnSiO 3 .
  • the filler is epoxy resin.
  • the invention also discloses a method for preparing a three-dimensional integrated system of a DRAM chip, comprising the following steps: forming a top trench and a bottom trench by photolithography and etching on the front and back of a single crystal silicon substrate; depositing sequentially in the bottom trench a first insulating medium, a first copper diffusion barrier layer and a copper seed layer; etching the silicon substrate between the top trench and the bottom trench to pass through to form a TSV;
  • the first insulating medium and the second insulating medium are at least one of SiO 2 , Si 3 N 4 , SiOCH, and SiOCFH.
  • the first copper diffusion barrier layer and the second copper diffusion barrier layer are at least one of TaN, TiN, ZrN, and MnSiO 3 .
  • the filler is epoxy resin.
  • the present invention can make full use of the silicon material, and can avoid problems such as warpage and deformation of the adapter plate.
  • placing the chip in the trench will not increase the overall package thickness, but also prevent the chip from being impacted by external forces.
  • FIG. 1 is a flow chart of a method for preparing a three-dimensional integrated system of a DRAM chip.
  • 2 to 13 are schematic structural diagrams of each step of a method for fabricating a three-dimensional integrated system of a DRAM chip.
  • FIG. 1 is a flow chart of a method for preparing a three-dimensional integrated system of DRAM chips
  • FIGS. 2-13 are schematic structural diagrams of each step of the method for preparing a three-dimensional integrated system of DRAM chips. As shown in Figure 1, the specific preparation steps are:
  • step S1 trenches are formed by etching on the silicon substrate.
  • photoresist is spin-coated on the front and back of the monocrystalline silicon substrate 200 and the positions of the top and bottom trenches are defined through exposure and development processes.
  • the trench structure is etched by a reactive ion etching process, and the obtained structure is shown in FIG. 2 .
  • the reactive ions for etching the silicon substrate 200 may be selected from at least one of CF 4 and SF 6 .
  • a reactive ion etching process is used to obtain the trench structure, but the present invention is not limited to this, and dry etching such as ion milling etching, plasma etching, reactive ion etching, and laser ablation can be selected, Or by at least one process of wet etching using an etchant solution.
  • step S2 a first insulating medium, a first copper diffusion barrier layer and a copper seed layer are deposited on the bottom trench.
  • a physical vapor deposition process in the bottom of the trench are sequentially deposited SiO 2 film, TaN film and a Cu film as a first insulating dielectric 201, a first copper diffusion barrier layer 202 and the copper seed layer 203, the resultant structure shown in Figure 3 Show.
  • the SiO 2 film is used as the first insulating medium
  • the TaN film is used as the first copper diffusion barrier layer
  • the present invention is not limited to this, and SiO 2 , Si 3 N 4 , low dielectric constant materials ( For example, at least one of SiOCH and SiOCFH) is used as the first insulating medium, and at least one of TaN, TiN, ZrN, and MnSiO 3 is selected as the first copper diffusion barrier layer.
  • a TSV is formed by etching between the top trench and the bottom trench.
  • a photoresist is spin-coated inside the top trench and the position of the TSV is defined by an exposure and development process.
  • the silicon substrate 200 between the top and bottom trenches is etched by using a deep plasma etching (DRIE) process until the first insulating medium 201 is contacted.
  • the photoresist is removed by dissolving or ashing in a solvent, and the resulting structure is shown in FIG. 4 .
  • the plasma for etching the silicon substrate 200 may be at least one of CF 4 and SF 6 .
  • a deep reactive ion etching process is used to obtain the trench structure, but the present invention is not limited to this, and dry etching such as ion milling etching, plasma etching, reactive ion etching, deep reactive ion etching can be selected. At least one of etching, laser ablation, or wet etching by using an etchant solution.
  • a second insulating medium and a second copper diffusion barrier layer are deposited in the top trench and TSV.
  • the first insulating dielectric 201 and the first copper at the bottom of the TSV are removed by dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or by a wet etching process using an etchant solution
  • the barrier layer 202 is diffused, thereby exposing the copper seed layer 203, and the resulting structure is shown in FIG. 5 .
  • a SiO 2 film and a TaN film are sequentially deposited on the top trench and TSV surface by chemical vapor deposition process as the second insulating medium 204 and the second copper diffusion barrier layer 205 respectively.
  • the resulting structure is shown in FIG. 6 .
  • the second insulating dielectric 204 and the second copper at the bottom of the TSV are removed by dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or by a wet etching process using an etchant solution
  • the barrier layer 205 is diffused, thereby exposing the copper seed layer 203, and the resulting structure is shown in FIG. 7 .
  • the SiO 2 film is used as the second insulating medium
  • the TaN film is used as the second copper diffusion barrier layer
  • the present invention is not limited to this, and SiO 2 , Si 3 N 4 , low dielectric constant materials (for example, at least one of SiOCH and SiOCFH) is used as the second insulating medium, and at least one of TaN, TiN, ZrN, and MnSiO 3 is selected as the second copper diffusion barrier layer.
  • step S5 conductive copper pillars are formed by electroplating in the TSV, and a copper film is deposited in the top trench.
  • the copper seed layer 203 is used as the seed layer, and copper material is electroplated on its surface by an electroplating process.
  • the copper material completely fills the TSV and is aligned with the upper surface of the second copper diffusion barrier layer 205 at the bottom of the top trench.
  • the conductive copper pillars 206 are formed, and the resulting structure is shown in FIG. 8 .
  • a copper film 207 is deposited in the top trench by a physical vapor deposition process, and the resulting structure is shown in FIG. 9 .
  • step S6 a DRAM chip is embedded in the trench and bonded to the TSV structure and rewired.
  • photolithography and etching are used to remove the first copper diffusion barrier layer 202 and the copper seed layer 203 in the area connected to the adjacent bottom trenches, and the second copper diffusion barrier layer 205 and the copper film 207 in the area connected to the top trenches , the resulting structure is shown in Figure 10.
  • the DRAM chip 208 with the copper contact bumps 209 is placed inside the trench, and then copper-copper bonding is performed in the temperature range of 300-400° C., that is to say, the copper contact bumps 209 are respectively connected with the copper film.
  • FIG. 11 epoxy resin 210 is filled in the gaps between the DRAM chip 208 and the top trench and the bottom trench as a buffer layer and an isolation layer, and the resulting structure is shown in FIG. 12 .
  • redistribution layers 211 are formed on the top and bottom of the above structure, so that the DRAM chips in the horizontal direction are electrically connected, and the resulting structure is shown in FIG. 13 .
  • a three-dimensional integration system of a DRAM chip of the present invention includes: a top trench, a bottom trench and a TSV through the silicon substrate 200, wherein the TSV connects the top trench and the bottom groove;
  • a first insulating medium 201, a first copper diffusion barrier layer 202 and a copper seed layer 203 wherein the first insulating medium 201 covers the bottom trench and is discontinuous at the bottom of the TSV; the first copper diffusion barrier layer 202 covers The first insulating medium 201; the copper seed layer 203 covers the first copper diffusion barrier layer 202 and presents a continuous film state; the first copper diffusion barrier layer 202 and the copper seed layer 203 are disconnected at the adjacent area of the bottom trench , to achieve insulation;
  • the second copper diffusion barrier layer 205 covers the second insulating medium 204; the copper film 207 covers the second copper diffusion barrier layer 205 in the top trench, and presents a continuous film state; the conductive copper pillar 206 covers the side of the TSV
  • the gap between the copper seed layer 203 and the copper thin film 207; the redistribution layer 211 covers the top and bottom of the three-dimensional integrated system.
  • the first insulating medium and the second insulating medium are SiO 2 , Si 3 N 4 , SiOCH, SiOCFH and the like.
  • the first copper diffusion barrier layer and the second copper diffusion barrier layer are at least one of TaN, TiN, ZrN, and MnSiO 3 .
  • the filler is epoxy resin.
  • the silicon wafer for manufacturing the transition board does not need to be thinned, so the process steps can be reduced, the silicon material can be fully utilized, and the transition board does not have the problem of warpage and deformation.
  • the overall package thickness is not increased, and the chip can be protected from external impact.
  • the electrical communication of the DRAM chips in the vertical direction is achieved by using the TSV structure between the upper and lower facing trenches.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

本发明公开了一种DRAM芯片三维集成系统及其制备方法。在硅片正反面刻蚀出若干个沟槽结构；然后，在上下相对的两个沟槽之间刻蚀出TSV结构进行电气连通；接着，在沟槽内放置DRAM芯片，并采用铜-铜键合的方式使得垂直方向上芯片与TSV结构电气连通；最后进行重布线，使得水平方向上的芯片之间电气连通。本发明能够充分利用硅材料，而且可以避免转接板出现翘曲、变形等问题。此外，将芯片放置在沟槽内，既不会增大整体封装厚度，又能保护芯片不会受到外力冲击。

Description

一种DRAM芯片三维集成系统及其制备方法 技术领域
本发明属于集成电路封装领域，具体涉及一种DRAM芯片三维集成系统及其制备方法。
背景技术
随着集成电路工艺技术的高速发展，微电子封装技术逐渐成为制约半导体技术发展的主要因素。为了实现电子封装的高密度化，获得更优越的性能和更低的总体成本，技术人员研究出一系列先进的封装技术。其中，三维系统级封装技术具有良好的电学性能以及较高的可靠性，同时能实现较高的封装密度，被应用于动态随机存储器(DRAM)芯片系统。
硅通孔(Through Silicon Via，简称TSV)转接板技术是三维集成电路中堆叠芯片实现互连的一种新技术，通过在硅圆片上制作出许多垂直互连通孔以及后续重布线(Redistribution Layer，简称RDL)来实现不同芯片之间的电互连。TSV转接板技术能够使DRAM芯片在三维方向堆叠的密度最大、芯片之间的互连线最短、外形尺寸最小，并且大大改善芯片存储密度、速度和低功耗的性能，是目前电子封装技术中最引人注目的一种技术。然而，为了满足封装总体厚度的要求，通常会将硅片先进行减薄，然后制作TSV结构，最后在垂直方向上堆叠芯片。硅片减薄无疑将增加工艺复杂度，造成硅材料的浪费，而且还容易出现翘曲变形的问题。
发明内容
为了解决上述问题，本发明公开一种DRAM芯片三维集成系统，包括：贯通硅衬底的顶部沟槽、底部沟槽和硅通孔，其中，所述硅通孔连接着所述顶部沟槽和所述底部沟槽；
第一绝缘介质、第一铜扩散阻挡层和铜籽晶层，其中，所述第一绝缘介质覆盖所述底部沟槽，并在所述硅通孔底部处不连续；所述第一铜扩散阻挡 层形成在所述第一绝缘介质上；所述铜籽晶层覆盖所述第一铜扩散阻挡层，并呈现出连续薄膜状态；所述第一铜扩散阻挡层和所述铜籽晶层在底部沟槽相邻区域处断开，以实现绝缘；
第二绝缘介质、第二铜扩散阻挡层、铜薄膜和导电铜柱，其中，所述第二绝缘介质覆盖所述顶部沟槽和所述硅通孔的侧壁，并在所述硅通孔顶部和底部呈不连续状态；所述第二铜扩散阻挡层形成在所述第二绝缘介质上；所述铜薄膜覆盖所述顶部沟槽内的所述第二铜扩散阻挡层，并呈现出连续薄膜状态；所述导电铜柱覆盖所述硅通孔侧壁的所述第二铜扩散阻挡层，并且完全填充所述硅通孔，其顶部与所述铜薄膜接触，底部与所述铜籽晶层接触；所述第二铜扩散阻挡层和所述铜薄膜在顶部沟槽相邻区域处断开，以实现绝缘；
DRAM芯片、接触凸点、填充物和重布线层，其中，所述DRAM芯片通过所述接触凸点分别与所述铜籽晶层以及所述铜薄膜键合；所述填充物填充所述DRAM芯片与所述铜籽晶层以及所述铜薄膜之间的间隙；所述重布线层覆盖三维集成系统的顶部和底部。
本发明的DRAM芯片三维集成系统中，优选为，所述第一绝缘介质、所述第二绝缘介质为SiO 2、Si 3N 4、SiOCH、SiOCFH中的至少一种。
本发明的DRAM芯片三维集成系统中，优选为，所述第一铜扩散阻挡层、所述第二铜扩散阻挡层为TaN、TiN、ZrN、MnSiO 3中的至少一种。
本发明的DRAM芯片三维集成系统中，优选为，所述填充物为环氧树脂。
本发明还公开一种DRAM芯片三维集成系统制备方法，包括以下步骤：在单晶硅衬底正面和背面光刻、刻蚀形成顶部沟槽和底部沟槽；在所述底部沟槽内依次沉积第一绝缘介质、第一铜扩散阻挡层和铜籽晶层；刻蚀所述顶部沟槽和所述底部沟槽之间的硅衬底，使之贯通形成硅通孔；
去除所述硅通孔底部的所述第一绝缘介质和第一铜扩散阻挡层，从而暴露出铜籽晶层；在顶部沟槽和硅通孔表面依次沉积第二绝缘介质和第二铜扩 散阻挡层；去除位于硅通孔底部的第二绝缘介质和第二铜扩散阻挡层，从而暴露出铜籽晶层；在所述铜籽晶层表面电镀铜材料，使其完全填充所述硅通孔并与位于所述顶部沟槽的底部的第二铜扩散阻挡层的上表面齐平，从而形成导电铜柱；在所述顶部沟槽表面沉积铜薄膜；
去除相邻底部沟槽相连区域的第一铜扩散阻挡层和铜籽晶层，以及相邻顶部沟槽相连区域的第二铜扩散阻挡层和铜薄膜；将所述DRAM芯片的接触凸点分别与所述铜籽晶层以及所述铜薄膜键合；在所述DRAM芯片与沟槽之间的间隙填充填充物，作为缓冲层和隔离层；在上述结构的顶部和底部制作重布线层，使得水平方向上的DRAM芯片电气连通。
本发明的DRAM芯片三维集成系统制备方法中，优选为，所述第一绝缘介质、所述第二绝缘介质为SiO 2、Si 3N 4、SiOCH、SiOCFH中的至少一种。
本发明的DRAM芯片三维集成系统制备方法中，优选为，所述第一铜扩散阻挡层、所述第二铜扩散阻挡层为TaN、TiN、ZrN、MnSiO 3中的至少一种。
本发明的DRAM芯片三维集成系统制备方法中，优选为，所述填充物为环氧树脂。
本发明能够充分利用硅材料，而且可以避免转接板出现翘曲、变形等问题。此外，将芯片放置在沟槽内，既不会增大整体封装厚度，又能防止芯片受到外力冲击。
附图说明
图1是DRAM芯片三维集成系统制备方法的流程图。
图2～图13是DRAM芯片三维集成系统制备方法各步骤的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，应当理解， 此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
在本发明的描述中，需要说明的是，术语“上”、“下”、“垂直”“水平”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
此外，在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。除非在下文中特别指出，器件中的各个部分可以由本领域的技术人员公知的材料构成，或者可以采用将来开发的具有类似功能的材料。
以下结合附图1-13和实施例对本发明的技术方案做进一步的说明。图1是DRAM芯片三维集成系统制备方法的流程图，图2-13示出了DRAM芯片三维集成系统制备方法各步骤的结构示意图。如图1所示，具体制备步骤为：
在步骤S1中，在硅衬底上刻蚀形成沟槽。首先，在单晶硅衬底200正面和背面旋涂光刻胶并通过曝光和显影工艺定义出顶部和底部沟槽的位置。然后，采用反应离子刻蚀工艺刻蚀出沟槽结构，所得结构如图2所示。刻蚀硅衬底200的反应离子体可以选择CF 4、SF 6中的至少一种。在本实施方式中采用反应离子刻蚀工艺来获得沟槽结构，但是本发明不限定于此，可以选择干法刻蚀比如离子铣刻蚀、等离子刻蚀、反应离子刻蚀、激光烧蚀，或者通过使用蚀刻剂溶液的湿法刻蚀中的至少一种工艺。
在步骤S2中，在底部沟槽淀积第一绝缘介质、第一铜扩散阻挡层和铜籽晶层。采用物理气相沉积工艺在底部沟槽内依次沉积SiO 2薄膜、TaN薄膜和Cu薄膜，分别作为第一绝缘介质201、第一铜扩散阻挡层202和铜籽晶层203，所得结构如图3所示。在本实施方式中采用SiO 2薄膜作为第一绝缘介质，采用TaN薄膜作为第一铜扩散阻挡层，但是本发明不限定于此，可以选择SiO 2、 Si 3N 4、低介电常数材料(如SiOCH、SiOCFH)中的至少一种作为第一绝缘介质，选择TaN、TiN、ZrN、MnSiO 3中的至少一种作为第一铜扩散阻挡层。
在步骤S3中，在顶部沟槽和底部沟槽之间刻蚀形成硅通孔。首先，在顶部沟槽内部旋涂光刻胶并通过曝光和显影工艺定义出硅通孔的位置。然后，采用深度等离子体刻蚀(DRIE)工艺对顶部和底部沟槽之间的硅衬底200进行刻蚀，直到接触到第一绝缘介质201。最后，在溶剂中溶解或灰化去除光刻胶，所得结构如图4所示。其中，刻蚀硅衬底200的等离子体可以选择CF 4、SF 6中的至少一种。在本实施方式中采用深度反应离子刻蚀工艺来获得沟槽结构，但是本发明不限定于此，可以选择干法刻蚀比如离子铣刻蚀、等离子刻蚀、反应离子刻蚀、深度反应离子刻蚀、激光烧蚀，或者通过使用蚀刻剂溶液的湿法刻蚀中的至少一种工艺。
在步骤S4中，在顶部沟槽和硅通孔内淀积第二绝缘介质和第二铜扩散阻挡层。首先，通过干法刻蚀如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过使用蚀刻剂溶液的湿法蚀刻工艺去除位于硅通孔底部的第一绝缘介质201和第一铜扩散阻挡层202，从而暴露出铜籽晶层203，所得结构如图5所示。然后，采用化学气相沉积工艺在顶部沟槽和硅通孔表面依次沉积SiO 2薄膜和TaN薄膜，分别作为第二绝缘介质204和第二铜扩散阻挡层205，所得结构如图6所示。接着，通过干法刻蚀如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过使用蚀刻剂溶液的湿法蚀刻工艺去除位于硅通孔底部的第二绝缘介质204和第二铜扩散阻挡层205，从而暴露出铜籽晶层203，所得结构如图7所示。在本实施方式中采用SiO 2薄膜作为第二绝缘介质，采用TaN薄膜作为第二铜扩散阻挡层，但是本发明不限定于此，可以选择SiO 2、Si 3N 4、低介电常数材料(如SiOCH、SiOCFH)中的至少一种作为第二绝缘介质，选择TaN、TiN、ZrN、MnSiO 3中的至少一种作为第二铜扩散阻挡层。
在步骤S5中，在硅通孔内电镀形成导电铜柱，以及在顶部沟槽内淀积铜薄膜。首先，以铜籽晶层203为籽晶层，采用电镀工艺在其表面电镀铜材料，铜材料完全填充硅通孔并与位于顶部沟槽的底部的第二铜扩散阻挡层205的上表面齐平，从而形成导电铜柱206，所得结构如图8所示。最后，采用物理气相沉积工艺在顶部沟槽内沉积铜薄膜207，所得结构如图9所示。
在步骤S6中，在沟槽内置入DRAM芯片并与TSV结构键合以及重布线。首先，采用光刻和刻蚀工艺去除相邻底部沟槽相连区域的第一铜扩散阻挡层202和铜籽晶层203，以及顶部沟槽相连区域的第二铜扩散阻挡层205和铜薄膜207，所得结构如图10所示。进一步，将带有铜接触凸点209的DRAM芯片208放置在沟槽内部，然后，在300～400℃的温度范围内进行铜-铜键合，也就是说铜接触凸点209分别与铜薄膜207和铜籽晶层203在加热条件下发生键合，所得结构如图11所示。接着，在DRAM芯片208与顶部沟槽以及底部沟槽的空隙内填充环氧树脂210作为缓冲层和隔离层，所得结构如图12所示。最后，在上述结构的顶部和底部制作重布线层211，使得水平方向上的DRAM芯片电气连通，所得结构如图13所示。
如图13所示，本发明的一种DRAM芯片三维集成系统包括：贯通硅衬底200的顶部沟槽、底部沟槽和硅通孔，其中，硅通孔连接着顶部沟槽和所述底部沟槽；
第一绝缘介质201、第一铜扩散阻挡层202和铜籽晶层203，其中，第一绝缘介质201覆盖底部沟槽，并在硅通孔底部处不连续；第一铜扩散阻挡层202覆盖第一绝缘介质201；铜籽晶层203覆盖第一铜扩散阻挡层202，并呈现出连续薄膜状态；第一铜扩散阻挡层202和铜籽晶层203在底部沟槽相邻区域处断开，以实现绝缘；
第二绝缘介质204、第二铜扩散阻挡层205、铜薄膜207和导电铜柱206，其中，第二绝缘介质204覆盖顶部沟槽和硅通孔，并在硅通孔的顶部和底部呈不连续状态；第二铜扩散阻挡层205覆盖第二绝缘介质204；铜薄膜207覆盖顶部沟槽内的第二铜扩散阻挡层205，并呈现出连续薄膜状态；导电铜柱206覆盖硅通孔侧壁的第二铜扩散阻挡层205，并且完全填充硅通孔，其顶部与铜薄膜207接触，底部与铜籽晶层203接触；第二铜扩散阻挡层205和铜薄膜207在顶部沟槽相邻区域处断开，以实现绝缘；
DRAM芯片208、接触凸点209、填充物210和重布线层211，其中，DRAM芯片208通过接触凸点209分别与铜籽晶层203以及铜薄膜207键合；填充物210填充DRAM芯片208与铜籽晶层203以及铜薄膜207之间的间隙；重布线层211覆盖三维集成系统的顶部和底部。
优选地，第一绝缘介质、第二绝缘介质为SiO 2、Si 3N 4、SiOCH、SiOCFH 等。第一铜扩散阻挡层、第二铜扩散阻挡层为TaN、TiN、ZrN、MnSiO 3中的至少一种。填充物为环氧树脂。
本发明制造转接板的硅片无需减薄，因此可以减少工艺步骤，还可以充分利用硅材料，而且转接板不会出现翘曲和变形的问题。此外，通过在转接板上刻蚀出沟槽，并在沟槽内放置芯片，既不会增大整体封装厚度，又能保护芯片不受外力冲击。另外，利用在上下两个正对的沟槽之间的TSV结构，实现垂直方向上DRAM芯片的电学连通。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。

Claims (8)

  1. 一种DRAM芯片三维集成系统，其特征在于，
    包括：
    贯通硅衬底(200)的顶部沟槽、底部沟槽和硅通孔，其中，所述硅通孔连接所述顶部沟槽和所述底部沟槽；
    第一绝缘介质(201)、第一铜扩散阻挡层(202)和铜籽晶层(203)，其中，所述第一绝缘介质(201)覆盖所述底部沟槽，并在所述硅通孔底部处不连续；所述第一铜扩散阻挡层(202)形成在所述第一绝缘介质(201)上；所述铜籽晶层(203)覆盖所述第一铜扩散阻挡层(202)，并呈现出连续薄膜状态；所述第一铜扩散阻挡层(202)和所述铜籽晶层(203)在相邻底部沟槽的连接区域处断开，以实现绝缘；
    第二绝缘介质(204)、第二铜扩散阻挡层(205)、铜薄膜(207)和导电铜柱(206)，其中，所述第二绝缘介质(204)覆盖所述顶部沟槽和所述硅通孔，并在所述硅通孔的底部呈不连续状态；所述第二铜扩散阻挡层(205)覆盖所述第二绝缘介质(204)；所述铜薄膜(207)覆盖所述顶部沟槽内的所述第二铜扩散阻挡层(205)，并呈现出连续薄膜状态；所述导电铜柱(206)覆盖所述硅通孔侧壁的所述第二铜扩散阻挡层(205)，并且完全填充所述硅通孔，其顶部与所述铜薄膜(207)接触，底部与所述铜籽晶层(203)接触；所述第二铜扩散阻挡层(205)和所述铜薄膜(207)在相邻顶部沟槽的连接区域处断开，以实现绝缘；
    DRAM芯片(208)、接触凸点(209)、填充物(210)和重布线层(211)，其中，所述DRAM芯片(208)通过所述接触凸点(209)分别与所述铜籽晶层(203)以及所述铜薄膜(207)键合；所述填充物(210)填充所述DRAM芯片(208)与沟槽之间的间隙；所述重布线层(211)覆盖三维集成系统的顶部和底部。
  2. 根据权利要求1所述的DRAM芯片三维集成系统，其特征在于，
    所述第一绝缘介质(201)、所述第二绝缘介质(204)为SiO 2、Si 3N 4、SiOCH、SiOCFH中的至少一种。
  3. 根据权利要求1所述的DRAM芯片三维集成系统，其特征在于，
    所述第一铜扩散阻挡层(202)、所述第二铜扩散阻挡层(205)为TaN、TiN、ZrN、MnSiO 3中的至少一种。
  4. 根据权利要求1所述的DRAM芯片三维集成系统，其特征在于，
    所述填充物(210)为环氧树脂。
  5. 一种DRAM芯片三维集成系统制备方法，其特征在于，
    包括以下步骤：
    在单晶硅衬底(200)正面和背面光刻、刻蚀形成顶部沟槽和底部沟槽；
    在所述底部沟槽内依次沉积第一绝缘介质(201)、第一铜扩散阻挡层(202)和铜籽晶层(203)；
    刻蚀所述顶部沟槽和所述底部沟槽之间的硅衬底，使之贯通形成硅通孔；
    去除所述硅通孔底部的所述第一绝缘介质(201)和第一铜扩散阻挡层(202)，从而暴露出铜籽晶层(203)；在顶部沟槽和硅通孔表面依次沉积第二绝缘介质(204)和第二铜扩散阻挡层(205)；
    去除位于硅通孔底部的第二绝缘介质(204)和第二铜扩散阻挡层(205)，从而暴露出铜籽晶层(203)；在所述铜籽晶层(203)表面电镀铜材料，使其完全填充所述硅通孔并与位于所述顶部沟槽的底部的第二铜扩散阻挡层(205)的上表面齐平，从而形成导电铜柱(206)；在所述顶部沟槽表面沉积铜薄膜(207)；
    去除相邻底部沟槽相连区域的第一铜扩散阻挡层(202)和铜籽晶层(203)，以及相邻顶部沟槽相连区域的第二铜扩散阻挡层(205)和铜薄膜(207)；将所述DRAM芯片(208)的接触凸点(209)分别与所述铜籽晶层(203)以及所述铜薄膜(207)键合；在所述DRAM芯片(208)与沟槽之间的间隙填充填充物(210)，作为缓冲层和隔离层；在上述结构的顶部和底部制作重布线层(211)，使得水平方向上的DRAM芯片电气连通。
  6. 根据权利要求5所述的DRAM芯片三维集成系统制备方法，其特征在于，
    所述第一绝缘介质(201)、所述第二绝缘介质(204)为SiO 2、Si 3N 4、SiOCH、SiOCFH中的至少一种。
  7. 根据权利要求5所述的DRAM芯片三维集成系统制备方法，其特征在于，
    所述第一铜扩散阻挡层(202)、所述第二铜扩散阻挡层(205)为TaN、TiN、ZrN、MnSiO 3中的至少一种。
  8. 根据权利要求5所述的DRAM芯片三维集成系统制备方法，其特征在于，
    所述填充物(210)为环氧树脂。
PCT/CN2020/099997 2020-06-30 2020-07-02 一种dram芯片三维集成系统及其制备方法 WO2022000438A1 (zh)

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