CN101924096A - 硅通孔结构及其形成工艺 - Google Patents
硅通孔结构及其形成工艺 Download PDFInfo
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Abstract
本发明公开了一种硅通孔(TSV)结构及其形成工艺。半导体衬底具有前表面和后表面,并且TSV结构被形成为延伸穿过半导体衬底。TSV结构包括金属层、围绕金属层的金属晶种层、围绕金属晶种层的阻挡层以及形成在金属层和金属晶种层之间夹置的部分中的金属硅化物层。
Description
相关申请的交叉参考
本申请要求于2009年6月12日提交的美国临时专利申请No.61/186,575的优先权,其全部内容结合于此作为参考。
技术领域
本发明涉及堆叠集成电路,尤其涉及用于三维堆叠技术的硅通孔(through-silicon via)工艺。
背景技术
三维(3D)晶圆-晶圆、管芯-晶圆或者管芯-管芯垂直堆叠技术设法实现垂直堆叠多层有源IC器件(诸如,处理器、可编程器件和存储器件)以缩短平均线长度,从而减小互连RC延迟并提高系统性能的期待已久的目标。在单个晶圆上或者在管芯-晶圆垂直堆叠中的3D互连的一个主要挑战是硅通孔(TSV)为高阻抗信号提供了从晶圆的一侧穿到另一侧的信号路径。硅通孔(TSV)通常被制造成提供填充有导电材料的硅通孔,其中,导电材料完全通过该层以与其他TSV和多个接合层的导体接触并连接。通常,铜已经成为为金属化TSV所选择的金属,这是因为铜具有比最常用的金属更低的电阻率和更高的载流容量。这些特性对于支持在高集成水平和提高的器件速度下经历的更高电流密度来说是重要的。而且,铜具有良好的热导率并且在高纯态下可用。之前尝试利用具有大于3∶1的高纵横比的TSV进行填充,然而,通常生产出存在缺陷的TSV,诸如在导电插塞中产生空隙(void)或缝隙(seam)。空隙或缝隙在电子器件的制造期间会引起一系列问题。可靠地生产TSV是三维堆叠技术的关键技术之一。因此,目前正在进行大量努力针对无空隙部件的形成。
发明内容
根据本发明的一个方面,提供了一种器件,包括:半导体衬底,具有前表面和后表面,并包括形成在前表面上的集成电路(IC)组件;层间电介质(ILD)层,被形成为上覆半导体衬底的所述前表面;接触插塞,形成在ILD层中,并且电连接至IC组件;以及通孔结构,形成在ILD层中,并且延伸穿过半导体衬底,其中,通孔结构包括金属层、围绕金属层的金属晶种层、围绕金属晶种层的阻挡层以及夹置在金属层的至少一部分和金属晶种层的至少一部分之间的金属硅化物层。
优选地,金属硅化物层包括铜;或者金属层包括铜,并且金属晶种层包括铜;或者阻挡层包括TaN、Ta、TiN、Ti或它们的组合。
优选地,通孔结构包括围绕阻挡层的钝化层,其中,钝化层包括硅氧化物。
优选地,通孔结构包括在半导体衬底的后表面上露出的端部。
此外,该器件还包括:半导体组件,堆叠在半导体衬底的后表面上并且电连接至通孔结构。
根据本发明的另一方面,提供了一种半导体器件,包括:半导体衬底,具有前表面和后表面,并包括形成在前表面上的集成电路(IC)组件;层间电介质(ILD)层,被形成为上覆半导体衬底的前表面;接触插塞,形成在ILD层中,并且电连接至IC组件;以及通孔结构,形成在ILD层中,并且延伸穿过半导体衬底;其中,通孔结构包括铜层、围绕铜层的铜晶种层、围绕铜晶种层的阻挡层以及夹置在铜层的至少一部分和铜晶种层的至少一部分之间的铜硅化物层;以及其中,通孔结构包括在半导体衬底的后表面上露出的端部。
优选地,阻挡层包括TaN、Ta、TiN、Ti或它们的组合。
该半导体器件还包括:围绕阻挡层的钝化层,其中,钝化层包括硅氧化物。
该半导体器件还包括:背侧介电层,被形成为上覆所述半导体衬底的后表面;以及外部接触,形成在背侧介电层上,其中,外部接触包括焊锡凸块、含铜凸块或它们的组合。
根据本发明的又一方面,提供了一种工艺,包括:形成从半导体衬底的前表面延伸到半导体衬底的至少一部分的开口,其中,开口具有大于5的纵横比;在开口中形成金属晶种层,其中,金属晶种层包括与开口的侧壁部分邻近的侧壁部分和与开口的底部邻近的底部部分;在金属晶种层的侧壁部分的至少一部分上形成金属硅化物层;以及在金属硅化物层和金属晶种层上电镀金属层,以填充开口。
优选地,金属硅化物层未形成在金属晶种层的底部部分上。
优选地,金属晶种层、金属硅化物层和金属层中的每一个都包括铜。
此外,该工艺还包括:在形成金属晶种层之前,形成对开口加衬的阻挡层;在形成阻挡层之前,形成对开口加衬的钝化层。
此外,该工艺还包括:对半导体衬底的后表面执行薄化工艺以露出金属层。
附图说明
本发明的上述目标、特征和优点将通过参照以下结合附图对实施例的详细描述而变得显而易见,其中:
图1至图7是示出TSV工艺的示例性实施例的截面图;以及
图8至图10是示出使用TSV结构的三维堆叠工艺的示例性实施例的截面图。
具体实施方式
实施例提供了用于填充高纵横比开口的金属化工艺和使用该工艺形成以避免在其中生成缝隙或空隙缺陷的结构。术语“纵横比”用于描述形成在金属层中的任何开口的高度-宽度比。本公开中的术语“高纵横比”是指开口的高度-宽度比大于5。金属化工艺的实施例还可以应用于硅通孔(TSV)结构的形成。如贯穿本公开所使用的,术语“硅通孔(TSV)”是指填充有导电材料的开口,其中,导电材料穿过半导体衬底或含硅衬底的至少一部分。实施例提供了在形成TSV的过程中使用铜金属化以及使用铜电镀技术来填充高纵横比开口,以避免缝隙或空隙缺陷。如贯穿本公开所采用的,铜(Cu)是指包含元素Cu以及充分显示出Cu的电特性的Cu基合金。
以下详细参考本发明的实施例,其实例在附图中示出。在尽可能的情况下,在附图和说明书中使用相同参考标号表示相同或相似的部分。在附图中,为了清楚和方便,一个实施例的形状和厚度可以被放大。根据本发明,本说明书将特别用于形成装置的一部分或更直接地与装置协作的元件。应该明白,没有具体示出或描述的元件可以采用本领域技术人员已知的多种形式。而且,当一层被称为在另一层之上或在衬底“之上”时,其可以直接在另一层之上或衬底之上,或者还可以出现中间层。
这里,图1至图7的截面图示出了TSV工艺的示例性实施例,图8至图10的截面图示出了使用TSV结构的三维堆叠工艺的示例性实施例。
现在参考图1,其是晶圆100的截面图,晶圆100包括半导体衬底10、由衬底10处理得到的IC组件200、上覆在半导体衬底10上的层间电介质(ILD)层12以及形成在ILD层12中与IC组件200电连接的接触插塞14。具体地,衬底10通常为硅(Si),例如,具有或不具有外延层的硅衬底,或者包含绝缘埋层的绝缘体上硅衬底。衬底10具有前表面10a(例如,电路侧)和后表面10b(例如,非电路侧)。形成在衬底10的前表面10a中和/或上的IC组件200可包括多个单独的电路元件,诸如晶体管、二极管、电阻器、电容器、电感器和/或通过多种集成电路制造工艺形成的其他有源和无源半导体器件。ILD层12形成在衬底10上,以使IC组件200与随后形成的互连结构隔离。ILD层12可以是单层或多层结构。在一些实施例中,ILD层12可以是通过热CVD工艺或高密度等离子体(HDP)工艺由掺杂或未掺杂的硅氧化物形成的硅氧化物包含层,例如,未掺杂的硅酸盐玻璃(USG)、掺磷硅酸盐玻璃(PSG)或硼磷硅玻璃(BPSG)。在一些可选实施例中,ILD层12可以由掺杂的或掺杂P的旋涂玻璃(SOG)、PTEOS或BPTEOS形成。接下来执行干蚀刻工艺,在ILD层12中形成接触孔,并且沉积导电材料层以填充接触孔,形成接触插塞14。接触插塞14可包括钨、含钨合金、铜、含铜合金或它们的组合。
参考图2,工艺前进至在衬底10中形成具有大于5的高纵横比的开口18。在形成TSV结构的实施例中,开口18为TSV开口,其中将执行金属化工艺。在限定TSV开口18的过程中,硬膜层16形成在ILD层12上,之后在其上形成图案化的光刻胶层。硬膜层16可以为氮化硅层、氮氧化硅层等。图中未示出的光刻胶层通过曝光、烘焙、显影和/或其他光刻工艺被图案化,以提供露出硬膜层16的开口。然后,使用图案化的光刻胶层作为掩膜元件,通过湿蚀刻或干蚀刻工艺蚀刻露出的硬膜层16,以提供开口。使用硬膜层16和图案化的光刻胶层作为掩膜元件,执行蚀刻工艺以蚀刻露出的衬底10,形成具有侧壁18a和底部18b的TSV开口18。TSV开口18穿过半导体衬底10的至少一部分。在一些实施例中,可使用任何合适的蚀刻方法来蚀刻TSV开口18,例如等离子体蚀刻、化学湿蚀刻、激光钻孔和/或现有技术中已知的其他工艺。在一个实施例中,蚀刻工艺包括深反应离子蚀刻(RIE)工艺以蚀刻半导体衬底10。在一些实施例中,蚀刻工艺可以是使得从前表面10a开始蚀刻TSV开口18以在深度上达到几十微米(μm)至几百微米而不穿过后表面10b。蚀刻工艺可能导致具有垂直侧壁轮廓或锥形侧壁轮廓的开口。在一个实施例中,TSV开口18的深度约为20μm~100μm,直径约为1.5μm~10μm。TSV开口18具有在大约5和大约10之间的高纵横比。在一些实施例中,TSV开口18的纵横比大于10。
在图3中,钝化层20共形地沉积在所得到的结构上,以覆盖硬膜层16并对TSV开口18的侧壁18a和底部18b加衬,从而防止任何导电材料渗漏到晶圆100的电路的任何有源部分中。在一些实施例中,钝化层20可以由硅氧化物、TEOS氧化物、硅氮化物、它们的组合等形成。沉积可以使用多种技术中的任何一种来形成,包括热氧化、LPCVD(低压化学汽相沉积)、APCVD(常压化学汽相沉积)、PECVD(等离子体增强化学汽相沉积)以及未来开发的沉积处理。例如,可以采用利用正硅酸四乙酯(TEOS)和O3的LPCVD或PECVD工艺来形成TEOS氧化膜。
在图4中,然后在钝化层20上形成阻挡层22,对TSV开口18加衬。阻挡层22用作防止金属扩散的扩散势垒并且作为金属和电介质之间的粘结层。在一些实施例中,难熔金属、难熔金属氮化物、难熔金属-硅-氮化物或它们的组合通常被用于阻挡层22。例如,可以使用TaN、Ta、Ti、TiN、TiSiN、WN或它们的组合。在一个实施例中,阻挡层22包括TaN层和Ta层。在另一实施例中,阻挡层22为TiN层。在另一实施例中,阻挡层22为Ti层。随后,金属晶种层24形成在阻挡层22上。在一个实施例中,金属晶种层是可通过物理汽相沉积形成的铜晶种层24。在一些实施例中,使用用于形成铜晶种层24的其他方法(诸如CVD)。
参考图5,在沉积金属晶种层24之后执行硅化物形成工艺,以将至少一部分暴露的表面转换为金属硅化物层26。在一些实施例中,硅化物形成工艺为等离子体辅助金属硅化物形成工艺。在一个实施例中,当沉积铜晶种层24以提供与TSV开口18的侧壁18a相邻的侧壁部分24a、与TSV开口18的底部18b相邻的底部部分24b以及TSV开口18外侧的表面部分24c时,通过等离子体辅助铜硅化物形成工艺在表面部分24c和侧壁部分24a的至少一部分上形成铜硅化物层26。金属硅化物层26可以小于10埃。在以下条件下使用含硅等离子体、SiH4等离子体、Si2H6等离子体、1MS等离子体、2MS等离子体、3MS等离子体或4MS等离子体进行等离子体辅助铜硅化物形成工艺:功率约为10瓦到1000瓦,偏置功率约为0瓦至1000瓦,温度约为10℃度至800℃,时间约为0.1秒至100秒,以及压力约为1毫托至100毫托。
通过控制操作条件,诸如调节等离子体带状电子(sheet electron)的螺旋角分布或调谐等离子体工艺的偏置功率条件,金属硅化物层26可以选择性地形成在金属晶种层24的侧壁部分24a和/或表面部分24c上,而不形成在金属晶种层24的底部部分24b上。侧壁部分24a可以整体或部分起反应,以在其上形成金属硅化物层,而底部部分24b不起反应以在其上不形成铜硅化物层26。图5A示出了使用利用等离子体电子的倾斜螺旋角的等离子体处理28来形成铜硅化物层26的示例性实施例,其使得铜晶种层24的底部部分24b没有铜硅化物层26。图5B示出了使用利用等离子体电子的垂直螺旋角而没有偏置功率的等离子体处理30来形成铜硅化物层26的另一示例性实施例,其使得侧壁部分24a和表面部分24c反应以形成铜硅化物层,使底部部分24b没有铜硅化物层26。
参考图6,晶圆100被转移至电镀工具(诸如电化学电镀(ECP)工具),并且金属层32通过电镀工艺被镀在晶圆100上以填充TSV开口18。虽然在此描述了ECP工艺,但实施例不限于ECP沉积金属。金属层32可包括选自包括但不限于铜和铜基合金的组中的低阻抗导体材料。在一些可选实施例中,金属层可包括多种材料,诸如钨、铝、金、银等。在一个实施例中,金属层32为形成在铜晶种层24之上的含铜层,并且铜硅化物层26夹在它们之间。通过在铜晶种层24的侧壁部分24a上形成铜硅化物层26,铜电镀工艺可以进行得更快,并且自下而上填充TSV开口18。该电镀工艺形成了无空隙金属化结构,以提供用于填充高纵横比开口的具有高生产量的可靠解决方案。
随后,如图7所示,通过蚀刻、化学机械抛光(CMP)等去除TSV开口18外侧的金属层32、金属硅化物层26、金属晶种层24、阻挡层22、钝化层20和/或硬膜层16的多余部分,形成与电介质层12的上表面基本共面的金属填充开口的上表面。现在,晶圆100包括形成在ILD层12中并延伸穿过衬底10的一部分的TSV结构34。TSV结构34包括金属层32、围绕金属层32的金属晶种层24、围绕金属晶种层24的阻挡层22、围绕阻挡层22的钝化层20以及形成在被金属晶种层24和金属层32夹置的部分中的金属硅化物层26。
接下来,对晶圆100执行后段工艺(BEOL)互连技术,以制造如图8所示的包括多个互连层、再分布层、金属层间电介质(IMD)层36和接合接触(bonding contact)38的结构。在一个实施例中,第一层的互连层形成在IMD层中,以与接触插塞14和TSV结构34分别电连接,此后,在第一层的互连层上制造另一层的互连层和IMD层,为了清楚和方便在图中省略这些。上覆完整的顶层互连层和顶层IMD层形成接合接触38。在一些实施例中,铜基导电材料被用于形成互连层和接合接触38。铜基导电材料是指包括高纯元素铜、含不可避免杂质的铜以及含少量元素(诸如,钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆)的铜合金。可利用铜BEOL互连来使用标准镶嵌工艺。
参考图9,晶圆100然后经过晶圆薄化工艺和背侧金属化工艺。在一个实施例中,晶圆100被附着至载体,然后将衬底10的后表面10b处理成理想的最终厚度,露出TSV结构34的底端34b。这可以通过例如研磨、蚀刻和/或抛光来进行,从而得到变薄的衬底10”,其具有取决于使用半导体封装目的的预定厚度。变薄的衬底10”可具有约5μm至约180μm的厚度。在示例性实施例中,在晶圆薄化处理之后,TSV结构34的底部34b被露出和/或从变薄衬底10”的后表面10b”伸出。背侧金属化包括将电连接和/或其他结构形成在变薄的衬底10”的后表面10b”上,包括背侧介电层40和用于连接外部管芯或晶圆的接合焊盘42。在图10中,外部管芯或晶圆300被接合到晶圆100上,其中,接合方法包括氧化物-氧化物接合、氧化物-硅接合、铜-铜接合、铜-焊料接合、粘附接合或它们的组合。在一个实施例中,各个半导体芯片的外部接触44可以形成在变薄的衬底10”的后表面10b”上的接合焊盘42上,分别用于接合到电接线端。外部接触44可以为焊锡凸块、含铜凸块或它们的组合。可进一步提供多个连接元件46,以将外部管芯300接合到晶圆100上,从而形成管芯-晶圆堆叠。连接元件可以为焊锡凸块、含铜凸块或它们的组合。在一些实施例中,在切割之后,通过例如各向异性导电连接膜将堆叠的一个芯片或多个芯片安装在IC卡上。
虽然已经在优选实施例中描述了本发明,但本发明不限于在此所披露的详细实施例。本领域技术人员还可以在不脱离本发明的精神和范围的情况下,做出多种改变和修改。从而,本发明的范围将由以下权利要求及其等价物来限定和保护。
Claims (10)
1.一种器件,包括:
半导体衬底,具有前表面和后表面,并包括形成在所述前表面上的集成电路(IC)组件;
层间电介质(ILD)层,被形成为上覆所述半导体衬底的所述前表面;
接触插塞,形成在所述ILD层中,并且电连接至所述IC组件;以及
通孔结构,形成在所述ILD层中,并且延伸穿过所述半导体衬底,其中,所述通孔结构包括金属层、围绕所述金属层的金属晶种层、围绕所述金属晶种层的阻挡层以及夹置在所述金属层的至少一部分和所述金属晶种层的至少一部分之间的金属硅化物层。
2.根据权利要求1所述的器件,其中,所述金属硅化物层包括铜;或者
所述金属层包括铜,并且所述金属晶种层包括铜;或者
所述阻挡层包括TaN、Ta、TiN、Ti或它们的组合。
3.根据权利要求1所述的器件,其中,所述通孔结构包括围绕所述阻挡层的钝化层,其中,所述钝化层包括硅氧化物,或者
所述通孔结构包括在所述半导体衬底的所述后表面上露出的端部。
4.根据权利要求1所述的器件,还包括:半导体组件,堆叠在所述半导体衬底的所述后表面上并且电连接至所述通孔结构。
5.一种半导体器件,包括:
半导体衬底,具有前表面和后表面,并包括形成在所述前表面上的集成电路(IC)组件;
层间电介质(ILD)层,被形成为上覆所述半导体衬底的所述前表面;
接触插塞,形成在所述ILD层中,并且电连接至所述IC组件;以及
通孔结构,形成在所述ILD层中,并且延伸穿过所述半导体衬底;
其中,所述通孔结构包括铜层、围绕所述铜层的铜晶种层、围绕所述铜晶种层的阻挡层以及夹置在所述铜层的至少一部分和所述铜晶种层的至少一部分之间的铜硅化物层;以及
其中,所述通孔结构包括在所述半导体衬底的所述后表面上露出的端部。
6.根据权利要求5所述的半导体器件,其中,所述阻挡层包括TaN、Ta、TiN、Ti或它们的组合,或者
所述半导体器件还包括:围绕所述阻挡层的钝化层,
其中,所述钝化层包括硅氧化物。
7.根据权利要求5所述的半导体器件,还包括:
背侧介电层,被形成为上覆所述半导体衬底的所述后表面;以及
外部接触,形成在所述背侧介电层上,
其中,所述外部接触包括焊锡凸块、含铜凸块或它们的组合。
8.一种工艺,包括:
形成从半导体衬底的前表面延伸到所述半导体衬底的至少一部分的开口,其中,所述开口具有大于5的纵横比;
在所述开口中形成金属晶种层,其中,所述金属晶种层包括与所述开口的侧壁部分邻近的侧壁部分和与所述开口的底部邻近的底部部分;
在所述金属晶种层的所述侧壁部分的至少一部分上形成金属硅化物层;以及
在所述金属硅化物层和所述金属晶种层上电镀金属层,以填充所述开口。
9.根据权利要求8所述的工艺,其中,所述金属硅化物层未形成在所述金属晶种层的所述底部部分上,或者
所述金属晶种层、所述金属硅化物层和所述金属层中的每一个都包括铜。
10.根据权利要求8所述的工艺,还包括:
在形成所述金属晶种层之前,形成对所述开口加衬的阻挡层,并且在形成所述阻挡层之前,形成对所述开口加衬的钝化层;或者
对所述半导体衬底的所述后表面执行薄化工艺以露出所述金属层。
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US8846523B2 (en) | 2014-09-30 |
US8432038B2 (en) | 2013-04-30 |
US20100314758A1 (en) | 2010-12-16 |
US20130224909A1 (en) | 2013-08-29 |
CN101924096B (zh) | 2012-07-18 |
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